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From: Dan M. <da...@us...> - 2004-04-30 01:49:27
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Module Name: pcb Committed By: danmc Date: Fri Apr 30 01:49:21 UTC 2004 Modified Files: pcb/src: Pcb.ad.in action.c file.c find.c global.h macro.h main.c parse_y.y sizedialog.c Log Message: Add some DRC checking of silkscreen layers. Currently this check looks for minimum widths of silk lines. Currently not checked are: - silk polygons - silk text - wide silk lines made by overlapping several narrow silk lines To generate a diff of this commit: cvs rdiff -r1.16 -r1.17 pcb/src/Pcb.ad.in cvs rdiff -r1.40 -r1.41 pcb/src/action.c cvs rdiff -r1.15 -r1.16 pcb/src/file.c cvs rdiff -r1.26 -r1.27 pcb/src/find.c cvs rdiff -r1.18 -r1.19 pcb/src/global.h cvs rdiff -r1.12 -r1.13 pcb/src/macro.h cvs rdiff -r1.14 -r1.15 pcb/src/main.c cvs rdiff -r1.11 -r1.12 pcb/src/parse_y.y cvs rdiff -r1.6 -r1.7 pcb/src/sizedialog.c To view the diffs online visit: http://cvs.sourceforge.net/viewcvs.py/pcb/pcb/src/parse_y.y?r1=1.11&r2=1.12 http://cvs.sourceforge.net/viewcvs.py/pcb/pcb/src/macro.h?r1=1.12&r2=1.13 http://cvs.sourceforge.net/viewcvs.py/pcb/pcb/src/main.c?r1=1.14&r2=1.15 http://cvs.sourceforge.net/viewcvs.py/pcb/pcb/src/file.c?r1=1.15&r2=1.16 http://cvs.sourceforge.net/viewcvs.py/pcb/pcb/src/Pcb.ad.in?r1=1.16&r2=1.17 http://cvs.sourceforge.net/viewcvs.py/pcb/pcb/src/global.h?r1=1.18&r2=1.19 http://cvs.sourceforge.net/viewcvs.py/pcb/pcb/src/find.c?r1=1.26&r2=1.27 http://cvs.sourceforge.net/viewcvs.py/pcb/pcb/src/action.c?r1=1.40&r2=1.41 http://cvs.sourceforge.net/viewcvs.py/pcb/pcb/src/sizedialog.c?r1=1.6&r2=1.7 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. |