A tool for the design of reconfigurable systems, implemented as Eclipse Plug-In, mainly for Xilinx FPGAs using the EarlyAccess design flow. Design your system graphically, attach source files (VHDL) and automatically generate (partial) bitstreams.

Project Samples

Part-E

Project Activity

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Categories

Computer-Aided Software Engineering (CASE), Design

License

GNU General Public License version 2.0 (GPLv2)

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Additional Project Details

Operating Systems

Windows

Intended Audience

Developers

User Interface

Eclipse

Programming Language

Java

Related Categories

Java Computer-Aided Software Engineering (CASE) Software, Java Design Software

Registered

2007-01-15
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