1. New Bias Element Structure
It seems that 32 bits is sufficient for 4:1 bias and so this new structure is planned to be used http://jaxonix.blogspot.com
2. Minon Port Hardware
Will places changes in design to have a single way mux rarther than 4 way mux per 4 port pair. This requires a simple co-processor on board but allow greater flexibility.
3. Minon instruction Set
possible changes here due to the more compact representation of 32 bits for a compressed kodek.... read more
Level 1 format support defined.
Currently thinking of level 2 feature of dynamic class loading from archive, for environments supporting class loader modification.
The filed patent description is now online as a GLPL public patent. Additions relating to the diamond algorithm bias element have yet to be included. I may also be interested in publishing patent pending titled boxkey cryptographic decoder, for set top box applications if there is enough interest.
Details in project docs. Read about the reasoning behind the the core classes, and about the expected bootstrap process.
The project documentation defines the instruction set for the Minon VHDL chip design.