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<tr><td>CYCLES</td><td>	Cycles </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_1PLUS_PPC_CMPL</td><td>	one or more ppc instructions finished </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_1PLUS_PPC_DISP</td><td>	Cycles at least one Instr Dispatched </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_ANY_THRD_RUN_CYC</td><td>	One of threads in run_cycles </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_BR_MPRED_CMPL</td><td>	Number of Branch Mispredicts </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_BR_TAKEN_CMPL</td><td>	New event for Branch Taken </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_CYC</td><td>	Cycles </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_DATA_FROM_L2MISS</td><td>	Demand LD - L2 Miss (not L2 hit) </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_DATA_FROM_L3MISS</td><td>	Demand LD - L3 Miss (not L2 hit and not L3 hit) </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_DATA_FROM_MEM</td><td>	data from Memory </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_DTLB_MISS</td><td>	Data PTEG reload </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_EXT_INT</td><td>	external interrupt </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_FLOP</td><td>	Floating Point Operations Finished </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_FLUSH</td><td>	Flush (any type) </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_GCT_NOSLOT_CYC</td><td>	No itags assigned </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_IERAT_MISS</td><td>	Cycles Instruction ERAT was reloaded </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_INST_DISP</td><td>	Number of PPC Dispatched </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_INST_FROM_L3MISS</td><td>	A Instruction cacheline request resolved from a location that was beyond the local L3 cache </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_ITLB_MISS</td><td>	ITLB Reloaded (always zero on POWER6) </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_L1_DCACHE_RELOAD_VALID</td><td>	DL1 reloaded due to Demand Load </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_L1_ICACHE_MISS</td><td>	Demand iCache Miss </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_LD_MISS_L1</td><td>	Load Missed L1 </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_LSU_DERAT_MISS</td><td>	DERAT Reloaded due to a DERAT miss </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_MRK_BR_MPRED_CMPL</td><td>	Marked Branch Mispredicted </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_MRK_BR_TAKEN_CMPL</td><td>	Marked Branch Taken completed </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L2MISS</td><td>	sampled load resolved beyond L2 </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L3MISS</td><td>	sampled load resolved beyond L3 </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_MEM</td><td>	sampled load resolved from memory </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_MRK_DERAT_MISS</td><td>	Erat Miss (TLB Access) All page sizes </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_MRK_DTLB_MISS</td><td>	sampled Instruction dtlb miss </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_MRK_INST_CMPL</td><td>	Marked group complete </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_MRK_INST_DISP</td><td>	The thread has dispatched a randomly sampled marked instruction </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_MRK_INST_FROM_L3MISS</td><td>	sampled instruction missed icache and came from beyond L3 A Instruction cacheline request for a marked/sampled instruction resolved from a location that was beyond the local L3 cache </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_MRK_L1_ICACHE_MISS</td><td>	sampled Instruction suffered an icache Miss </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_MRK_L1_RELOAD_VALID</td><td>	Sampled Instruction had a data reload </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_MRK_LD_MISS_L1</td><td>	Marked DL1 Demand Miss </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_MRK_ST_CMPL</td><td>	marked store completed and sent to nest </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_RUN_CYC</td><td>	Run_cycles </td><td> 5</td><td>
</td>

</tr>

<tr><td>PM_RUN_INST_CMPL</td><td>	Run_Instructions </td><td> 4</td><td>
</td>

</tr>

<tr><td>PM_RUN_PURR</td><td>	Run_PURR </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_ST_FIN</td><td>	Store Instructions Finished </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_ST_MISS_L1</td><td>	Store Missed L1 </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_TB_BIT_TRANS</td><td>	timebase event </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_THRD_CONC_RUN_INST</td><td>	PPC Instructions Finished when both threads in run_cycles </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_THRESH_EXC_1024</td><td>	Threshold counter exceeded a value of 1024 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 1024 </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_THRESH_EXC_128</td><td>	Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 128 </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_THRESH_EXC_2048</td><td>	Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 2048 </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_THRESH_EXC_256</td><td>	Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 256 </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_THRESH_EXC_32</td><td>	Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 32 </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_THRESH_EXC_4096</td><td>	Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 4096 </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_THRESH_EXC_512</td><td>	Threshold counter exceeded a value of 512 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 512 </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_THRESH_EXC_64</td><td>	Threshold counter exceeded a value of 64 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 64 </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_THRESH_MET</td><td>	Threshold exceeded </td><td> 0</td><td>
</td>

</tr>

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