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<tr><td>CYCLES</td><td>	Processor Cycles </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_CYC_GRP1</td><td> Processor Cycles </td><td> 0</td><td>	Group 1 pm_utilization</td>

</tr>

<tr><td>PM_RUN_CYC_GRP1</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 1</td><td>	Group 1 pm_utilization</td>

</tr>

<tr><td>PM_INST_DISP_GRP1</td><td> Number of PowerPC instructions successfully dispatched. </td><td> 2</td><td>	Group 1 pm_utilization</td>

</tr>

<tr><td>PM_INST_CMPL_GRP1</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 1 pm_utilization</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP1</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 1 pm_utilization</td>

</tr>

<tr><td>PM_RUN_CYC_GRP1</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 1 pm_utilization</td>

</tr>

<tr><td>PM_BR_PRED_CCACHE_GRP2</td><td> The count value of a Branch and Count instruction was predicted </td><td> 0</td><td>	Group 2 pm_branch1</td>

</tr>

<tr><td>PM_BR_PRED_LSTACK_GRP2</td><td> The target address of a Branch to Link instruction was predicted by the link stack. </td><td> 1</td><td>	Group 2 pm_branch1</td>

</tr>

<tr><td>PM_BR_MPRED_CCACHE_GRP2</td><td> A branch instruction target was incorrectly predicted by the count cache. This will result in a branch redirect flush if not overwritten by a flush of an older instruction. </td><td> 2</td><td>	Group 2 pm_branch1</td>

</tr>

<tr><td>PM_BR_MPRED_TA_GRP2</td><td> A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction. </td><td> 3</td><td>	Group 2 pm_branch1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP2</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 2 pm_branch1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP2</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 2 pm_branch1</td>

</tr>

<tr><td>PM_BR_PRED_GRP3</td><td> A branch prediction was made. This could have been a target prediction, a condition prediction, or both </td><td> 0</td><td>	Group 3 pm_branch2</td>

</tr>

<tr><td>PM_BR_PRED_CR_GRP3</td><td> A conditional branch instruction was predicted as taken or not taken. </td><td> 1</td><td>	Group 3 pm_branch2</td>

</tr>

<tr><td>PM_BR_PRED_CCACHE_GRP3</td><td> The count value of a Branch and Count instruction was predicted </td><td> 2</td><td>	Group 3 pm_branch2</td>

</tr>

<tr><td>PM_BR_PRED_LSTACK_GRP3</td><td> The target address of a Branch to Link instruction was predicted by the link stack. </td><td> 3</td><td>	Group 3 pm_branch2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP3</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 3 pm_branch2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP3</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 3 pm_branch2</td>

</tr>

<tr><td>PM_BRU_FIN_GRP4</td><td> The Branch execution unit finished an instruction </td><td> 0</td><td>	Group 4 pm_branch3</td>

</tr>

<tr><td>PM_BR_TAKEN_GRP4</td><td> A branch instruction was taken. This could have been a conditional branch or an unconditional branch </td><td> 1</td><td>	Group 4 pm_branch3</td>

</tr>

<tr><td>PM_BR_PRED_GRP4</td><td> A branch prediction was made. This could have been a target prediction, a condition prediction, or both </td><td> 2</td><td>	Group 4 pm_branch3</td>

</tr>

<tr><td>PM_BR_MPRED_GRP4</td><td> A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both </td><td> 3</td><td>	Group 4 pm_branch3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP4</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 4 pm_branch3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP4</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 4 pm_branch3</td>

</tr>

<tr><td>PM_BR_MPRED_CR_GRP5</td><td> A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction. </td><td> 0</td><td>	Group 5 pm_branch4</td>

</tr>

<tr><td>PM_BR_UNCOND_GRP5</td><td> An unconditional branch was executed. </td><td> 1</td><td>	Group 5 pm_branch4</td>

</tr>

<tr><td>PM_BR_MPRED_TA_GRP5</td><td> A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction. </td><td> 2</td><td>	Group 5 pm_branch4</td>

</tr>

<tr><td>PM_BR_MPRED_CCACHE_GRP5</td><td> A branch instruction target was incorrectly predicted by the count cache. This will result in a branch redirect flush if not overwritten by a flush of an older instruction. </td><td> 3</td><td>	Group 5 pm_branch4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP5</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 5 pm_branch4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP5</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 5 pm_branch4</td>

</tr>

<tr><td>PM_BR_PRED_CR_TA_GRP6</td><td> Both the condition (taken or not taken) and the target address of a branch instruction was predicted. </td><td> 0</td><td>	Group 6 pm_branch5</td>

</tr>

<tr><td>PM_BR_MPRED_CR_TA_GRP6</td><td> Branch mispredict - taken/not taken and target </td><td> 1</td><td>	Group 6 pm_branch5</td>

</tr>

<tr><td>PM_BR_PRED_GRP6</td><td> A branch prediction was made. This could have been a target prediction, a condition prediction, or both </td><td> 2</td><td>	Group 6 pm_branch5</td>

</tr>

<tr><td>PM_BR_PRED_CR_GRP6</td><td> A conditional branch instruction was predicted as taken or not taken. </td><td> 3</td><td>	Group 6 pm_branch5</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP6</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 6 pm_branch5</td>

</tr>

<tr><td>PM_RUN_CYC_GRP6</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 6 pm_branch5</td>

</tr>

<tr><td>PM_BR_PRED_CCACHE_GRP7</td><td> The count value of a Branch and Count instruction was predicted </td><td> 0</td><td>	Group 7 pm_branch6</td>

</tr>

<tr><td>PM_BR_PRED_LSTACK_GRP7</td><td> The target address of a Branch to Link instruction was predicted by the link stack. </td><td> 1</td><td>	Group 7 pm_branch6</td>

</tr>

<tr><td>PM_BR_PRED_CR_GRP7</td><td> A conditional branch instruction was predicted as taken or not taken. </td><td> 2</td><td>	Group 7 pm_branch6</td>

</tr>

<tr><td>PM_BR_PRED_TA_GRP7</td><td> The target address of a branch instruction was predicted. </td><td> 3</td><td>	Group 7 pm_branch6</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP7</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 7 pm_branch6</td>

</tr>

<tr><td>PM_RUN_CYC_GRP7</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 7 pm_branch6</td>

</tr>

<tr><td>PM_BR_MPRED_CR_GRP8</td><td> A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction. </td><td> 0</td><td>	Group 8 pm_branch7</td>

</tr>

<tr><td>PM_BR_PRED_CR_GRP8</td><td> A conditional branch instruction was predicted as taken or not taken. </td><td> 1</td><td>	Group 8 pm_branch7</td>

</tr>

<tr><td>PM_BR_PRED_CCACHE_GRP8</td><td> The count value of a Branch and Count instruction was predicted </td><td> 2</td><td>	Group 8 pm_branch7</td>

</tr>

<tr><td>PM_BR_PRED_LSTACK_GRP8</td><td> The target address of a Branch to Link instruction was predicted by the link stack. </td><td> 3</td><td>	Group 8 pm_branch7</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP8</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 8 pm_branch7</td>

</tr>

<tr><td>PM_RUN_CYC_GRP8</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 8 pm_branch7</td>

</tr>

<tr><td>PM_BR_MPRED_TA_GRP9</td><td> A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction. </td><td> 0</td><td>	Group 9 pm_branch8</td>

</tr>

<tr><td>PM_BR_PRED_CR_GRP9</td><td> A conditional branch instruction was predicted as taken or not taken. </td><td> 1</td><td>	Group 9 pm_branch8</td>

</tr>

<tr><td>PM_BR_PRED_CCACHE_GRP9</td><td> The count value of a Branch and Count instruction was predicted </td><td> 2</td><td>	Group 9 pm_branch8</td>

</tr>

<tr><td>PM_BR_PRED_LSTACK_GRP9</td><td> The target address of a Branch to Link instruction was predicted by the link stack. </td><td> 3</td><td>	Group 9 pm_branch8</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP9</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 9 pm_branch8</td>

</tr>

<tr><td>PM_RUN_CYC_GRP9</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 9 pm_branch8</td>

</tr>

<tr><td>PM_BR_MPRED_CCACHE_GRP10</td><td> A branch instruction target was incorrectly predicted by the count cache. This will result in a branch redirect flush if not overwritten by a flush of an older instruction. </td><td> 0</td><td>	Group 10 pm_branch9</td>

</tr>

<tr><td>PM_BR_PRED_CR_GRP10</td><td> A conditional branch instruction was predicted as taken or not taken. </td><td> 1</td><td>	Group 10 pm_branch9</td>

</tr>

<tr><td>PM_BR_PRED_CCACHE_GRP10</td><td> The count value of a Branch and Count instruction was predicted </td><td> 2</td><td>	Group 10 pm_branch9</td>

</tr>

<tr><td>PM_BR_PRED_LSTACK_GRP10</td><td> The target address of a Branch to Link instruction was predicted by the link stack. </td><td> 3</td><td>	Group 10 pm_branch9</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP10</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 10 pm_branch9</td>

</tr>

<tr><td>PM_RUN_CYC_GRP10</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 10 pm_branch9</td>

</tr>

<tr><td>PM_IERAT_MISS_GRP11</td><td> A translation request missed the Instruction Effective to Real Address Translation (ERAT) table </td><td> 0</td><td>	Group 11 pm_slb_miss</td>

</tr>

<tr><td>PM_DSLB_MISS_GRP11</td><td> A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve. </td><td> 1</td><td>	Group 11 pm_slb_miss</td>

</tr>

<tr><td>PM_ISLB_MISS_GRP11</td><td> A SLB miss for an instruction fetch as occurred </td><td> 2</td><td>	Group 11 pm_slb_miss</td>

</tr>

<tr><td>PM_SLB_MISS_GRP11</td><td> Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data. </td><td> 3</td><td>	Group 11 pm_slb_miss</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP11</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 11 pm_slb_miss</td>

</tr>

<tr><td>PM_RUN_CYC_GRP11</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 11 pm_slb_miss</td>

</tr>

<tr><td>PM_BTAC_MISS_GRP12</td><td> BTAC Mispredicted </td><td> 0</td><td>	Group 12 pm_tlb_miss</td>

</tr>

<tr><td>PM_TLB_MISS_GRP12</td><td> Total of Data TLB mises + Instruction TLB misses </td><td> 1</td><td>	Group 12 pm_tlb_miss</td>

</tr>

<tr><td>PM_DTLB_MISS_GRP12</td><td> Data TLB misses, all page sizes. </td><td> 2</td><td>	Group 12 pm_tlb_miss</td>

</tr>

<tr><td>PM_ITLB_MISS_GRP12</td><td> A TLB miss for an Instruction Fetch has occurred </td><td> 3</td><td>	Group 12 pm_tlb_miss</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP12</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 12 pm_tlb_miss</td>

</tr>

<tr><td>PM_RUN_CYC_GRP12</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 12 pm_tlb_miss</td>

</tr>

<tr><td>PM_DTLB_MISS_16G_GRP13</td><td> Data TLB references to 16GB pages that missed the TLB. Page size is determined at TLB reload time. </td><td> 0</td><td>	Group 13 pm_dtlb_miss</td>

</tr>

<tr><td>PM_DTLB_MISS_4K_GRP13</td><td> Data TLB references to 4KB pages that missed the TLB. Page size is determined at TLB reload time. </td><td> 1</td><td>	Group 13 pm_dtlb_miss</td>

</tr>

<tr><td>PM_DTLB_MISS_64K_GRP13</td><td> Data TLB references to 64KB pages that missed the TLB. Page size is determined at TLB reload time. </td><td> 2</td><td>	Group 13 pm_dtlb_miss</td>

</tr>

<tr><td>PM_DTLB_MISS_16M_GRP13</td><td> Data TLB references to 16MB pages that missed the TLB. Page size is determined at TLB reload time. </td><td> 3</td><td>	Group 13 pm_dtlb_miss</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP13</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 13 pm_dtlb_miss</td>

</tr>

<tr><td>PM_RUN_CYC_GRP13</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 13 pm_dtlb_miss</td>

</tr>

<tr><td>PM_DERAT_MISS_4K_GRP14</td><td> A data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload. </td><td> 0</td><td>	Group 14 pm_derat_miss1</td>

</tr>

<tr><td>PM_DERAT_MISS_64K_GRP14</td><td> A data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload. </td><td> 1</td><td>	Group 14 pm_derat_miss1</td>

</tr>

<tr><td>PM_DERAT_MISS_16M_GRP14</td><td> A data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload. </td><td> 2</td><td>	Group 14 pm_derat_miss1</td>

</tr>

<tr><td>PM_DERAT_MISS_16G_GRP14</td><td> A data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload. </td><td> 3</td><td>	Group 14 pm_derat_miss1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP14</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 14 pm_derat_miss1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP14</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 14 pm_derat_miss1</td>

</tr>

<tr><td>PM_INST_CMPL_GRP15</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 15 pm_derat_miss2</td>

</tr>

<tr><td>PM_DERAT_MISS_64K_GRP15</td><td> A data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload. </td><td> 1</td><td>	Group 15 pm_derat_miss2</td>

</tr>

<tr><td>PM_DERAT_MISS_16M_GRP15</td><td> A data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload. </td><td> 2</td><td>	Group 15 pm_derat_miss2</td>

</tr>

<tr><td>PM_DERAT_MISS_16G_GRP15</td><td> A data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload. </td><td> 3</td><td>	Group 15 pm_derat_miss2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP15</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 15 pm_derat_miss2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP15</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 15 pm_derat_miss2</td>

</tr>

<tr><td>PM_DSLB_MISS_GRP16</td><td> A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve. </td><td> 0</td><td>	Group 16 pm_misc_miss1</td>

</tr>

<tr><td>PM_DATA_FROM_L2MISS_GRP16</td><td> The processor's Data Cache was reloaded but not from the local L2. </td><td> 1</td><td>	Group 16 pm_misc_miss1</td>

</tr>

<tr><td>PM_LSU_DERAT_MISS_GRP16</td><td> Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1. </td><td> 2</td><td>	Group 16 pm_misc_miss1</td>

</tr>

<tr><td>PM_LD_MISS_L1_GRP16</td><td> Load references that miss the Level 1 Data cache. Combined unit 0 + 1. </td><td> 3</td><td>	Group 16 pm_misc_miss1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP16</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 16 pm_misc_miss1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP16</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 16 pm_misc_miss1</td>

</tr>

<tr><td>PM_CYC_GRP17</td><td> Processor Cycles </td><td> 0</td><td>	Group 17 pm_misc_miss2</td>

</tr>

<tr><td>PM_PTEG_FROM_L3MISS_GRP17</td><td> Page Table Entry was loaded into the ERAT from beyond the L3 due to a demand load or store. </td><td> 1</td><td>	Group 17 pm_misc_miss2</td>

</tr>

<tr><td>PM_LSU_DERAT_MISS_GRP17</td><td> Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1. </td><td> 2</td><td>	Group 17 pm_misc_miss2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP17</td><td> Number of run instructions completed. </td><td> 3</td><td>	Group 17 pm_misc_miss2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP17</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 17 pm_misc_miss2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP17</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 17 pm_misc_miss2</td>

</tr>

<tr><td>PM_CYC_GRP18</td><td> Processor Cycles </td><td> 0</td><td>	Group 18 pm_misc_miss3</td>

</tr>

<tr><td>PM_PTEG_FROM_L3MISS_GRP18</td><td> Page Table Entry was loaded into the ERAT from beyond the L3 due to a demand load or store. </td><td> 1</td><td>	Group 18 pm_misc_miss3</td>

</tr>

<tr><td>PM_LSU_DERAT_MISS_GRP18</td><td> Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1. </td><td> 2</td><td>	Group 18 pm_misc_miss3</td>

</tr>

<tr><td>PM_PTEG_FROM_L2MISS_GRP18</td><td> A Page Table Entry was loaded into the TLB but not from the local L2. </td><td> 3</td><td>	Group 18 pm_misc_miss3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP18</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 18 pm_misc_miss3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP18</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 18 pm_misc_miss3</td>

</tr>

<tr><td>PM_DSLB_MISS_GRP19</td><td> A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve. </td><td> 0</td><td>	Group 19 pm_misc_miss4</td>

</tr>

<tr><td>PM_INST_FROM_L3MISS_GRP19</td><td> An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions. </td><td> 1</td><td>	Group 19 pm_misc_miss4</td>

</tr>

<tr><td>PM_INST_CMPL_GRP19</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 19 pm_misc_miss4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP19</td><td> Number of run instructions completed. </td><td> 3</td><td>	Group 19 pm_misc_miss4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP19</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 19 pm_misc_miss4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP19</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 19 pm_misc_miss4</td>

</tr>

<tr><td>PM_IERAT_MISS_GRP20</td><td> A translation request missed the Instruction Effective to Real Address Translation (ERAT) table </td><td> 0</td><td>	Group 20 pm_misc_miss5</td>

</tr>

<tr><td>PM_DSLB_MISS_GRP20</td><td> A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve. </td><td> 1</td><td>	Group 20 pm_misc_miss5</td>

</tr>

<tr><td>PM_ISLB_MISS_GRP20</td><td> A SLB miss for an instruction fetch as occurred </td><td> 2</td><td>	Group 20 pm_misc_miss5</td>

</tr>

<tr><td>PM_INST_CMPL_GRP20</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 20 pm_misc_miss5</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP20</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 20 pm_misc_miss5</td>

</tr>

<tr><td>PM_RUN_CYC_GRP20</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 20 pm_misc_miss5</td>

</tr>

<tr><td>PM_PTEG_FROM_L2_GRP21</td><td> A Page Table Entry was loaded into the ERAT from the local L2 due to a demand load or store. </td><td> 0</td><td>	Group 21 pm_pteg1</td>

</tr>

<tr><td>PM_INST_PTEG_FROM_L3_GRP21</td><td> Instruction PTEG loaded from L3 </td><td> 1</td><td>	Group 21 pm_pteg1</td>

</tr>

<tr><td>PM_PTEG_FROM_L21_MOD_GRP21</td><td> PTEG loaded from another L2 on same chip modified </td><td> 2</td><td>	Group 21 pm_pteg1</td>

</tr>

<tr><td>PM_INST_PTEG_FROM_DL2L3_MOD_GRP21</td><td> Instruction PTEG loaded from distant L2 or L3 modified </td><td> 3</td><td>	Group 21 pm_pteg1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP21</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 21 pm_pteg1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP21</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 21 pm_pteg1</td>

</tr>

<tr><td>PM_INST_PTEG_FROM_L2_GRP22</td><td> Instruction PTEG loaded from L2 </td><td> 0</td><td>	Group 22 pm_pteg2</td>

</tr>

<tr><td>PM_INST_PTEG_FROM_RL2L3_SHR_GRP22</td><td> Instruction PTEG loaded from remote L2 or L3 shared </td><td> 1</td><td>	Group 22 pm_pteg2</td>

</tr>

<tr><td>PM_INST_PTEG_FROM_DL2L3_SHR_GRP22</td><td> Instruction PTEG loaded from remote L2 or L3 shared </td><td> 2</td><td>	Group 22 pm_pteg2</td>

</tr>

<tr><td>PM_PTEG_FROM_DL2L3_MOD_GRP22</td><td> A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a distant module due to a demand load or store. </td><td> 3</td><td>	Group 22 pm_pteg2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP22</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 22 pm_pteg2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP22</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 22 pm_pteg2</td>

</tr>

<tr><td>PM_PTEG_FROM_L31_MOD_GRP23</td><td> PTEG loaded from another L3 on same chip modified </td><td> 0</td><td>	Group 23 pm_pteg3</td>

</tr>

<tr><td>PM_PTEG_FROM_L3MISS_GRP23</td><td> Page Table Entry was loaded into the ERAT from beyond the L3 due to a demand load or store. </td><td> 1</td><td>	Group 23 pm_pteg3</td>

</tr>

<tr><td>PM_INST_PTEG_FROM_RMEM_GRP23</td><td> Instruction PTEG loaded from remote memory </td><td> 2</td><td>	Group 23 pm_pteg3</td>

</tr>

<tr><td>PM_PTEG_FROM_LMEM_GRP23</td><td> A Page Table Entry was loaded into the TLB from memory attached to the same module this processor is located on. </td><td> 3</td><td>	Group 23 pm_pteg3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP23</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 23 pm_pteg3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP23</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 23 pm_pteg3</td>

</tr>

<tr><td>PM_INST_PTEG_FROM_RL2L3_MOD_GRP24</td><td> Instruction PTEG loaded from remote L2 or L3 modified </td><td> 0</td><td>	Group 24 pm_pteg4</td>

</tr>

<tr><td>PM_PTEG_FROM_DMEM_GRP24</td><td> A Page Table Entry was loaded into the ERAT with data from memory attached to a distant module due to a demand load or store. </td><td> 1</td><td>	Group 24 pm_pteg4</td>

</tr>

<tr><td>PM_PTEG_FROM_RMEM_GRP24</td><td> A Page Table Entry was loaded into the TLB from memory attached to a different module than this processor is located on. </td><td> 2</td><td>	Group 24 pm_pteg4</td>

</tr>

<tr><td>PM_PTEG_FROM_LMEM_GRP24</td><td> A Page Table Entry was loaded into the TLB from memory attached to the same module this processor is located on. </td><td> 3</td><td>	Group 24 pm_pteg4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP24</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 24 pm_pteg4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP24</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 24 pm_pteg4</td>

</tr>

<tr><td>PM_PTEG_FROM_RL2L3_MOD_GRP25</td><td> A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a remote module due to a demand load or store. </td><td> 0</td><td>	Group 25 pm_pteg5</td>

</tr>

<tr><td>PM_PTEG_FROM_L31_SHR_GRP25</td><td> PTEG loaded from another L3 on same chip shared </td><td> 1</td><td>	Group 25 pm_pteg5</td>

</tr>

<tr><td>PM_PTEG_FROM_DL2L3_SHR_GRP25</td><td> A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load or store. </td><td> 2</td><td>	Group 25 pm_pteg5</td>

</tr>

<tr><td>PM_PTEG_FROM_L21_SHR_GRP25</td><td> PTEG loaded from another L2 on same chip shared </td><td> 3</td><td>	Group 25 pm_pteg5</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP25</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 25 pm_pteg5</td>

</tr>

<tr><td>PM_RUN_CYC_GRP25</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 25 pm_pteg5</td>

</tr>

<tr><td>PM_INST_PTEG_FROM_L31_MOD_GRP26</td><td> Instruction PTEG loaded from another L3 on same chip modified </td><td> 0</td><td>	Group 26 pm_pteg6</td>

</tr>

<tr><td>PM_INST_PTEG_FROM_DMEM_GRP26</td><td> Instruction PTEG loaded from distant memory </td><td> 1</td><td>	Group 26 pm_pteg6</td>

</tr>

<tr><td>PM_INST_PTEG_FROM_L21_MOD_GRP26</td><td> Instruction PTEG loaded from another L2 on same chip modified </td><td> 2</td><td>	Group 26 pm_pteg6</td>

</tr>

<tr><td>PM_INST_PTEG_FROM_LMEM_GRP26</td><td> Instruction PTEG loaded from local memory </td><td> 3</td><td>	Group 26 pm_pteg6</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP26</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 26 pm_pteg6</td>

</tr>

<tr><td>PM_RUN_CYC_GRP26</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 26 pm_pteg6</td>

</tr>

<tr><td>PM_INST_PTEG_FROM_L31_MOD_GRP27</td><td> Instruction PTEG loaded from another L3 on same chip modified </td><td> 0</td><td>	Group 27 pm_pteg7</td>

</tr>

<tr><td>PM_INST_PTEG_FROM_L31_SHR_GRP27</td><td> Instruction PTEG loaded from another L3 on same chip shared </td><td> 1</td><td>	Group 27 pm_pteg7</td>

</tr>

<tr><td>PM_INST_PTEG_FROM_L21_MOD_GRP27</td><td> Instruction PTEG loaded from another L2 on same chip modified </td><td> 2</td><td>	Group 27 pm_pteg7</td>

</tr>

<tr><td>PM_INST_PTEG_FROM_L21_SHR_GRP27</td><td> Instruction PTEG loaded from another L2 on same chip shared </td><td> 3</td><td>	Group 27 pm_pteg7</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP27</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 27 pm_pteg7</td>

</tr>

<tr><td>PM_RUN_CYC_GRP27</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 27 pm_pteg7</td>

</tr>

<tr><td>PM_INST_PTEG_FROM_L2_GRP28</td><td> Instruction PTEG loaded from L2 </td><td> 0</td><td>	Group 28 pm_pteg8</td>

</tr>

<tr><td>PM_INST_PTEG_FROM_L3MISS_GRP28</td><td> Instruction PTEG loaded from L3 miss </td><td> 1</td><td>	Group 28 pm_pteg8</td>

</tr>

<tr><td>PM_INST_PTEG_FROM_RMEM_GRP28</td><td> Instruction PTEG loaded from remote memory </td><td> 2</td><td>	Group 28 pm_pteg8</td>

</tr>

<tr><td>PM_INST_PTEG_FROM_L2MISS_GRP28</td><td> Instruction PTEG loaded from L2 miss </td><td> 3</td><td>	Group 28 pm_pteg8</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP28</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 28 pm_pteg8</td>

</tr>

<tr><td>PM_RUN_CYC_GRP28</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 28 pm_pteg8</td>

</tr>

<tr><td>PM_PTEG_FROM_L2_GRP29</td><td> A Page Table Entry was loaded into the ERAT from the local L2 due to a demand load or store. </td><td> 0</td><td>	Group 29 pm_pteg9</td>

</tr>

<tr><td>PM_PTEG_FROM_L3_GRP29</td><td> A Page Table Entry was loaded into the TLB from the local L3 due to a demand load. </td><td> 1</td><td>	Group 29 pm_pteg9</td>

</tr>

<tr><td>PM_PTEG_FROM_RMEM_GRP29</td><td> A Page Table Entry was loaded into the TLB from memory attached to a different module than this processor is located on. </td><td> 2</td><td>	Group 29 pm_pteg9</td>

</tr>

<tr><td>PM_PTEG_FROM_L2MISS_GRP29</td><td> A Page Table Entry was loaded into the TLB but not from the local L2. </td><td> 3</td><td>	Group 29 pm_pteg9</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP29</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 29 pm_pteg9</td>

</tr>

<tr><td>PM_RUN_CYC_GRP29</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 29 pm_pteg9</td>

</tr>

<tr><td>PM_PTEG_FROM_L2_GRP30</td><td> A Page Table Entry was loaded into the ERAT from the local L2 due to a demand load or store. </td><td> 0</td><td>	Group 30 pm_pteg10</td>

</tr>

<tr><td>PM_PTEG_FROM_L3_GRP30</td><td> A Page Table Entry was loaded into the TLB from the local L3 due to a demand load. </td><td> 1</td><td>	Group 30 pm_pteg10</td>

</tr>

<tr><td>PM_INST_CMPL_GRP30</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 30 pm_pteg10</td>

</tr>

<tr><td>PM_CYC_GRP30</td><td> Processor Cycles </td><td> 3</td><td>	Group 30 pm_pteg10</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP30</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 30 pm_pteg10</td>

</tr>

<tr><td>PM_RUN_CYC_GRP30</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 30 pm_pteg10</td>

</tr>

<tr><td>PM_PTEG_FROM_RL2L3_MOD_GRP31</td><td> A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a remote module due to a demand load or store. </td><td> 0</td><td>	Group 31 pm_pteg11</td>

</tr>

<tr><td>PM_PTEG_FROM_RL2L3_SHR_GRP31</td><td> A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load or store. </td><td> 1</td><td>	Group 31 pm_pteg11</td>

</tr>

<tr><td>PM_INST_CMPL_GRP31</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 31 pm_pteg11</td>

</tr>

<tr><td>PM_PTEG_FROM_DL2L3_MOD_GRP31</td><td> A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a distant module due to a demand load or store. </td><td> 3</td><td>	Group 31 pm_pteg11</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP31</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 31 pm_pteg11</td>

</tr>

<tr><td>PM_RUN_CYC_GRP31</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 31 pm_pteg11</td>

</tr>

<tr><td>PM_INST_CMPL_GRP32</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 32 pm_pteg12</td>

</tr>

<tr><td>PM_PTEG_FROM_DMEM_GRP32</td><td> A Page Table Entry was loaded into the ERAT with data from memory attached to a distant module due to a demand load or store. </td><td> 1</td><td>	Group 32 pm_pteg12</td>

</tr>

<tr><td>PM_PTEG_FROM_RMEM_GRP32</td><td> A Page Table Entry was loaded into the TLB from memory attached to a different module than this processor is located on. </td><td> 2</td><td>	Group 32 pm_pteg12</td>

</tr>

<tr><td>PM_PTEG_FROM_LMEM_GRP32</td><td> A Page Table Entry was loaded into the TLB from memory attached to the same module this processor is located on. </td><td> 3</td><td>	Group 32 pm_pteg12</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP32</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 32 pm_pteg12</td>

</tr>

<tr><td>PM_RUN_CYC_GRP32</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 32 pm_pteg12</td>

</tr>

<tr><td>PM_POWER_EVENT1_GRP33</td><td> Power Management Event 1 </td><td> 0</td><td>	Group 33 pm_freq1</td>

</tr>

<tr><td>PM_DPU_HELD_POWER_GRP33</td><td> Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time </td><td> 1</td><td>	Group 33 pm_freq1</td>

</tr>

<tr><td>PM_FREQ_DOWN_GRP33</td><td> Processor frequency was slowed down due to power management </td><td> 2</td><td>	Group 33 pm_freq1</td>

</tr>

<tr><td>PM_FREQ_UP_GRP33</td><td> Processor frequency was sped up due to power management </td><td> 3</td><td>	Group 33 pm_freq1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP33</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 33 pm_freq1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP33</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 33 pm_freq1</td>

</tr>

<tr><td>PM_POWER_EVENT1_GRP34</td><td> Power Management Event 1 </td><td> 0</td><td>	Group 34 pm_freq2</td>

</tr>

<tr><td>PM_DPU_HELD_POWER_GRP34</td><td> Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time </td><td> 1</td><td>	Group 34 pm_freq2</td>

</tr>

<tr><td>PM_DISP_HELD_THERMAL_GRP34</td><td> Dispatch Held due to Thermal </td><td> 2</td><td>	Group 34 pm_freq2</td>

</tr>

<tr><td>PM_FREQ_UP_GRP34</td><td> Processor frequency was sped up due to power management </td><td> 3</td><td>	Group 34 pm_freq2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP34</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 34 pm_freq2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP34</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 34 pm_freq2</td>

</tr>

<tr><td>PM_LD_REF_L1_GRP35</td><td> L1 D cache load references counted at finish </td><td> 0</td><td>	Group 35 pm_L1_ref</td>

</tr>

<tr><td>PM_LD_REF_L1_LSU0_GRP35</td><td> Load references to Level 1 Data Cache, by unit 0. </td><td> 1</td><td>	Group 35 pm_L1_ref</td>

</tr>

<tr><td>PM_LD_REF_L1_LSU1_GRP35</td><td> Load references to Level 1 Data Cache, by unit 1. </td><td> 2</td><td>	Group 35 pm_L1_ref</td>

</tr>

<tr><td>PM_LSU_TWO_TABLEWALK_CYC_GRP35</td><td> Cycles when two tablewalks pending on this thread </td><td> 3</td><td>	Group 35 pm_L1_ref</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP35</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 35 pm_L1_ref</td>

</tr>

<tr><td>PM_RUN_CYC_GRP35</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 35 pm_L1_ref</td>

</tr>

<tr><td>PM_FLUSH_DISP_SYNC_GRP36</td><td> Dispatch Flush: Sync </td><td> 0</td><td>	Group 36 pm_flush1</td>

</tr>

<tr><td>PM_FLUSH_DISP_TLBIE_GRP36</td><td> Dispatch Flush: TLBIE </td><td> 1</td><td>	Group 36 pm_flush1</td>

</tr>

<tr><td>PM_FLUSH_DISP_SB_GRP36</td><td> Dispatch Flush: Scoreboard </td><td> 2</td><td>	Group 36 pm_flush1</td>

</tr>

<tr><td>PM_FLUSH_GRP36</td><td> Flushes occurred including LSU and Branch flushes. </td><td> 3</td><td>	Group 36 pm_flush1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP36</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 36 pm_flush1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP36</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 36 pm_flush1</td>

</tr>

<tr><td>PM_FLUSH_PARTIAL_GRP37</td><td> Partial flush </td><td> 0</td><td>	Group 37 pm_flush2</td>

</tr>

<tr><td>PM_FLUSH_DISP_GRP37</td><td> Dispatch flush </td><td> 1</td><td>	Group 37 pm_flush2</td>

</tr>

<tr><td>PM_LSU_FLUSH_GRP37</td><td> A flush was initiated by the Load Store Unit. </td><td> 2</td><td>	Group 37 pm_flush2</td>

</tr>

<tr><td>PM_LSU_PARTIAL_CDF_GRP37</td><td> A partial cacheline was returned from the L3 </td><td> 3</td><td>	Group 37 pm_flush2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP37</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 37 pm_flush2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP37</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 37 pm_flush2</td>

</tr>

<tr><td>PM_FLUSH_DISP_GRP38</td><td> Dispatch flush </td><td> 0</td><td>	Group 38 pm_flush</td>

</tr>

<tr><td>PM_CYC_GRP38</td><td> Processor Cycles </td><td> 1</td><td>	Group 38 pm_flush</td>

</tr>

<tr><td>PM_FLUSH_COMPLETION_GRP38</td><td> Completion Flush </td><td> 2</td><td>	Group 38 pm_flush</td>

</tr>

<tr><td>PM_FLUSH_GRP38</td><td> Flushes occurred including LSU and Branch flushes. </td><td> 3</td><td>	Group 38 pm_flush</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP38</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 38 pm_flush</td>

</tr>

<tr><td>PM_RUN_CYC_GRP38</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 38 pm_flush</td>

</tr>

<tr><td>PM_LSU_FLUSH_ULD_GRP39</td><td> A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1). Combined Unit 0 + 1. </td><td> 0</td><td>	Group 39 pm_lsu_flush1</td>

</tr>

<tr><td>PM_LSU_FLUSH_UST_GRP39</td><td> A store was flushed because it was unaligned (crossed a 4K boundary). Combined Unit 0 + 1. </td><td> 1</td><td>	Group 39 pm_lsu_flush1</td>

</tr>

<tr><td>PM_LSU_FLUSH_LRQ_GRP39</td><td> Load Hit Load or Store Hit Load flush. A younger load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. Combined Unit 0 + 1. </td><td> 2</td><td>	Group 39 pm_lsu_flush1</td>

</tr>

<tr><td>PM_LSU_FLUSH_SRQ_GRP39</td><td> Load Hit Store flush. A younger load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. Combined Unit 0 + 1. </td><td> 3</td><td>	Group 39 pm_lsu_flush1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP39</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 39 pm_lsu_flush1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP39</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 39 pm_lsu_flush1</td>

</tr>

<tr><td>PM_LSU_FLUSH_ULD_GRP40</td><td> A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1). Combined Unit 0 + 1. </td><td> 0</td><td>	Group 40 pm_lsu_flush2</td>

</tr>

<tr><td>PM_LSU0_FLUSH_ULD_GRP40</td><td> A load was flushed from unit 0 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1) </td><td> 1</td><td>	Group 40 pm_lsu_flush2</td>

</tr>

<tr><td>PM_LSU1_FLUSH_ULD_GRP40</td><td> A load was flushed from unit 1 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1). </td><td> 2</td><td>	Group 40 pm_lsu_flush2</td>

</tr>

<tr><td>PM_FLUSH_GRP40</td><td> Flushes occurred including LSU and Branch flushes. </td><td> 3</td><td>	Group 40 pm_lsu_flush2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP40</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 40 pm_lsu_flush2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP40</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 40 pm_lsu_flush2</td>

</tr>

<tr><td>PM_LSU_FLUSH_UST_GRP41</td><td> A store was flushed because it was unaligned (crossed a 4K boundary). Combined Unit 0 + 1. </td><td> 0</td><td>	Group 41 pm_lsu_flush3</td>

</tr>

<tr><td>PM_LSU0_FLUSH_UST_GRP41</td><td> A store was flushed from unit 0 because it was unaligned (crossed a 4K boundary). </td><td> 1</td><td>	Group 41 pm_lsu_flush3</td>

</tr>

<tr><td>PM_LSU1_FLUSH_UST_GRP41</td><td> A store was flushed from unit 1 because it was unaligned (crossed a 4K boundary) </td><td> 2</td><td>	Group 41 pm_lsu_flush3</td>

</tr>

<tr><td>PM_FLUSH_GRP41</td><td> Flushes occurred including LSU and Branch flushes. </td><td> 3</td><td>	Group 41 pm_lsu_flush3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP41</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 41 pm_lsu_flush3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP41</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 41 pm_lsu_flush3</td>

</tr>

<tr><td>PM_LSU_FLUSH_LRQ_GRP42</td><td> Load Hit Load or Store Hit Load flush. A younger load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. Combined Unit 0 + 1. </td><td> 0</td><td>	Group 42 pm_lsu_flush4</td>

</tr>

<tr><td>PM_LSU0_FLUSH_LRQ_GRP42</td><td> Load Hit Load or Store Hit Load flush. A younger load was flushed from unit 0 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. </td><td> 1</td><td>	Group 42 pm_lsu_flush4</td>

</tr>

<tr><td>PM_LSU1_FLUSH_LRQ_GRP42</td><td> Load Hit Load or Store Hit Load flush. A younger load was flushed from unit 1 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. </td><td> 2</td><td>	Group 42 pm_lsu_flush4</td>

</tr>

<tr><td>PM_FLUSH_GRP42</td><td> Flushes occurred including LSU and Branch flushes. </td><td> 3</td><td>	Group 42 pm_lsu_flush4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP42</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 42 pm_lsu_flush4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP42</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 42 pm_lsu_flush4</td>

</tr>

<tr><td>PM_LSU_FLUSH_SRQ_GRP43</td><td> Load Hit Store flush. A younger load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. Combined Unit 0 + 1. </td><td> 0</td><td>	Group 43 pm_lsu_flush5</td>

</tr>

<tr><td>PM_LSU0_FLUSH_SRQ_GRP43</td><td> Load Hit Store flush. A younger load was flushed from unit 0 because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. </td><td> 1</td><td>	Group 43 pm_lsu_flush5</td>

</tr>

<tr><td>PM_LSU1_FLUSH_SRQ_GRP43</td><td> Load Hit Store flush. A younger load was flushed from unit 1 because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. </td><td> 2</td><td>	Group 43 pm_lsu_flush5</td>

</tr>

<tr><td>PM_FLUSH_GRP43</td><td> Flushes occurred including LSU and Branch flushes. </td><td> 3</td><td>	Group 43 pm_lsu_flush5</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP43</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 43 pm_lsu_flush5</td>

</tr>

<tr><td>PM_RUN_CYC_GRP43</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 43 pm_lsu_flush5</td>

</tr>

<tr><td>PM_IC_DEMAND_CYC_GRP44</td><td> Cycles when a demand ifetch was pending </td><td> 0</td><td>	Group 44 pm_prefetch</td>

</tr>

<tr><td>PM_IC_PREF_REQ_GRP44</td><td> An instruction prefetch request has been made. </td><td> 1</td><td>	Group 44 pm_prefetch</td>

</tr>

<tr><td>PM_IC_RELOAD_SHR_GRP44</td><td> An Instruction Cache request was made by this thread and the cache line was already in the cache for the other thread. The line is marked valid for all threads. </td><td> 2</td><td>	Group 44 pm_prefetch</td>

</tr>

<tr><td>PM_IC_PREF_WRITE_GRP44</td><td> Number of Instruction Cache entries written because of prefetch. Prefetch entries are marked least recently used and are candidates for eviction if they are not needed to satify a demand fetch. </td><td> 3</td><td>	Group 44 pm_prefetch</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP44</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 44 pm_prefetch</td>

</tr>

<tr><td>PM_RUN_CYC_GRP44</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 44 pm_prefetch</td>

</tr>

<tr><td>PM_ANY_THRD_RUN_CYC_GRP45</td><td> One of threads in run_cycles </td><td> 0</td><td>	Group 45 pm_thread_cyc1</td>

</tr>

<tr><td>PM_THRD_ALL_RUN_CYC_GRP45</td><td> Cycles when all threads had their run latches set. Operating systems use the run latch to indicate when they are doing useful work. </td><td> 1</td><td>	Group 45 pm_thread_cyc1</td>

</tr>

<tr><td>PM_THRD_CONC_RUN_INST_GRP45</td><td> Instructions completed by this thread when both threads had their run latches set. </td><td> 2</td><td>	Group 45 pm_thread_cyc1</td>

</tr>

<tr><td>PM_THRD_4_RUN_CYC_GRP45</td><td> 4 thread in Run Cycles </td><td> 3</td><td>	Group 45 pm_thread_cyc1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP45</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 45 pm_thread_cyc1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP45</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 45 pm_thread_cyc1</td>

</tr>

<tr><td>PM_THRD_GRP_CMPL_BOTH_CYC_GRP46</td><td> Cycles that both threads completed. </td><td> 0</td><td>	Group 46 pm_thread_cyc2</td>

</tr>

<tr><td>PM_THRD_ALL_RUN_CYC_GRP46</td><td> Cycles when all threads had their run latches set. Operating systems use the run latch to indicate when they are doing useful work. </td><td> 1</td><td>	Group 46 pm_thread_cyc2</td>

</tr>

<tr><td>PM_THRD_CONC_RUN_INST_GRP46</td><td> Instructions completed by this thread when both threads had their run latches set. </td><td> 2</td><td>	Group 46 pm_thread_cyc2</td>

</tr>

<tr><td>PM_THRD_PRIO_0_1_CYC_GRP46</td><td> Cycles thread running at priority level 0 or 1 </td><td> 3</td><td>	Group 46 pm_thread_cyc2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP46</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 46 pm_thread_cyc2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP46</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 46 pm_thread_cyc2</td>

</tr>

<tr><td>PM_THRD_3_CONC_RUN_INST_GRP47</td><td> 3 thread Concurrent Run Instructions </td><td> 0</td><td>	Group 47 pm_thread_cyc3</td>

</tr>

<tr><td>PM_THRD_2_RUN_CYC_GRP47</td><td> 2 thread in Run Cycles </td><td> 1</td><td>	Group 47 pm_thread_cyc3</td>

</tr>

<tr><td>PM_THRD_3_RUN_CYC_GRP47</td><td> 3 thread in Run Cycles </td><td> 2</td><td>	Group 47 pm_thread_cyc3</td>

</tr>

<tr><td>PM_THRD_PRIO_4_5_CYC_GRP47</td><td> Cycles thread running at priority level 4 or 5 </td><td> 3</td><td>	Group 47 pm_thread_cyc3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP47</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 47 pm_thread_cyc3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP47</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 47 pm_thread_cyc3</td>

</tr>

<tr><td>PM_THRD_PRIO_2_3_CYC_GRP48</td><td> Cycles thread running at priority level 2 or 3 </td><td> 0</td><td>	Group 48 pm_thread_cyc4</td>

</tr>

<tr><td>PM_THRD_4_CONC_RUN_INST_GRP48</td><td> 4 thread Concurrent Run Instructions </td><td> 1</td><td>	Group 48 pm_thread_cyc4</td>

</tr>

<tr><td>PM_1THRD_CON_RUN_INSTR_GRP48</td><td> 1 thread Concurrent Run Instructions </td><td> 2</td><td>	Group 48 pm_thread_cyc4</td>

</tr>

<tr><td>PM_THRD_2_CONC_RUN_INSTR_GRP48</td><td> 2 thread Concurrent Run Instructions </td><td> 3</td><td>	Group 48 pm_thread_cyc4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP48</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 48 pm_thread_cyc4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP48</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 48 pm_thread_cyc4</td>

</tr>

<tr><td>PM_THRD_PRIO_0_1_CYC_GRP49</td><td> Cycles thread running at priority level 0 or 1 </td><td> 0</td><td>	Group 49 pm_thread_cyc5</td>

</tr>

<tr><td>PM_THRD_PRIO_2_3_CYC_GRP49</td><td> Cycles thread running at priority level 2 or 3 </td><td> 1</td><td>	Group 49 pm_thread_cyc5</td>

</tr>

<tr><td>PM_THRD_PRIO_4_5_CYC_GRP49</td><td> Cycles thread running at priority level 4 or 5 </td><td> 2</td><td>	Group 49 pm_thread_cyc5</td>

</tr>

<tr><td>PM_THRD_PRIO_6_7_CYC_GRP49</td><td> Cycles thread running at priority level 6 or 7 </td><td> 3</td><td>	Group 49 pm_thread_cyc5</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP49</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 49 pm_thread_cyc5</td>

</tr>

<tr><td>PM_RUN_CYC_GRP49</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 49 pm_thread_cyc5</td>

</tr>

<tr><td>PM_THRD_1_RUN_CYC_GRP50</td><td> At least one thread has set its run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. This event does not respect FCWAIT. </td><td> 0</td><td>	Group 50 pm_thread_cyc6</td>

</tr>

<tr><td>PM_THRD_ALL_RUN_CYC_GRP50</td><td> Cycles when all threads had their run latches set. Operating systems use the run latch to indicate when they are doing useful work. </td><td> 1</td><td>	Group 50 pm_thread_cyc6</td>

</tr>

<tr><td>PM_THRD_CONC_RUN_INST_GRP50</td><td> Instructions completed by this thread when both threads had their run latches set. </td><td> 2</td><td>	Group 50 pm_thread_cyc6</td>

</tr>

<tr><td>PM_THRD_4_RUN_CYC_GRP50</td><td> 4 thread in Run Cycles </td><td> 3</td><td>	Group 50 pm_thread_cyc6</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP50</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 50 pm_thread_cyc6</td>

</tr>

<tr><td>PM_RUN_CYC_GRP50</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 50 pm_thread_cyc6</td>

</tr>

<tr><td>PM_FXU_IDLE_GRP51</td><td> FXU0 and FXU1 are both idle. </td><td> 0</td><td>	Group 51 pm_fxu1</td>

</tr>

<tr><td>PM_FXU_BUSY_GRP51</td><td> Cycles when both FXU0 and FXU1 are busy. </td><td> 1</td><td>	Group 51 pm_fxu1</td>

</tr>

<tr><td>PM_FXU0_BUSY_FXU1_IDLE_GRP51</td><td> FXU0 is busy while FXU1 was idle </td><td> 2</td><td>	Group 51 pm_fxu1</td>

</tr>

<tr><td>PM_FXU1_BUSY_FXU0_IDLE_GRP51</td><td> FXU0 was idle while FXU1 was busy </td><td> 3</td><td>	Group 51 pm_fxu1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP51</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 51 pm_fxu1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP51</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 51 pm_fxu1</td>

</tr>

<tr><td>PM_FXU0_FIN_GRP52</td><td> The Fixed Point unit 0 finished an instruction and produced a result. Instructions that finish may not necessary complete. </td><td> 0</td><td>	Group 52 pm_fxu2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP52</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 1</td><td>	Group 52 pm_fxu2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP52</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 52 pm_fxu2</td>

</tr>

<tr><td>PM_FXU1_FIN_GRP52</td><td> The Fixed Point unit 1 finished an instruction and produced a result. Instructions that finish may not necessary complete. </td><td> 3</td><td>	Group 52 pm_fxu2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP52</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 52 pm_fxu2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP52</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 52 pm_fxu2</td>

</tr>

<tr><td>PM_CYC_GRP53</td><td> Processor Cycles </td><td> 0</td><td>	Group 53 pm_fxu3</td>

</tr>

<tr><td>PM_FXU_BUSY_GRP53</td><td> Cycles when both FXU0 and FXU1 are busy. </td><td> 1</td><td>	Group 53 pm_fxu3</td>

</tr>

<tr><td>PM_FXU0_BUSY_FXU1_IDLE_GRP53</td><td> FXU0 is busy while FXU1 was idle </td><td> 2</td><td>	Group 53 pm_fxu3</td>

</tr>

<tr><td>PM_FXU1_BUSY_FXU0_IDLE_GRP53</td><td> FXU0 was idle while FXU1 was busy </td><td> 3</td><td>	Group 53 pm_fxu3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP53</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 53 pm_fxu3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP53</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 53 pm_fxu3</td>

</tr>

<tr><td>PM_FXU_IDLE_GRP54</td><td> FXU0 and FXU1 are both idle. </td><td> 0</td><td>	Group 54 pm_fxu4</td>

</tr>

<tr><td>PM_FXU_BUSY_GRP54</td><td> Cycles when both FXU0 and FXU1 are busy. </td><td> 1</td><td>	Group 54 pm_fxu4</td>

</tr>

<tr><td>PM_CYC_GRP54</td><td> Processor Cycles </td><td> 2</td><td>	Group 54 pm_fxu4</td>

</tr>

<tr><td>PM_INST_CMPL_GRP54</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 54 pm_fxu4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP54</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 54 pm_fxu4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP54</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 54 pm_fxu4</td>

</tr>

<tr><td>PM_L2_RCLD_DISP_GRP55</td><td> L2 RC load dispatch attempt </td><td> 0</td><td>	Group 55 pm_L2_RCLD</td>

</tr>

<tr><td>PM_L2_RCLD_DISP_FAIL_OTHER_GRP55</td><td> L2 RC load dispatch attempt failed due to other reasons </td><td> 1</td><td>	Group 55 pm_L2_RCLD</td>

</tr>

<tr><td>PM_L2_RCST_DISP_GRP55</td><td> L2 RC store dispatch attempt </td><td> 2</td><td>	Group 55 pm_L2_RCLD</td>

</tr>

<tr><td>PM_L2_RCLD_BUSY_RC_FULL_GRP55</td><td> L2 activated Busy to the core for loads due to all RC full </td><td> 3</td><td>	Group 55 pm_L2_RCLD</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP55</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 55 pm_L2_RCLD</td>

</tr>

<tr><td>PM_RUN_CYC_GRP55</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 55 pm_L2_RCLD</td>

</tr>

<tr><td>PM_L2_CO_FAIL_BUSY_GRP56</td><td> L2 RC Cast Out dispatch attempt failed due to all CO machines busy </td><td> 0</td><td>	Group 56 pm_L2_RC</td>

</tr>

<tr><td>PM_CYC_GRP56</td><td> Processor Cycles </td><td> 1</td><td>	Group 56 pm_L2_RC</td>

</tr>

<tr><td>PM_L2_RC_ST_DONE_GRP56</td><td> RC did st to line that was Tx or Sx </td><td> 2</td><td>	Group 56 pm_L2_RC</td>

</tr>

<tr><td>PM_INST_CMPL_GRP56</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 56 pm_L2_RC</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP56</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 56 pm_L2_RC</td>

</tr>

<tr><td>PM_RUN_CYC_GRP56</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 56 pm_L2_RC</td>

</tr>

<tr><td>PM_L2_RCLD_DISP_GRP57</td><td> L2 RC load dispatch attempt </td><td> 0</td><td>	Group 57 pm_L2_RCST</td>

</tr>

<tr><td>PM_L2_RCLD_DISP_FAIL_OTHER_GRP57</td><td> L2 RC load dispatch attempt failed due to other reasons </td><td> 1</td><td>	Group 57 pm_L2_RCST</td>

</tr>

<tr><td>PM_L2_RCST_DISP_FAIL_ADDR_GRP57</td><td> L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ </td><td> 2</td><td>	Group 57 pm_L2_RCST</td>

</tr>

<tr><td>PM_L2_RCST_DISP_FAIL_OTHER_GRP57</td><td> L2 RC store dispatch attempt failed due to other reasons </td><td> 3</td><td>	Group 57 pm_L2_RCST</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP57</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 57 pm_L2_RCST</td>

</tr>

<tr><td>PM_RUN_CYC_GRP57</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 57 pm_L2_RCST</td>

</tr>

<tr><td>PM_L2_ST_GRP58</td><td> Data Store Count </td><td> 0</td><td>	Group 58 pm_L2_ldst_1</td>

</tr>

<tr><td>PM_L2_LD_MISS_GRP58</td><td> Data Load Miss </td><td> 1</td><td>	Group 58 pm_L2_ldst_1</td>

</tr>

<tr><td>PM_INST_CMPL_GRP58</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 58 pm_L2_ldst_1</td>

</tr>

<tr><td>PM_CYC_GRP58</td><td> Processor Cycles </td><td> 3</td><td>	Group 58 pm_L2_ldst_1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP58</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 58 pm_L2_ldst_1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP58</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 58 pm_L2_ldst_1</td>

</tr>

<tr><td>PM_INST_CMPL_GRP59</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 59 pm_L2_ldst_2</td>

</tr>

<tr><td>PM_CYC_GRP59</td><td> Processor Cycles </td><td> 1</td><td>	Group 59 pm_L2_ldst_2</td>

</tr>

<tr><td>PM_L2_LD_HIT_GRP59</td><td> A load request (data or instruction) hit in the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Total for all slices </td><td> 2</td><td>	Group 59 pm_L2_ldst_2</td>

</tr>

<tr><td>PM_L2_ST_HIT_GRP59</td><td> A store request hit in the L2 directory. This event includes all requests to this L2 from all sources. Total for all slices. </td><td> 3</td><td>	Group 59 pm_L2_ldst_2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP59</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 59 pm_L2_ldst_2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP59</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 59 pm_L2_ldst_2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP60</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 60 pm_L2_ldst_3</td>

</tr>

<tr><td>PM_CYC_GRP60</td><td> Processor Cycles </td><td> 1</td><td>	Group 60 pm_L2_ldst_3</td>

</tr>

<tr><td>PM_L2_LD_DISP_GRP60</td><td> All successful load dispatches </td><td> 2</td><td>	Group 60 pm_L2_ldst_3</td>

</tr>

<tr><td>PM_L2_ST_DISP_GRP60</td><td> All successful store dispatches </td><td> 3</td><td>	Group 60 pm_L2_ldst_3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP60</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 60 pm_L2_ldst_3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP60</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 60 pm_L2_ldst_3</td>

</tr>

<tr><td>PM_L2_RCLD_DISP_FAIL_ADDR_GRP61</td><td> L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ </td><td> 0</td><td>	Group 61 pm_L2_RCSTLD</td>

</tr>

<tr><td>PM_L2_RCST_BUSY_RC_FULL_GRP61</td><td> L2 activated Busy to the core for stores due to all RC full </td><td> 1</td><td>	Group 61 pm_L2_RCSTLD</td>

</tr>

<tr><td>PM_INST_CMPL_GRP61</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 61 pm_L2_RCSTLD</td>

</tr>

<tr><td>PM_CYC_GRP61</td><td> Processor Cycles </td><td> 3</td><td>	Group 61 pm_L2_RCSTLD</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP61</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 61 pm_L2_RCSTLD</td>

</tr>

<tr><td>PM_RUN_CYC_GRP61</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 61 pm_L2_RCSTLD</td>

</tr>

<tr><td>PM_PB_NODE_PUMP_GRP62</td><td> Nest events (MC0/MC1/PB/GX), Pair0 Bit0 </td><td> 0</td><td>	Group 62 pm_nest1</td>

</tr>

<tr><td>PM_PB_SYS_PUMP_GRP62</td><td> Nest events (MC0/MC1/PB/GX), Pair1 Bit0 </td><td> 1</td><td>	Group 62 pm_nest1</td>

</tr>

<tr><td>PM_PB_RETRY_NODE_PUMP_GRP62</td><td> Nest events (MC0/MC1/PB/GX), Pair2 Bit0 </td><td> 2</td><td>	Group 62 pm_nest1</td>

</tr>

<tr><td>PM_PB_RETRY_SYS_PUMP_GRP62</td><td> Nest events (MC0/MC1/PB/GX), Pair3 Bit0 </td><td> 3</td><td>	Group 62 pm_nest1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP62</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 62 pm_nest1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP62</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 62 pm_nest1</td>

</tr>

<tr><td>PM_MEM0_RQ_DISP_GRP63</td><td> Nest events (MC0/MC1/PB/GX), Pair0 Bit1 </td><td> 0</td><td>	Group 63 pm_nest2</td>

</tr>

<tr><td>PM_MEM0_PREFETCH_DISP_GRP63</td><td> Nest events (MC0/MC1/PB/GX), Pair1 Bit1 </td><td> 1</td><td>	Group 63 pm_nest2</td>

</tr>

<tr><td>PM_MEM0_PB_RD_CL_GRP63</td><td> Nest events (MC0/MC1/PB/GX), Pair2 Bit1 </td><td> 2</td><td>	Group 63 pm_nest2</td>

</tr>

<tr><td>PM_MEM0_WQ_DISP_GRP63</td><td> Nest events (MC0/MC1/PB/GX), Pair3 Bit1 </td><td> 3</td><td>	Group 63 pm_nest2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP63</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 63 pm_nest2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP63</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 63 pm_nest2</td>

</tr>

<tr><td>PM_NEST_PAIR0_ADD_GRP64</td><td> Nest events (MC0/MC1/PB/GX), Pair0 ADD </td><td> 0</td><td>	Group 64 pm_nest3</td>

</tr>

<tr><td>PM_NEST_PAIR1_ADD_GRP64</td><td> Nest events (MC0/MC1/PB/GX), Pair1 ADD </td><td> 1</td><td>	Group 64 pm_nest3</td>

</tr>

<tr><td>PM_NEST_PAIR2_ADD_GRP64</td><td> Nest events (MC0/MC1/PB/GX), Pair2 ADD </td><td> 2</td><td>	Group 64 pm_nest3</td>

</tr>

<tr><td>PM_NEST_PAIR3_ADD_GRP64</td><td> Nest events (MC0/MC1/PB/GX), Pair3 ADD </td><td> 3</td><td>	Group 64 pm_nest3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP64</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 64 pm_nest3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP64</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 64 pm_nest3</td>

</tr>

<tr><td>PM_NEST_PAIR0_AND_GRP65</td><td> Nest events (MC0/MC1/PB/GX), Pair0 AND </td><td> 0</td><td>	Group 65 pm_nest4</td>

</tr>

<tr><td>PM_NEST_PAIR1_AND_GRP65</td><td> Nest events (MC0/MC1/PB/GX), Pair1 AND </td><td> 1</td><td>	Group 65 pm_nest4</td>

</tr>

<tr><td>PM_NEST_PAIR2_AND_GRP65</td><td> Nest events (MC0/MC1/PB/GX), Pair2 AND </td><td> 2</td><td>	Group 65 pm_nest4</td>

</tr>

<tr><td>PM_NEST_PAIR3_AND_GRP65</td><td> Nest events (MC0/MC1/PB/GX), Pair3 AND </td><td> 3</td><td>	Group 65 pm_nest4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP65</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 65 pm_nest4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP65</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 65 pm_nest4</td>

</tr>

<tr><td>PM_IC_DEMAND_L2_BHT_REDIRECT_GRP66</td><td> A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict). </td><td> 0</td><td>	Group 66 pm_L2_redir_pref</td>

</tr>

<tr><td>PM_IC_DEMAND_L2_BR_REDIRECT_GRP66</td><td> A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target). </td><td> 1</td><td>	Group 66 pm_L2_redir_pref</td>

</tr>

<tr><td>PM_IC_DEMAND_REQ_GRP66</td><td> Demand Instruction fetch request </td><td> 2</td><td>	Group 66 pm_L2_redir_pref</td>

</tr>

<tr><td>PM_IC_BANK_CONFLICT_GRP66</td><td> Read blocked due to interleave conflict. </td><td> 3</td><td>	Group 66 pm_L2_redir_pref</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP66</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 66 pm_L2_redir_pref</td>

</tr>

<tr><td>PM_RUN_CYC_GRP66</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 66 pm_L2_redir_pref</td>

</tr>

<tr><td>PM_DATA_FROM_L2_GRP67</td><td> The processor's Data Cache was reloaded from the local L2 due to a demand load. </td><td> 0</td><td>	Group 67 pm_dlatencies1</td>

</tr>

<tr><td>PM_INST_DISP_GRP67</td><td> Number of PowerPC instructions successfully dispatched. </td><td> 1</td><td>	Group 67 pm_dlatencies1</td>

</tr>

<tr><td>PM_L1_DCACHE_RELOAD_VALID_GRP67</td><td> The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads. </td><td> 2</td><td>	Group 67 pm_dlatencies1</td>

</tr>

<tr><td>PM_1PLUS_PPC_DISP_GRP67</td><td> A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once. </td><td> 3</td><td>	Group 67 pm_dlatencies1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP67</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 67 pm_dlatencies1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP67</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 67 pm_dlatencies1</td>

</tr>

<tr><td>PM_DATA_FROM_L3_GRP68</td><td> The processor's Data Cache was reloaded from the local L3 due to a demand load. </td><td> 0</td><td>	Group 68 pm_dlatencies2</td>

</tr>

<tr><td>PM_CYC_GRP68</td><td> Processor Cycles </td><td> 1</td><td>	Group 68 pm_dlatencies2</td>

</tr>

<tr><td>PM_L1_DCACHE_RELOAD_VALID_GRP68</td><td> The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads. </td><td> 2</td><td>	Group 68 pm_dlatencies2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP68</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 68 pm_dlatencies2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP68</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 68 pm_dlatencies2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP68</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 68 pm_dlatencies2</td>

</tr>

<tr><td>PM_DATA_FROM_RL2L3_MOD_GRP69</td><td> The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a demand load </td><td> 0</td><td>	Group 69 pm_dlatencies3</td>

</tr>

<tr><td>PM_DATA_FROM_RL2L3_SHR_GRP69</td><td> The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load </td><td> 1</td><td>	Group 69 pm_dlatencies3</td>

</tr>

<tr><td>PM_L1_DCACHE_RELOAD_VALID_GRP69</td><td> The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads. </td><td> 2</td><td>	Group 69 pm_dlatencies3</td>

</tr>

<tr><td>PM_INST_CMPL_GRP69</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 69 pm_dlatencies3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP69</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 69 pm_dlatencies3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP69</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 69 pm_dlatencies3</td>

</tr>

<tr><td>PM_LSU_REJECT_GRP70</td><td> The Load Store Unit rejected an instruction. Combined Unit 0 + 1 </td><td> 0</td><td>	Group 70 pm_rejects1</td>

</tr>

<tr><td>PM_LSU0_REJECT_LHS_GRP70</td><td> Load Store Unit 0 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. </td><td> 1</td><td>	Group 70 pm_rejects1</td>

</tr>

<tr><td>PM_LSU1_REJECT_LHS_GRP70</td><td> Load Store Unit 1 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. </td><td> 2</td><td>	Group 70 pm_rejects1</td>

</tr>

<tr><td>PM_LSU_REJECT_LHS_GRP70</td><td> The Load Store Unit rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. Combined Unit 0 + 1 </td><td> 3</td><td>	Group 70 pm_rejects1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP70</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 70 pm_rejects1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP70</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 70 pm_rejects1</td>

</tr>

<tr><td>PM_LSU_REJECT_GRP71</td><td> The Load Store Unit rejected an instruction. Combined Unit 0 + 1 </td><td> 0</td><td>	Group 71 pm_rejects2</td>

</tr>

<tr><td>PM_LSU_REJECT_ERAT_MISS_GRP71</td><td> Total cycles the Load Store Unit is busy rejecting instructions due to an ERAT miss. Combined unit 0 + 1. Requests that miss the Derat are rejected and retried until the request hits in the Erat. </td><td> 1</td><td>	Group 71 pm_rejects2</td>

</tr>

<tr><td>PM_LSU_REJECT_SET_MPRED_GRP71</td><td> The Load Store Unit rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1 </td><td> 2</td><td>	Group 71 pm_rejects2</td>

</tr>

<tr><td>PM_LSU_SRQ_EMPTY_CYC_GRP71</td><td> The Store Request Queue is empty </td><td> 3</td><td>	Group 71 pm_rejects2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP71</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 71 pm_rejects2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP71</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 71 pm_rejects2</td>

</tr>

<tr><td>PM_LSU_REJECT_SET_MPRED_GRP72</td><td> The Load Store Unit rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1 </td><td> 0</td><td>	Group 72 pm_rejects3</td>

</tr>

<tr><td>PM_LSU_SET_MPRED_GRP72</td><td> Line already in cache at reload time </td><td> 1</td><td>	Group 72 pm_rejects3</td>

</tr>

<tr><td>PM_CYC_GRP72</td><td> Processor Cycles </td><td> 2</td><td>	Group 72 pm_rejects3</td>

</tr>

<tr><td>PM_INST_CMPL_GRP72</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 72 pm_rejects3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP72</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 72 pm_rejects3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP72</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 72 pm_rejects3</td>

</tr>

<tr><td>PM_LSU_REJECT_LMQ_FULL_GRP73</td><td> Total cycles the Load Store Unit is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all the eight entries are full, subsequent load instructions are rejected. Combined unit 0 + 1. </td><td> 0</td><td>	Group 73 pm_lsu_reject</td>

</tr>

<tr><td>PM_LSU0_REJECT_LMQ_FULL_GRP73</td><td> Total cycles the Load Store Unit 0 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected. </td><td> 1</td><td>	Group 73 pm_lsu_reject</td>

</tr>

<tr><td>PM_LSU1_REJECT_LMQ_FULL_GRP73</td><td> Total cycles the Load Store Unit 1 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected. </td><td> 2</td><td>	Group 73 pm_lsu_reject</td>

</tr>

<tr><td>PM_INST_CMPL_GRP73</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 73 pm_lsu_reject</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP73</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 73 pm_lsu_reject</td>

</tr>

<tr><td>PM_RUN_CYC_GRP73</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 73 pm_lsu_reject</td>

</tr>

<tr><td>PM_LSU_NCLD_GRP74</td><td> A non-cacheable load was executed. Combined Unit 0 + 1. </td><td> 0</td><td>	Group 74 pm_lsu_ncld</td>

</tr>

<tr><td>PM_LSU0_NCLD_GRP74</td><td> A non-cacheable load was executed by unit 0. </td><td> 1</td><td>	Group 74 pm_lsu_ncld</td>

</tr>

<tr><td>PM_LSU1_NCLD_GRP74</td><td> A non-cacheable load was executed by Unit 0. </td><td> 2</td><td>	Group 74 pm_lsu_ncld</td>

</tr>

<tr><td>PM_INST_CMPL_GRP74</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 74 pm_lsu_ncld</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP74</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 74 pm_lsu_ncld</td>

</tr>

<tr><td>PM_RUN_CYC_GRP74</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 74 pm_lsu_ncld</td>

</tr>

<tr><td>PM_GCT_NOSLOT_CYC_GRP75</td><td> Cycles when the Global Completion Table has no slots from this thread. </td><td> 0</td><td>	Group 75 pm_gct1</td>

</tr>

<tr><td>PM_GCT_EMPTY_CYC_GRP75</td><td> Cycles when the Global Completion Table was completely empty. No thread had an entry allocated. </td><td> 1</td><td>	Group 75 pm_gct1</td>

</tr>

<tr><td>PM_GCT_FULL_CYC_GRP75</td><td> The Global Completion Table is completely full. </td><td> 2</td><td>	Group 75 pm_gct1</td>

</tr>

<tr><td>PM_CYC_GRP75</td><td> Processor Cycles </td><td> 3</td><td>	Group 75 pm_gct1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP75</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 75 pm_gct1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP75</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 75 pm_gct1</td>

</tr>

<tr><td>PM_GCT_UTIL_1_TO_2_SLOTS_GRP76</td><td> GCT Utilization 1-2 entries </td><td> 0</td><td>	Group 76 pm_gct2</td>

</tr>

<tr><td>PM_GCT_UTIL_3_TO_6_SLOTS_GRP76</td><td> GCT Utilization 3-6 entries </td><td> 1</td><td>	Group 76 pm_gct2</td>

</tr>

<tr><td>PM_GCT_UTIL_7_TO_10_SLOTS_GRP76</td><td> GCT Utilization 7-10 entries </td><td> 2</td><td>	Group 76 pm_gct2</td>

</tr>

<tr><td>PM_GCT_UTIL_11_PLUS_SLOTS_GRP76</td><td> GCT Utilization 11+ entries </td><td> 3</td><td>	Group 76 pm_gct2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP76</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 76 pm_gct2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP76</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 76 pm_gct2</td>

</tr>

<tr><td>PM_L2_CASTOUT_MOD_GRP77</td><td> An L2 line in the Modified state was castout. Total for all slices. </td><td> 0</td><td>	Group 77 pm_L2_castout_invalidate_1</td>

</tr>

<tr><td>PM_L2_DC_INV_GRP77</td><td> The L2 invalidated a line in processor's data cache. This is caused by the L2 line being cast out or invalidated. Total for all slices </td><td> 1</td><td>	Group 77 pm_L2_castout_invalidate_1</td>

</tr>

<tr><td>PM_INST_CMPL_GRP77</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 77 pm_L2_castout_invalidate_1</td>

</tr>

<tr><td>PM_CYC_GRP77</td><td> Processor Cycles </td><td> 3</td><td>	Group 77 pm_L2_castout_invalidate_1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP77</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 77 pm_L2_castout_invalidate_1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP77</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 77 pm_L2_castout_invalidate_1</td>

</tr>

<tr><td>PM_L2_CASTOUT_SHR_GRP78</td><td> An L2 line in the Shared state was castout. Total for all slices. </td><td> 0</td><td>	Group 78 pm_L2_castout_invalidate_2</td>

</tr>

<tr><td>PM_L2_IC_INV_GRP78</td><td> Icache Invalidates from L2 </td><td> 1</td><td>	Group 78 pm_L2_castout_invalidate_2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP78</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 78 pm_L2_castout_invalidate_2</td>

</tr>

<tr><td>PM_CYC_GRP78</td><td> Processor Cycles </td><td> 3</td><td>	Group 78 pm_L2_castout_invalidate_2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP78</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 78 pm_L2_castout_invalidate_2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP78</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 78 pm_L2_castout_invalidate_2</td>

</tr>

<tr><td>PM_DISP_HELD_GRP79</td><td> Dispatch Held </td><td> 0</td><td>	Group 79 pm_disp_held1</td>

</tr>

<tr><td>PM_DPU_HELD_POWER_GRP79</td><td> Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time </td><td> 1</td><td>	Group 79 pm_disp_held1</td>

</tr>

<tr><td>PM_DISP_HELD_THERMAL_GRP79</td><td> Dispatch Held due to Thermal </td><td> 2</td><td>	Group 79 pm_disp_held1</td>

</tr>

<tr><td>PM_1PLUS_PPC_DISP_GRP79</td><td> A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once. </td><td> 3</td><td>	Group 79 pm_disp_held1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP79</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 79 pm_disp_held1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP79</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 79 pm_disp_held1</td>

</tr>

<tr><td>PM_THERMAL_WARN_GRP80</td><td> Processor in Thermal Warning </td><td> 0</td><td>	Group 80 pm_disp_held2</td>

</tr>

<tr><td>PM_DPU_HELD_POWER_GRP80</td><td> Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time </td><td> 1</td><td>	Group 80 pm_disp_held2</td>

</tr>

<tr><td>PM_DISP_HELD_THERMAL_GRP80</td><td> Dispatch Held due to Thermal </td><td> 2</td><td>	Group 80 pm_disp_held2</td>

</tr>

<tr><td>PM_THERMAL_MAX_GRP80</td><td> The processor experienced a thermal overload condition. This bit is sticky, it remains set until cleared by software. </td><td> 3</td><td>	Group 80 pm_disp_held2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP80</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 80 pm_disp_held2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP80</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 80 pm_disp_held2</td>

</tr>

<tr><td>PM_DISP_CLB_HELD_BAL_GRP81</td><td> Dispatch/CLB Hold: Balance </td><td> 0</td><td>	Group 81 pm_disp_clb_held</td>

</tr>

<tr><td>PM_DISP_CLB_HELD_RES_GRP81</td><td> Dispatch/CLB Hold: Resource </td><td> 1</td><td>	Group 81 pm_disp_clb_held</td>

</tr>

<tr><td>PM_DISP_CLB_HELD_TLBIE_GRP81</td><td> Dispatch Hold: Due to TLBIE </td><td> 2</td><td>	Group 81 pm_disp_clb_held</td>

</tr>

<tr><td>PM_DISP_CLB_HELD_SYNC_GRP81</td><td> Dispatch/CLB Hold: Sync type instruction </td><td> 3</td><td>	Group 81 pm_disp_clb_held</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP81</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 81 pm_disp_clb_held</td>

</tr>

<tr><td>PM_RUN_CYC_GRP81</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 81 pm_disp_clb_held</td>

</tr>

<tr><td>PM_POWER_EVENT1_GRP82</td><td> Power Management Event 1 </td><td> 0</td><td>	Group 82 pm_power</td>

</tr>

<tr><td>PM_POWER_EVENT2_GRP82</td><td> Power Management Event 2 </td><td> 1</td><td>	Group 82 pm_power</td>

</tr>

<tr><td>PM_POWER_EVENT3_GRP82</td><td> Power Management Event 3 </td><td> 2</td><td>	Group 82 pm_power</td>

</tr>

<tr><td>PM_POWER_EVENT4_GRP82</td><td> Power Management Event 4 </td><td> 3</td><td>	Group 82 pm_power</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP82</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 82 pm_power</td>

</tr>

<tr><td>PM_RUN_CYC_GRP82</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 82 pm_power</td>

</tr>

<tr><td>PM_1PLUS_PPC_CMPL_GRP83</td><td> A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once. </td><td> 0</td><td>	Group 83 pm_dispatch1</td>

</tr>

<tr><td>PM_INST_DISP_GRP83</td><td> Number of PowerPC instructions successfully dispatched. </td><td> 1</td><td>	Group 83 pm_dispatch1</td>

</tr>

<tr><td>PM_GRP_DISP_GRP83</td><td> A group was dispatched </td><td> 2</td><td>	Group 83 pm_dispatch1</td>

</tr>

<tr><td>PM_1PLUS_PPC_DISP_GRP83</td><td> A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once. </td><td> 3</td><td>	Group 83 pm_dispatch1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP83</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 83 pm_dispatch1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP83</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 83 pm_dispatch1</td>

</tr>

<tr><td>PM_1PLUS_PPC_CMPL_GRP84</td><td> A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once. </td><td> 0</td><td>	Group 84 pm_dispatch2</td>

</tr>

<tr><td>PM_CYC_GRP84</td><td> Processor Cycles </td><td> 1</td><td>	Group 84 pm_dispatch2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP84</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 84 pm_dispatch2</td>

</tr>

<tr><td>PM_1PLUS_PPC_DISP_GRP84</td><td> A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once. </td><td> 3</td><td>	Group 84 pm_dispatch2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP84</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 84 pm_dispatch2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP84</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 84 pm_dispatch2</td>

</tr>

<tr><td>PM_IC_REQ_ALL_GRP85</td><td> Icache requests, prefetch + demand </td><td> 0</td><td>	Group 85 pm_ic</td>

</tr>

<tr><td>PM_IC_WRITE_ALL_GRP85</td><td> Icache sectors written, prefetch + demand </td><td> 1</td><td>	Group 85 pm_ic</td>

</tr>

<tr><td>PM_IC_PREF_CANCEL_ALL_GRP85</td><td> Prefetch Canceled due to page boundary or icache hit </td><td> 2</td><td>	Group 85 pm_ic</td>

</tr>

<tr><td>PM_IC_DEMAND_L2_BR_ALL_GRP85</td><td> L2 I cache demand request due to BHT or redirect </td><td> 3</td><td>	Group 85 pm_ic</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP85</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 85 pm_ic</td>

</tr>

<tr><td>PM_RUN_CYC_GRP85</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 85 pm_ic</td>

</tr>

<tr><td>PM_IC_PREF_CANCEL_PAGE_GRP86</td><td> Prefetch Canceled due to page boundary </td><td> 0</td><td>	Group 86 pm_ic_pref_cancel</td>

</tr>

<tr><td>PM_IC_PREF_CANCEL_HIT_GRP86</td><td> Prefetch Canceled due to icache hit </td><td> 1</td><td>	Group 86 pm_ic_pref_cancel</td>

</tr>

<tr><td>PM_IC_PREF_CANCEL_L2_GRP86</td><td> L2 Squashed request </td><td> 2</td><td>	Group 86 pm_ic_pref_cancel</td>

</tr>

<tr><td>PM_IC_PREF_CANCEL_ALL_GRP86</td><td> Prefetch Canceled due to page boundary or icache hit </td><td> 3</td><td>	Group 86 pm_ic_pref_cancel</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP86</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 86 pm_ic_pref_cancel</td>

</tr>

<tr><td>PM_RUN_CYC_GRP86</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 86 pm_ic_pref_cancel</td>

</tr>

<tr><td>PM_IERAT_MISS_GRP87</td><td> A translation request missed the Instruction Effective to Real Address Translation (ERAT) table </td><td> 0</td><td>	Group 87 pm_ic_miss</td>

</tr>

<tr><td>PM_L1_ICACHE_MISS_GRP87</td><td> An instruction fetch request missed the L1 cache. </td><td> 1</td><td>	Group 87 pm_ic_miss</td>

</tr>

<tr><td>PM_INST_CMPL_GRP87</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 87 pm_ic_miss</td>

</tr>

<tr><td>PM_CYC_GRP87</td><td> Processor Cycles </td><td> 3</td><td>	Group 87 pm_ic_miss</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP87</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 87 pm_ic_miss</td>

</tr>

<tr><td>PM_RUN_CYC_GRP87</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 87 pm_ic_miss</td>

</tr>

<tr><td>PM_DATA_FROM_L2_GRP88</td><td> The processor's Data Cache was reloaded from the local L2 due to a demand load. </td><td> 0</td><td>	Group 88 pm_cpi_stack1</td>

</tr>

<tr><td>PM_CMPLU_STALL_DCACHE_MISS_GRP88</td><td> Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a Data Cache Miss. Data Cache Miss has higher priority than any other Load/Store delay, so if an instruction encounters multiple delays only the Data Cache Miss will be reported and the entire delay period will be charged to Data Cache Miss. This is a subset of PM_CMPLU_STALL_LSU. </td><td> 1</td><td>	Group 88 pm_cpi_stack1</td>

</tr>

<tr><td>PM_L1_DCACHE_RELOAD_VALID_GRP88</td><td> The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads. </td><td> 2</td><td>	Group 88 pm_cpi_stack1</td>

</tr>

<tr><td>PM_CMPLU_STALL_ERAT_MISS_GRP88</td><td> Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered an ERAT miss. This is a subset of PM_CMPLU_STALL_REJECT. </td><td> 3</td><td>	Group 88 pm_cpi_stack1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP88</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 88 pm_cpi_stack1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP88</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 88 pm_cpi_stack1</td>

</tr>

<tr><td>PM_FXU_IDLE_GRP89</td><td> FXU0 and FXU1 are both idle. </td><td> 0</td><td>	Group 89 pm_cpi_stack2</td>

</tr>

<tr><td>PM_CMPLU_STALL_FXU_GRP89</td><td> Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point instruction. </td><td> 1</td><td>	Group 89 pm_cpi_stack2</td>

</tr>

<tr><td>PM_GRP_CMPL_GRP89</td><td> A group completed. Microcoded instructions that span multiple groups will generate this event once per group. </td><td> 2</td><td>	Group 89 pm_cpi_stack2</td>

</tr>

<tr><td>PM_CMPLU_STALL_DIV_GRP89</td><td> Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point divide instruction. This is a subset of PM_CMPLU_STALL_FXU. </td><td> 3</td><td>	Group 89 pm_cpi_stack2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP89</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 89 pm_cpi_stack2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP89</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 89 pm_cpi_stack2</td>

</tr>

<tr><td>PM_TABLEWALK_CYC_GRP90</td><td> Cycles doing instruction or data tablewalks </td><td> 0</td><td>	Group 90 pm_cpi_stack3</td>

</tr>

<tr><td>PM_CMPLU_STALL_LSU_GRP90</td><td> Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a load/store instruction. </td><td> 1</td><td>	Group 90 pm_cpi_stack3</td>

</tr>

<tr><td>PM_DATA_TABLEWALK_CYC_GRP90</td><td> Cycles a translation tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried. </td><td> 2</td><td>	Group 90 pm_cpi_stack3</td>

</tr>

<tr><td>PM_CMPLU_STALL_REJECT_GRP90</td><td> Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a load/store reject. This is a subset of PM_CMPLU_STALL_LSU. </td><td> 3</td><td>	Group 90 pm_cpi_stack3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP90</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 90 pm_cpi_stack3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP90</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 90 pm_cpi_stack3</td>

</tr>

<tr><td>PM_FLOP_GRP91</td><td> A floating point operation has completed </td><td> 0</td><td>	Group 91 pm_cpi_stack4</td>

</tr>

<tr><td>PM_CMPLU_STALL_SCALAR_LONG_GRP91</td><td> Completion stall caused by long latency scalar instruction </td><td> 1</td><td>	Group 91 pm_cpi_stack4</td>

</tr>

<tr><td>PM_MRK_STALL_CMPLU_CYC_GRP91</td><td> Marked Group Completion Stall cycles </td><td> 2</td><td>	Group 91 pm_cpi_stack4</td>

</tr>

<tr><td>PM_CMPLU_STALL_SCALAR_GRP91</td><td> Completion stall caused by FPU instruction </td><td> 3</td><td>	Group 91 pm_cpi_stack4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP91</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 91 pm_cpi_stack4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP91</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 91 pm_cpi_stack4</td>

</tr>

<tr><td>PM_CMPLU_STALL_END_GCT_NOSLOT_GRP92</td><td> Count ended because GCT went empty </td><td> 0</td><td>	Group 92 pm_cpi_stack5</td>

</tr>

<tr><td>PM_CMPLU_STALL_VECTOR_GRP92</td><td> Completion stall caused by Vector instruction </td><td> 1</td><td>	Group 92 pm_cpi_stack5</td>

</tr>

<tr><td>PM_MRK_STALL_CMPLU_CYC_COUNT_GRP92</td><td> Marked Group Completion Stall cycles (use edge detect to count #) </td><td> 2</td><td>	Group 92 pm_cpi_stack5</td>

</tr>

<tr><td>PM_CMPLU_STALL_GRP92</td><td> No groups completed, GCT not empty </td><td> 3</td><td>	Group 92 pm_cpi_stack5</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP92</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 92 pm_cpi_stack5</td>

</tr>

<tr><td>PM_RUN_CYC_GRP92</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 92 pm_cpi_stack5</td>

</tr>

<tr><td>PM_CMPLU_STALL_THRD_GRP93</td><td> Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn </td><td> 0</td><td>	Group 93 pm_cpi_stack6</td>

</tr>

<tr><td>PM_CMPLU_STALL_DFU_GRP93</td><td> Completion stall caused by Decimal Floating Point Unit </td><td> 1</td><td>	Group 93 pm_cpi_stack6</td>

</tr>

<tr><td>PM_INST_CMPL_GRP93</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 93 pm_cpi_stack6</td>

</tr>

<tr><td>PM_GCT_NOSLOT_BR_MPRED_IC_MISS_GRP93</td><td> No slot in GCT caused by branch mispredict or I cache miss </td><td> 3</td><td>	Group 93 pm_cpi_stack6</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP93</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 93 pm_cpi_stack6</td>

</tr>

<tr><td>PM_RUN_CYC_GRP93</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 93 pm_cpi_stack6</td>

</tr>

<tr><td>PM_GCT_NOSLOT_CYC_GRP94</td><td> Cycles when the Global Completion Table has no slots from this thread. </td><td> 0</td><td>	Group 94 pm_cpi_stack7</td>

</tr>

<tr><td>PM_GCT_NOSLOT_IC_MISS_GRP94</td><td> Cycles when the Global Completion Table has no slots from this thread because of an Instruction Cache miss. </td><td> 1</td><td>	Group 94 pm_cpi_stack7</td>

</tr>

<tr><td>PM_IOPS_DISP_GRP94</td><td> IOPS dispatched </td><td> 2</td><td>	Group 94 pm_cpi_stack7</td>

</tr>

<tr><td>PM_GCT_NOSLOT_BR_MPRED_GRP94</td><td> Cycles when the Global Completion Table has no slots from this thread because of a branch misprediction. </td><td> 3</td><td>	Group 94 pm_cpi_stack7</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP94</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 94 pm_cpi_stack7</td>

</tr>

<tr><td>PM_RUN_CYC_GRP94</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 94 pm_cpi_stack7</td>

</tr>

<tr><td>PM_1PLUS_PPC_CMPL_GRP95</td><td> A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once. </td><td> 0</td><td>	Group 95 pm_cpi_stack8</td>

</tr>

<tr><td>PM_CMPLU_STALL_STORE_GRP95</td><td> Completion stall due to store instruction </td><td> 1</td><td>	Group 95 pm_cpi_stack8</td>

</tr>

<tr><td>PM_INST_DISP_GRP95</td><td> Number of PowerPC instructions successfully dispatched. </td><td> 2</td><td>	Group 95 pm_cpi_stack8</td>

</tr>

<tr><td>PM_CMPLU_STALL_VECTOR_LONG_GRP95</td><td> completion stall due to long latency vector instruction </td><td> 3</td><td>	Group 95 pm_cpi_stack8</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP95</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 95 pm_cpi_stack8</td>

</tr>

<tr><td>PM_RUN_CYC_GRP95</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 95 pm_cpi_stack8</td>

</tr>

<tr><td>PM_CMPLU_STALL_THRD_GRP96</td><td> Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn </td><td> 0</td><td>	Group 96 pm_cpi_stack9</td>

</tr>

<tr><td>PM_CMPLU_STALL_DFU_GRP96</td><td> Completion stall caused by Decimal Floating Point Unit </td><td> 1</td><td>	Group 96 pm_cpi_stack9</td>

</tr>

<tr><td>PM_INST_CMPL_GRP96</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 96 pm_cpi_stack9</td>

</tr>

<tr><td>PM_CMPLU_STALL_COUNT_GRP96</td><td> Count of Cycles where a thread was not completing any groups , when the group completion table had entries for that thread. </td><td> 3</td><td>	Group 96 pm_cpi_stack9</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP96</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 96 pm_cpi_stack9</td>

</tr>

<tr><td>PM_RUN_CYC_GRP96</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 96 pm_cpi_stack9</td>

</tr>

<tr><td>PM_1PLUS_PPC_CMPL_GRP97</td><td> A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once. </td><td> 0</td><td>	Group 97 pm_cpi_stack10</td>

</tr>

<tr><td>PM_CMPLU_STALL_DCACHE_MISS_GRP97</td><td> Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a Data Cache Miss. Data Cache Miss has higher priority than any other Load/Store delay, so if an instruction encounters multiple delays only the Data Cache Miss will be reported and the entire delay period will be charged to Data Cache Miss. This is a subset of PM_CMPLU_STALL_LSU. </td><td> 1</td><td>	Group 97 pm_cpi_stack10</td>

</tr>

<tr><td>PM_L1_DCACHE_RELOAD_VALID_GRP97</td><td> The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads. </td><td> 2</td><td>	Group 97 pm_cpi_stack10</td>

</tr>

<tr><td>PM_CMPLU_STALL_ERAT_MISS_GRP97</td><td> Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered an ERAT miss. This is a subset of PM_CMPLU_STALL_REJECT. </td><td> 3</td><td>	Group 97 pm_cpi_stack10</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP97</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 97 pm_cpi_stack10</td>

</tr>

<tr><td>PM_RUN_CYC_GRP97</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 97 pm_cpi_stack10</td>

</tr>

<tr><td>PM_DATA_FROM_L2_GRP98</td><td> The processor's Data Cache was reloaded from the local L2 due to a demand load. </td><td> 0</td><td>	Group 98 pm_dsource1</td>

</tr>

<tr><td>PM_DATA_FROM_L3_GRP98</td><td> The processor's Data Cache was reloaded from the local L3 due to a demand load. </td><td> 1</td><td>	Group 98 pm_dsource1</td>

</tr>

<tr><td>PM_DATA_FROM_RMEM_GRP98</td><td> The processor's Data Cache was reloaded from memory attached to a different module than this processor is located on. </td><td> 2</td><td>	Group 98 pm_dsource1</td>

</tr>

<tr><td>PM_DATA_FROM_LMEM_GRP98</td><td> The processor's Data Cache was reloaded from memory attached to the same module this processor is located on. </td><td> 3</td><td>	Group 98 pm_dsource1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP98</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 98 pm_dsource1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP98</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 98 pm_dsource1</td>

</tr>

<tr><td>PM_DATA_FROM_L3_GRP99</td><td> The processor's Data Cache was reloaded from the local L3 due to a demand load. </td><td> 0</td><td>	Group 99 pm_dsource2</td>

</tr>

<tr><td>PM_DATA_FROM_L31_SHR_GRP99</td><td> Data loaded from another L3 on same chip shared </td><td> 1</td><td>	Group 99 pm_dsource2</td>

</tr>

<tr><td>PM_DATA_FROM_LMEM_GRP99</td><td> The processor's Data Cache was reloaded from memory attached to the same module this processor is located on. </td><td> 2</td><td>	Group 99 pm_dsource2</td>

</tr>

<tr><td>PM_DATA_FROM_L2MISS_GRP99</td><td> The processor's Data Cache was reloaded but not from the local L2. </td><td> 3</td><td>	Group 99 pm_dsource2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP99</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 99 pm_dsource2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP99</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 99 pm_dsource2</td>

</tr>

<tr><td>PM_DATA_FROM_DMEM_GRP100</td><td> The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load </td><td> 0</td><td>	Group 100 pm_dsource3</td>

</tr>

<tr><td>PM_DATA_FROM_L3MISS_GRP100</td><td> The processor's Data Cache was reloaded from beyond L3 due to a demand load </td><td> 1</td><td>	Group 100 pm_dsource3</td>

</tr>

<tr><td>PM_DATA_FROM_L21_MOD_GRP100</td><td> Data loaded from another L2 on same chip modified </td><td> 2</td><td>	Group 100 pm_dsource3</td>

</tr>

<tr><td>PM_DATA_FROM_L2MISS_GRP100</td><td> The processor's Data Cache was reloaded but not from the local L2. </td><td> 3</td><td>	Group 100 pm_dsource3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP100</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 100 pm_dsource3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP100</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 100 pm_dsource3</td>

</tr>

<tr><td>PM_DATA_FROM_L31_MOD_GRP101</td><td> Data loaded from another L3 on same chip modified </td><td> 0</td><td>	Group 101 pm_dsource4</td>

</tr>

<tr><td>PM_DATA_FROM_RL2L3_SHR_GRP101</td><td> The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load </td><td> 1</td><td>	Group 101 pm_dsource4</td>

</tr>

<tr><td>PM_DATA_FROM_DL2L3_MOD_GRP101</td><td> The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load </td><td> 2</td><td>	Group 101 pm_dsource4</td>

</tr>

<tr><td>PM_DATA_FROM_DL2L3_MOD_GRP101</td><td> The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load </td><td> 3</td><td>	Group 101 pm_dsource4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP101</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 101 pm_dsource4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP101</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 101 pm_dsource4</td>

</tr>

<tr><td>PM_DATA_FROM_L31_SHR_GRP102</td><td> Data loaded from another L3 on same chip shared </td><td> 0</td><td>	Group 102 pm_dsource5</td>

</tr>

<tr><td>PM_DATA_FROM_DMEM_GRP102</td><td> The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load </td><td> 1</td><td>	Group 102 pm_dsource5</td>

</tr>

<tr><td>PM_DATA_FROM_DL2L3_SHR_GRP102</td><td> The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a demand load </td><td> 2</td><td>	Group 102 pm_dsource5</td>

</tr>

<tr><td>PM_DATA_FROM_L21_SHR_GRP102</td><td> Data loaded from another L2 on same chip shared </td><td> 3</td><td>	Group 102 pm_dsource5</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP102</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 102 pm_dsource5</td>

</tr>

<tr><td>PM_RUN_CYC_GRP102</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 102 pm_dsource5</td>

</tr>

<tr><td>PM_DATA_FROM_RL2L3_MOD_GRP103</td><td> The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a demand load </td><td> 0</td><td>	Group 103 pm_dsource6</td>

</tr>

<tr><td>PM_DATA_FROM_RL2L3_SHR_GRP103</td><td> The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load </td><td> 1</td><td>	Group 103 pm_dsource6</td>

</tr>

<tr><td>PM_DATA_FROM_L21_SHR_GRP103</td><td> Data loaded from another L2 on same chip shared </td><td> 2</td><td>	Group 103 pm_dsource6</td>

</tr>

<tr><td>PM_DATA_FROM_L2MISS_GRP103</td><td> The processor's Data Cache was reloaded but not from the local L2. </td><td> 3</td><td>	Group 103 pm_dsource6</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP103</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 103 pm_dsource6</td>

</tr>

<tr><td>PM_RUN_CYC_GRP103</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 103 pm_dsource6</td>

</tr>

<tr><td>PM_DATA_FROM_RL2L3_SHR_GRP104</td><td> The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load </td><td> 0</td><td>	Group 104 pm_dsource7</td>

</tr>

<tr><td>PM_DATA_FROM_L3MISS_GRP104</td><td> The processor's Data Cache was reloaded from beyond L3 due to a demand load </td><td> 1</td><td>	Group 104 pm_dsource7</td>

</tr>

<tr><td>PM_DATA_FROM_DL2L3_MOD_GRP104</td><td> The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load </td><td> 2</td><td>	Group 104 pm_dsource7</td>

</tr>

<tr><td>PM_DATA_FROM_DL2L3_MOD_GRP104</td><td> The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load </td><td> 3</td><td>	Group 104 pm_dsource7</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP104</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 104 pm_dsource7</td>

</tr>

<tr><td>PM_RUN_CYC_GRP104</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 104 pm_dsource7</td>

</tr>

<tr><td>PM_INST_CMPL_GRP105</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 105 pm_dsource8</td>

</tr>

<tr><td>PM_DATA_FROM_L3_GRP105</td><td> The processor's Data Cache was reloaded from the local L3 due to a demand load. </td><td> 1</td><td>	Group 105 pm_dsource8</td>

</tr>

<tr><td>PM_DATA_FROM_L3MISS_GRP105</td><td> The processor's Data Cache was reloaded from beyond L3 due to a demand load </td><td> 2</td><td>	Group 105 pm_dsource8</td>

</tr>

<tr><td>PM_DATA_FROM_LMEM_GRP105</td><td> The processor's Data Cache was reloaded from memory attached to the same module this processor is located on. </td><td> 3</td><td>	Group 105 pm_dsource8</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP105</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 105 pm_dsource8</td>

</tr>

<tr><td>PM_RUN_CYC_GRP105</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 105 pm_dsource8</td>

</tr>

<tr><td>PM_DATA_FROM_L2_GRP106</td><td> The processor's Data Cache was reloaded from the local L2 due to a demand load. </td><td> 0</td><td>	Group 106 pm_dsource9</td>

</tr>

<tr><td>PM_DATA_FROM_L2MISS_GRP106</td><td> The processor's Data Cache was reloaded but not from the local L2. </td><td> 1</td><td>	Group 106 pm_dsource9</td>

</tr>

<tr><td>PM_L1_DCACHE_RELOAD_VALID_GRP106</td><td> The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads. </td><td> 2</td><td>	Group 106 pm_dsource9</td>

</tr>

<tr><td>PM_LD_MISS_L1_GRP106</td><td> Load references that miss the Level 1 Data cache. Combined unit 0 + 1. </td><td> 3</td><td>	Group 106 pm_dsource9</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP106</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 106 pm_dsource9</td>

</tr>

<tr><td>PM_RUN_CYC_GRP106</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 106 pm_dsource9</td>

</tr>

<tr><td>PM_DATA_FROM_RL2L3_MOD_GRP107</td><td> The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a demand load </td><td> 0</td><td>	Group 107 pm_dsource10</td>

</tr>

<tr><td>PM_DATA_FROM_RL2L3_SHR_GRP107</td><td> The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load </td><td> 1</td><td>	Group 107 pm_dsource10</td>

</tr>

<tr><td>PM_DATA_FROM_DL2L3_SHR_GRP107</td><td> The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a demand load </td><td> 2</td><td>	Group 107 pm_dsource10</td>

</tr>

<tr><td>PM_DATA_FROM_DL2L3_MOD_GRP107</td><td> The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load </td><td> 3</td><td>	Group 107 pm_dsource10</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP107</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 107 pm_dsource10</td>

</tr>

<tr><td>PM_RUN_CYC_GRP107</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 107 pm_dsource10</td>

</tr>

<tr><td>PM_DATA_FROM_L2_GRP108</td><td> The processor's Data Cache was reloaded from the local L2 due to a demand load. </td><td> 0</td><td>	Group 108 pm_dsource11</td>

</tr>

<tr><td>PM_DATA_FROM_L2MISS_GRP108</td><td> The processor's Data Cache was reloaded but not from the local L2. </td><td> 1</td><td>	Group 108 pm_dsource11</td>

</tr>

<tr><td>PM_DATA_FROM_L3MISS_GRP108</td><td> The processor's Data Cache was reloaded from beyond L3 due to a demand load </td><td> 2</td><td>	Group 108 pm_dsource11</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP108</td><td> Number of run instructions completed. </td><td> 3</td><td>	Group 108 pm_dsource11</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP108</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 108 pm_dsource11</td>

</tr>

<tr><td>PM_RUN_CYC_GRP108</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 108 pm_dsource11</td>

</tr>

<tr><td>PM_DATA_FROM_RL2L3_MOD_GRP109</td><td> The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a demand load </td><td> 0</td><td>	Group 109 pm_dsource12</td>

</tr>

<tr><td>PM_DATA_FROM_DMEM_GRP109</td><td> The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load </td><td> 1</td><td>	Group 109 pm_dsource12</td>

</tr>

<tr><td>PM_DATA_FROM_RMEM_GRP109</td><td> The processor's Data Cache was reloaded from memory attached to a different module than this processor is located on. </td><td> 2</td><td>	Group 109 pm_dsource12</td>

</tr>

<tr><td>PM_DATA_FROM_LMEM_GRP109</td><td> The processor's Data Cache was reloaded from memory attached to the same module this processor is located on. </td><td> 3</td><td>	Group 109 pm_dsource12</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP109</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 109 pm_dsource12</td>

</tr>

<tr><td>PM_RUN_CYC_GRP109</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 109 pm_dsource12</td>

</tr>

<tr><td>PM_DERAT_MISS_4K_GRP110</td><td> A data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload. </td><td> 0</td><td>	Group 110 pm_dsource13</td>

</tr>

<tr><td>PM_INST_CMPL_GRP110</td><td> Number of PowerPC Instructions that completed. </td><td> 1</td><td>	Group 110 pm_dsource13</td>

</tr>

<tr><td>PM_DATA_FROM_DL2L3_SHR_GRP110</td><td> The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a demand load </td><td> 2</td><td>	Group 110 pm_dsource13</td>

</tr>

<tr><td>PM_DATA_FROM_DL2L3_MOD_GRP110</td><td> The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load </td><td> 3</td><td>	Group 110 pm_dsource13</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP110</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 110 pm_dsource13</td>

</tr>

<tr><td>PM_RUN_CYC_GRP110</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 110 pm_dsource13</td>

</tr>

<tr><td>PM_DATA_FROM_DMEM_GRP111</td><td> The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load </td><td> 0</td><td>	Group 111 pm_dsource14</td>

</tr>

<tr><td>PM_INST_CMPL_GRP111</td><td> Number of PowerPC Instructions that completed. </td><td> 1</td><td>	Group 111 pm_dsource14</td>

</tr>

<tr><td>PM_DATA_FROM_RMEM_GRP111</td><td> The processor's Data Cache was reloaded from memory attached to a different module than this processor is located on. </td><td> 2</td><td>	Group 111 pm_dsource14</td>

</tr>

<tr><td>PM_DATA_FROM_LMEM_GRP111</td><td> The processor's Data Cache was reloaded from memory attached to the same module this processor is located on. </td><td> 3</td><td>	Group 111 pm_dsource14</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP111</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 111 pm_dsource14</td>

</tr>

<tr><td>PM_RUN_CYC_GRP111</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 111 pm_dsource14</td>

</tr>

<tr><td>PM_DATA_FROM_DMEM_GRP112</td><td> The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load </td><td> 0</td><td>	Group 112 pm_dsource15</td>

</tr>

<tr><td>PM_INST_CMPL_GRP112</td><td> Number of PowerPC Instructions that completed. </td><td> 1</td><td>	Group 112 pm_dsource15</td>

</tr>

<tr><td>PM_L1_DCACHE_RELOAD_VALID_GRP112</td><td> The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads. </td><td> 2</td><td>	Group 112 pm_dsource15</td>

</tr>

<tr><td>PM_DATA_FROM_LMEM_GRP112</td><td> The processor's Data Cache was reloaded from memory attached to the same module this processor is located on. </td><td> 3</td><td>	Group 112 pm_dsource15</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP112</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 112 pm_dsource15</td>

</tr>

<tr><td>PM_RUN_CYC_GRP112</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 112 pm_dsource15</td>

</tr>

<tr><td>PM_INST_FROM_L2_GRP113</td><td> An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions </td><td> 0</td><td>	Group 113 pm_isource1</td>

</tr>

<tr><td>PM_INST_FROM_L3_GRP113</td><td> An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions </td><td> 1</td><td>	Group 113 pm_isource1</td>

</tr>

<tr><td>PM_INST_FROM_LMEM_GRP113</td><td> An instruction fetch group was fetched from memory attached to the same module this processor is located on. Fetch groups can contain up to 8 instructions </td><td> 2</td><td>	Group 113 pm_isource1</td>

</tr>

<tr><td>PM_INST_FROM_L2MISS_GRP113</td><td> An instruction fetch group was fetched from beyond the local L2. </td><td> 3</td><td>	Group 113 pm_isource1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP113</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 113 pm_isource1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP113</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 113 pm_isource1</td>

</tr>

<tr><td>PM_INST_FROM_L3_GRP114</td><td> An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions </td><td> 0</td><td>	Group 114 pm_isource2</td>

</tr>

<tr><td>PM_INST_FROM_DMEM_GRP114</td><td> An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions </td><td> 1</td><td>	Group 114 pm_isource2</td>

</tr>

<tr><td>PM_INST_FROM_DL2L3_MOD_GRP114</td><td> An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions </td><td> 2</td><td>	Group 114 pm_isource2</td>

</tr>

<tr><td>PM_INST_FROM_LMEM_GRP114</td><td> An instruction fetch group was fetched from memory attached to the same module this processor is located on. Fetch groups can contain up to 8 instructions </td><td> 3</td><td>	Group 114 pm_isource2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP114</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 114 pm_isource2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP114</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 114 pm_isource2</td>

</tr>

<tr><td>PM_INST_FROM_DMEM_GRP115</td><td> An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions </td><td> 0</td><td>	Group 115 pm_isource3</td>

</tr>

<tr><td>PM_INST_FROM_L3MISS_GRP115</td><td> An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions. </td><td> 1</td><td>	Group 115 pm_isource3</td>

</tr>

<tr><td>PM_INST_FROM_DL2L3_SHR_GRP115</td><td> An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions </td><td> 2</td><td>	Group 115 pm_isource3</td>

</tr>

<tr><td>PM_INST_FROM_DL2L3_MOD_GRP115</td><td> An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions </td><td> 3</td><td>	Group 115 pm_isource3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP115</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 115 pm_isource3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP115</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 115 pm_isource3</td>

</tr>

<tr><td>PM_INST_FROM_L31_MOD_GRP116</td><td> Instruction fetched from another L3 on same chip modified </td><td> 0</td><td>	Group 116 pm_isource4</td>

</tr>

<tr><td>PM_INST_FROM_L31_SHR_GRP116</td><td> Instruction fetched from another L3 on same chip shared </td><td> 1</td><td>	Group 116 pm_isource4</td>

</tr>

<tr><td>PM_INST_FROM_L21_MOD_GRP116</td><td> Instruction fetched from another L2 on same chip modified </td><td> 2</td><td>	Group 116 pm_isource4</td>

</tr>

<tr><td>PM_INST_FROM_L21_SHR_GRP116</td><td> Instruction fetched from another L2 on same chip shared </td><td> 3</td><td>	Group 116 pm_isource4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP116</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 116 pm_isource4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP116</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 116 pm_isource4</td>

</tr>

<tr><td>PM_INST_FROM_L31_SHR_GRP117</td><td> Instruction fetched from another L3 on same chip shared </td><td> 0</td><td>	Group 117 pm_isource5</td>

</tr>

<tr><td>PM_INST_FROM_RL2L3_SHR_GRP117</td><td> An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions </td><td> 1</td><td>	Group 117 pm_isource5</td>

</tr>

<tr><td>PM_INST_FROM_L21_SHR_GRP117</td><td> Instruction fetched from another L2 on same chip shared </td><td> 2</td><td>	Group 117 pm_isource5</td>

</tr>

<tr><td>PM_INST_FROM_L2MISS_GRP117</td><td> An instruction fetch group was fetched from beyond the local L2. </td><td> 3</td><td>	Group 117 pm_isource5</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP117</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 117 pm_isource5</td>

</tr>

<tr><td>PM_RUN_CYC_GRP117</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 117 pm_isource5</td>

</tr>

<tr><td>PM_INST_FROM_PREF_GRP118</td><td> An instruction fetch group was fetched from the prefetch buffer. Fetch groups can contain up to 8 instructions </td><td> 0</td><td>	Group 118 pm_isource6</td>

</tr>

<tr><td>PM_INST_FROM_L3MISS_GRP118</td><td> An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions. </td><td> 1</td><td>	Group 118 pm_isource6</td>

</tr>

<tr><td>PM_INST_FROM_LMEM_GRP118</td><td> An instruction fetch group was fetched from memory attached to the same module this processor is located on. Fetch groups can contain up to 8 instructions </td><td> 2</td><td>	Group 118 pm_isource6</td>

</tr>

<tr><td>PM_INST_FROM_L2MISS_GRP118</td><td> An instruction fetch group was fetched from beyond the local L2. </td><td> 3</td><td>	Group 118 pm_isource6</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP118</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 118 pm_isource6</td>

</tr>

<tr><td>PM_RUN_CYC_GRP118</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 118 pm_isource6</td>

</tr>

<tr><td>PM_INST_FROM_RL2L3_MOD_GRP119</td><td> An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions </td><td> 0</td><td>	Group 119 pm_isource7</td>

</tr>

<tr><td>PM_INST_FROM_RL2L3_SHR_GRP119</td><td> An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions </td><td> 1</td><td>	Group 119 pm_isource7</td>

</tr>

<tr><td>PM_INST_FROM_DL2L3_SHR_GRP119</td><td> An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions </td><td> 2</td><td>	Group 119 pm_isource7</td>

</tr>

<tr><td>PM_INST_FROM_DL2L3_MOD_GRP119</td><td> An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions </td><td> 3</td><td>	Group 119 pm_isource7</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP119</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 119 pm_isource7</td>

</tr>

<tr><td>PM_RUN_CYC_GRP119</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 119 pm_isource7</td>

</tr>

<tr><td>PM_INST_FROM_RL2L3_SHR_GRP120</td><td> An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions </td><td> 0</td><td>	Group 120 pm_isource8</td>

</tr>

<tr><td>PM_INST_FROM_L3MISS_GRP120</td><td> An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions. </td><td> 1</td><td>	Group 120 pm_isource8</td>

</tr>

<tr><td>PM_INST_FROM_LMEM_GRP120</td><td> An instruction fetch group was fetched from memory attached to the same module this processor is located on. Fetch groups can contain up to 8 instructions </td><td> 2</td><td>	Group 120 pm_isource8</td>

</tr>

<tr><td>PM_INST_FROM_L2MISS_GRP120</td><td> An instruction fetch group was fetched from beyond the local L2. </td><td> 3</td><td>	Group 120 pm_isource8</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP120</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 120 pm_isource8</td>

</tr>

<tr><td>PM_RUN_CYC_GRP120</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 120 pm_isource8</td>

</tr>

<tr><td>PM_INST_FROM_PREF_GRP121</td><td> An instruction fetch group was fetched from the prefetch buffer. Fetch groups can contain up to 8 instructions </td><td> 0</td><td>	Group 121 pm_isource9</td>

</tr>

<tr><td>PM_INST_FROM_DMEM_GRP121</td><td> An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions </td><td> 1</td><td>	Group 121 pm_isource9</td>

</tr>

<tr><td>PM_INST_FROM_RMEM_GRP121</td><td> An instruction fetch group was fetched from memory attached to a different module than this processor is located on. Fetch groups can contain up to 8 instructions </td><td> 2</td><td>	Group 121 pm_isource9</td>

</tr>

<tr><td>PM_INST_FROM_LMEM_GRP121</td><td> An instruction fetch group was fetched from memory attached to the same module this processor is located on. Fetch groups can contain up to 8 instructions </td><td> 3</td><td>	Group 121 pm_isource9</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP121</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 121 pm_isource9</td>

</tr>

<tr><td>PM_RUN_CYC_GRP121</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 121 pm_isource9</td>

</tr>

<tr><td>PM_INST_FROM_L2_GRP122</td><td> An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions </td><td> 0</td><td>	Group 122 pm_isource10</td>

</tr>

<tr><td>PM_INST_FROM_L3_GRP122</td><td> An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions </td><td> 1</td><td>	Group 122 pm_isource10</td>

</tr>

<tr><td>PM_INST_CMPL_GRP122</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 122 pm_isource10</td>

</tr>

<tr><td>PM_CYC_GRP122</td><td> Processor Cycles </td><td> 3</td><td>	Group 122 pm_isource10</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP122</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 122 pm_isource10</td>

</tr>

<tr><td>PM_RUN_CYC_GRP122</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 122 pm_isource10</td>

</tr>

<tr><td>PM_INST_FROM_RL2L3_MOD_GRP123</td><td> An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions </td><td> 0</td><td>	Group 123 pm_isource11</td>

</tr>

<tr><td>PM_INST_FROM_RL2L3_SHR_GRP123</td><td> An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions </td><td> 1</td><td>	Group 123 pm_isource11</td>

</tr>

<tr><td>PM_INST_FROM_LMEM_GRP123</td><td> An instruction fetch group was fetched from memory attached to the same module this processor is located on. Fetch groups can contain up to 8 instructions </td><td> 2</td><td>	Group 123 pm_isource11</td>

</tr>

<tr><td>PM_INST_CMPL_GRP123</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 123 pm_isource11</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP123</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 123 pm_isource11</td>

</tr>

<tr><td>PM_RUN_CYC_GRP123</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 123 pm_isource11</td>

</tr>

<tr><td>PM_CYC_GRP124</td><td> Processor Cycles </td><td> 0</td><td>	Group 124 pm_isource12</td>

</tr>

<tr><td>PM_INST_CMPL_GRP124</td><td> Number of PowerPC Instructions that completed. </td><td> 1</td><td>	Group 124 pm_isource12</td>

</tr>

<tr><td>PM_INST_FROM_DL2L3_SHR_GRP124</td><td> An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions </td><td> 2</td><td>	Group 124 pm_isource12</td>

</tr>

<tr><td>PM_INST_FROM_DL2L3_MOD_GRP124</td><td> An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions </td><td> 3</td><td>	Group 124 pm_isource12</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP124</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 124 pm_isource12</td>

</tr>

<tr><td>PM_RUN_CYC_GRP124</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 124 pm_isource12</td>

</tr>

<tr><td>PM_INST_FROM_DMEM_GRP125</td><td> An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions </td><td> 0</td><td>	Group 125 pm_isource13</td>

</tr>

<tr><td>PM_INST_CMPL_GRP125</td><td> Number of PowerPC Instructions that completed. </td><td> 1</td><td>	Group 125 pm_isource13</td>

</tr>

<tr><td>PM_INST_FROM_RMEM_GRP125</td><td> An instruction fetch group was fetched from memory attached to a different module than this processor is located on. Fetch groups can contain up to 8 instructions </td><td> 2</td><td>	Group 125 pm_isource13</td>

</tr>

<tr><td>PM_INST_FROM_LMEM_GRP125</td><td> An instruction fetch group was fetched from memory attached to the same module this processor is located on. Fetch groups can contain up to 8 instructions </td><td> 3</td><td>	Group 125 pm_isource13</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP125</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 125 pm_isource13</td>

</tr>

<tr><td>PM_RUN_CYC_GRP125</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 125 pm_isource13</td>

</tr>

<tr><td>PM_LSU_DC_PREF_STREAM_ALLOC_GRP126</td><td> D cache new prefetch stream allocated </td><td> 0</td><td>	Group 126 pm_prefetch1</td>

</tr>

<tr><td>PM_L3_PREF_LDST_GRP126</td><td> L3 cache prefetches LD + ST </td><td> 1</td><td>	Group 126 pm_prefetch1</td>

</tr>

<tr><td>PM_LSU_DC_PREF_STREAM_CONFIRM_GRP126</td><td> Dcache new prefetch stream confirmed </td><td> 2</td><td>	Group 126 pm_prefetch1</td>

</tr>

<tr><td>PM_L1_PREF_GRP126</td><td> A request to prefetch data into the L1 was made </td><td> 3</td><td>	Group 126 pm_prefetch1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP126</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 126 pm_prefetch1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP126</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 126 pm_prefetch1</td>

</tr>

<tr><td>PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM_GRP127</td><td> Dcache Strided prefetch stream confirmed (software + hardware) </td><td> 0</td><td>	Group 127 pm_prefetch2</td>

</tr>

<tr><td>PM_LD_REF_L1_GRP127</td><td> L1 D cache load references counted at finish </td><td> 1</td><td>	Group 127 pm_prefetch2</td>

</tr>

<tr><td>PM_LSU_FIN_GRP127</td><td> LSU Finished an instruction (up to 2 per cycle) </td><td> 2</td><td>	Group 127 pm_prefetch2</td>

</tr>

<tr><td>PM_LD_MISS_L1_GRP127</td><td> Load references that miss the Level 1 Data cache. Combined unit 0 + 1. </td><td> 3</td><td>	Group 127 pm_prefetch2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP127</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 127 pm_prefetch2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP127</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 127 pm_prefetch2</td>

</tr>

<tr><td>PM_VSU0_1FLOP_GRP128</td><td> one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished </td><td> 0</td><td>	Group 128 pm_vsu0</td>

</tr>

<tr><td>PM_VSU1_1FLOP_GRP128</td><td> one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished </td><td> 1</td><td>	Group 128 pm_vsu0</td>

</tr>

<tr><td>PM_VSU0_2FLOP_GRP128</td><td> two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) </td><td> 2</td><td>	Group 128 pm_vsu0</td>

</tr>

<tr><td>PM_VSU1_2FLOP_GRP128</td><td> two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) </td><td> 3</td><td>	Group 128 pm_vsu0</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP128</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 128 pm_vsu0</td>

</tr>

<tr><td>PM_RUN_CYC_GRP128</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 128 pm_vsu0</td>

</tr>

<tr><td>PM_VSU0_4FLOP_GRP129</td><td> four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) </td><td> 0</td><td>	Group 129 pm_vsu1</td>

</tr>

<tr><td>PM_VSU1_4FLOP_GRP129</td><td> four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) </td><td> 1</td><td>	Group 129 pm_vsu1</td>

</tr>

<tr><td>PM_VSU0_8FLOP_GRP129</td><td> eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) </td><td> 2</td><td>	Group 129 pm_vsu1</td>

</tr>

<tr><td>PM_VSU1_8FLOP_GRP129</td><td> eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) </td><td> 3</td><td>	Group 129 pm_vsu1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP129</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 129 pm_vsu1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP129</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 129 pm_vsu1</td>

</tr>

<tr><td>PM_VSU_2FLOP_GRP130</td><td> two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) </td><td> 0</td><td>	Group 130 pm_vsu2</td>

</tr>

<tr><td>PM_VSU_2FLOP_DOUBLE_GRP130</td><td> DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg </td><td> 1</td><td>	Group 130 pm_vsu2</td>

</tr>

<tr><td>PM_VSU0_2FLOP_DOUBLE_GRP130</td><td> two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) </td><td> 2</td><td>	Group 130 pm_vsu2</td>

</tr>

<tr><td>PM_VSU1_2FLOP_DOUBLE_GRP130</td><td> two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) </td><td> 3</td><td>	Group 130 pm_vsu2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP130</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 130 pm_vsu2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP130</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 130 pm_vsu2</td>

</tr>

<tr><td>PM_VSU0_FMA_GRP131</td><td> two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only! </td><td> 0</td><td>	Group 131 pm_vsu3</td>

</tr>

<tr><td>PM_VSU1_FMA_GRP131</td><td> two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only! </td><td> 1</td><td>	Group 131 pm_vsu3</td>

</tr>

<tr><td>PM_VSU_FMA_GRP131</td><td> two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! </td><td> 2</td><td>	Group 131 pm_vsu3</td>

</tr>

<tr><td>PM_INST_CMPL_GRP131</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 131 pm_vsu3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP131</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 131 pm_vsu3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP131</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 131 pm_vsu3</td>

</tr>

<tr><td>PM_VSU0_FMA_DOUBLE_GRP132</td><td> four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp) </td><td> 0</td><td>	Group 132 pm_vsu4</td>

</tr>

<tr><td>PM_VSU1_FMA_DOUBLE_GRP132</td><td> four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp) </td><td> 1</td><td>	Group 132 pm_vsu4</td>

</tr>

<tr><td>PM_VSU_FMA_DOUBLE_GRP132</td><td> DP vector version of fmadd,fnmadd,fmsub,fnmsub </td><td> 2</td><td>	Group 132 pm_vsu4</td>

</tr>

<tr><td>PM_INST_CMPL_GRP132</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 132 pm_vsu4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP132</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 132 pm_vsu4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP132</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 132 pm_vsu4</td>

</tr>

<tr><td>PM_VSU_VECTOR_DOUBLE_ISSUED_GRP133</td><td> Double Precision vector instruction issued on Pipe0 </td><td> 0</td><td>	Group 133 pm_vsu5</td>

</tr>

<tr><td>PM_VSU0_VECT_DOUBLE_ISSUED_GRP133</td><td> Double Precision vector instruction issued on Pipe0 </td><td> 1</td><td>	Group 133 pm_vsu5</td>

</tr>

<tr><td>PM_VSU1_VECT_DOUBLE_ISSUED_GRP133</td><td> Double Precision vector instruction issued on Pipe1 </td><td> 2</td><td>	Group 133 pm_vsu5</td>

</tr>

<tr><td>PM_INST_CMPL_GRP133</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 133 pm_vsu5</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP133</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 133 pm_vsu5</td>

</tr>

<tr><td>PM_RUN_CYC_GRP133</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 133 pm_vsu5</td>

</tr>

<tr><td>PM_VSU_DENORM_GRP134</td><td> Vector or Scalar denorm operand </td><td> 0</td><td>	Group 134 pm_vsu6</td>

</tr>

<tr><td>PM_VSU0_DENORM_GRP134</td><td> VSU0 received denormalized data </td><td> 1</td><td>	Group 134 pm_vsu6</td>

</tr>

<tr><td>PM_VSU1_DENORM_GRP134</td><td> VSU1 received denormalized data </td><td> 2</td><td>	Group 134 pm_vsu6</td>

</tr>

<tr><td>PM_INST_CMPL_GRP134</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 134 pm_vsu6</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP134</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 134 pm_vsu6</td>

</tr>

<tr><td>PM_RUN_CYC_GRP134</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 134 pm_vsu6</td>

</tr>

<tr><td>PM_VSU_FIN_GRP135</td><td> VSU0 Finished an instruction </td><td> 0</td><td>	Group 135 pm_vsu7</td>

</tr>

<tr><td>PM_VSU0_FIN_GRP135</td><td> VSU0 Finished an instruction </td><td> 1</td><td>	Group 135 pm_vsu7</td>

</tr>

<tr><td>PM_VSU1_FIN_GRP135</td><td> VSU1 Finished an instruction </td><td> 2</td><td>	Group 135 pm_vsu7</td>

</tr>

<tr><td>PM_INST_CMPL_GRP135</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 135 pm_vsu7</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP135</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 135 pm_vsu7</td>

</tr>

<tr><td>PM_RUN_CYC_GRP135</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 135 pm_vsu7</td>

</tr>

<tr><td>PM_VSU_STF_GRP136</td><td> FPU store (SP or DP) issued on Pipe0 </td><td> 0</td><td>	Group 136 pm_vsu8</td>

</tr>

<tr><td>PM_VSU0_STF_GRP136</td><td> FPU store (SP or DP) issued on Pipe0 </td><td> 1</td><td>	Group 136 pm_vsu8</td>

</tr>

<tr><td>PM_VSU1_STF_GRP136</td><td> FPU store (SP or DP) issued on Pipe1 </td><td> 2</td><td>	Group 136 pm_vsu8</td>

</tr>

<tr><td>PM_INST_CMPL_GRP136</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 136 pm_vsu8</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP136</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 136 pm_vsu8</td>

</tr>

<tr><td>PM_RUN_CYC_GRP136</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 136 pm_vsu8</td>

</tr>

<tr><td>PM_VSU_SINGLE_GRP137</td><td> Vector or Scalar single precision </td><td> 0</td><td>	Group 137 pm_vsu9</td>

</tr>

<tr><td>PM_VSU0_SINGLE_GRP137</td><td> VSU0 executed single precision instruction </td><td> 1</td><td>	Group 137 pm_vsu9</td>

</tr>

<tr><td>PM_VSU1_SINGLE_GRP137</td><td> VSU1 executed single precision instruction </td><td> 2</td><td>	Group 137 pm_vsu9</td>

</tr>

<tr><td>PM_VSU0_16FLOP_GRP137</td><td> Sixteen flops operation (SP vector versions of fdiv,fsqrt) </td><td> 3</td><td>	Group 137 pm_vsu9</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP137</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 137 pm_vsu9</td>

</tr>

<tr><td>PM_RUN_CYC_GRP137</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 137 pm_vsu9</td>

</tr>

<tr><td>PM_VSU_FSQRT_FDIV_GRP138</td><td> DP vector versions of fdiv,fsqrt </td><td> 0</td><td>	Group 138 pm_vsu10</td>

</tr>

<tr><td>PM_VSU0_FSQRT_FDIV_GRP138</td><td> four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only! </td><td> 1</td><td>	Group 138 pm_vsu10</td>

</tr>

<tr><td>PM_VSU1_FSQRT_FDIV_GRP138</td><td> four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only! </td><td> 2</td><td>	Group 138 pm_vsu10</td>

</tr>

<tr><td>PM_INST_CMPL_GRP138</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 138 pm_vsu10</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP138</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 138 pm_vsu10</td>

</tr>

<tr><td>PM_RUN_CYC_GRP138</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 138 pm_vsu10</td>

</tr>

<tr><td>PM_VSU_FSQRT_FDIV_DOUBLE_GRP139</td><td> DP vector versions of fdiv,fsqrt </td><td> 0</td><td>	Group 139 pm_vsu11</td>

</tr>

<tr><td>PM_VSU0_FSQRT_FDIV_DOUBLE_GRP139</td><td> eight flop DP vector operations (xvfdivdp, xvsqrtdp </td><td> 1</td><td>	Group 139 pm_vsu11</td>

</tr>

<tr><td>PM_VSU1_FSQRT_FDIV_DOUBLE_GRP139</td><td> eight flop DP vector operations (xvfdivdp, xvsqrtdp </td><td> 2</td><td>	Group 139 pm_vsu11</td>

</tr>

<tr><td>PM_INST_CMPL_GRP139</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 139 pm_vsu11</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP139</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 139 pm_vsu11</td>

</tr>

<tr><td>PM_RUN_CYC_GRP139</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 139 pm_vsu11</td>

</tr>

<tr><td>PM_VSU_SCALAR_DOUBLE_ISSUED_GRP140</td><td> Double Precision scalar instruction issued on Pipe0 </td><td> 0</td><td>	Group 140 pm_vsu12</td>

</tr>

<tr><td>PM_VSU0_SCAL_DOUBLE_ISSUED_GRP140</td><td> Double Precision scalar instruction issued on Pipe0 </td><td> 1</td><td>	Group 140 pm_vsu12</td>

</tr>

<tr><td>PM_VSU1_SCAL_DOUBLE_ISSUED_GRP140</td><td> Double Precision scalar instruction issued on Pipe1 </td><td> 2</td><td>	Group 140 pm_vsu12</td>

</tr>

<tr><td>PM_INST_CMPL_GRP140</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 140 pm_vsu12</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP140</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 140 pm_vsu12</td>

</tr>

<tr><td>PM_RUN_CYC_GRP140</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 140 pm_vsu12</td>

</tr>

<tr><td>PM_VSU_SCALAR_SINGLE_ISSUED_GRP141</td><td> Single Precision scalar instruction issued on Pipe0 </td><td> 0</td><td>	Group 141 pm_vsu13</td>

</tr>

<tr><td>PM_VSU0_SCAL_SINGLE_ISSUED_GRP141</td><td> Single Precision scalar instruction issued on Pipe0 </td><td> 1</td><td>	Group 141 pm_vsu13</td>

</tr>

<tr><td>PM_VSU1_SCAL_SINGLE_ISSUED_GRP141</td><td> Single Precision scalar instruction issued on Pipe1 </td><td> 2</td><td>	Group 141 pm_vsu13</td>

</tr>

<tr><td>PM_INST_CMPL_GRP141</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 141 pm_vsu13</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP141</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 141 pm_vsu13</td>

</tr>

<tr><td>PM_RUN_CYC_GRP141</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 141 pm_vsu13</td>

</tr>

<tr><td>PM_VSU_1FLOP_GRP142</td><td> one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished </td><td> 0</td><td>	Group 142 pm_vsu14</td>

</tr>

<tr><td>PM_VSU_4FLOP_GRP142</td><td> four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) </td><td> 1</td><td>	Group 142 pm_vsu14</td>

</tr>

<tr><td>PM_VSU_8FLOP_GRP142</td><td> eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) </td><td> 2</td><td>	Group 142 pm_vsu14</td>

</tr>

<tr><td>PM_VSU_2FLOP_GRP142</td><td> two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) </td><td> 3</td><td>	Group 142 pm_vsu14</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP142</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 142 pm_vsu14</td>

</tr>

<tr><td>PM_RUN_CYC_GRP142</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 142 pm_vsu14</td>

</tr>

<tr><td>PM_VSU_VECTOR_SINGLE_ISSUED_GRP143</td><td> Single Precision vector instruction issued (executed) </td><td> 0</td><td>	Group 143 pm_vsu15</td>

</tr>

<tr><td>PM_VSU0_VECTOR_SP_ISSUED_GRP143</td><td> Single Precision vector instruction issued (executed) </td><td> 1</td><td>	Group 143 pm_vsu15</td>

</tr>

<tr><td>PM_VSU0_FPSCR_GRP143</td><td> Move to/from FPSCR type instruction issued on Pipe 0 </td><td> 2</td><td>	Group 143 pm_vsu15</td>

</tr>

<tr><td>PM_INST_CMPL_GRP143</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 143 pm_vsu15</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP143</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 143 pm_vsu15</td>

</tr>

<tr><td>PM_RUN_CYC_GRP143</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 143 pm_vsu15</td>

</tr>

<tr><td>PM_VSU_SIMPLE_ISSUED_GRP144</td><td> Simple VMX instruction issued </td><td> 0</td><td>	Group 144 pm_vsu16</td>

</tr>

<tr><td>PM_VSU0_SIMPLE_ISSUED_GRP144</td><td> Simple VMX instruction issued </td><td> 1</td><td>	Group 144 pm_vsu16</td>

</tr>

<tr><td>PM_VSU0_COMPLEX_ISSUED_GRP144</td><td> Complex VMX instruction issued </td><td> 2</td><td>	Group 144 pm_vsu16</td>

</tr>

<tr><td>PM_VMX_RESULT_SAT_1_GRP144</td><td> Valid result with sat=1 </td><td> 3</td><td>	Group 144 pm_vsu16</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP144</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 144 pm_vsu16</td>

</tr>

<tr><td>PM_RUN_CYC_GRP144</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 144 pm_vsu16</td>

</tr>

<tr><td>PM_VSU1_DD_ISSUED_GRP145</td><td> 64BIT Decimal Issued on Pipe1 </td><td> 0</td><td>	Group 145 pm_vsu17</td>

</tr>

<tr><td>PM_VSU1_DQ_ISSUED_GRP145</td><td> 128BIT Decimal Issued on Pipe1 </td><td> 1</td><td>	Group 145 pm_vsu17</td>

</tr>

<tr><td>PM_VSU1_PERMUTE_ISSUED_GRP145</td><td> Permute VMX Instruction Issued </td><td> 2</td><td>	Group 145 pm_vsu17</td>

</tr>

<tr><td>PM_VSU1_SQ_GRP145</td><td> Store Vector Issued on Pipe1 </td><td> 3</td><td>	Group 145 pm_vsu17</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP145</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 145 pm_vsu17</td>

</tr>

<tr><td>PM_RUN_CYC_GRP145</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 145 pm_vsu17</td>

</tr>

<tr><td>PM_VSU_FCONV_GRP146</td><td> Convert instruction executed </td><td> 0</td><td>	Group 146 pm_vsu18</td>

</tr>

<tr><td>PM_VSU0_FCONV_GRP146</td><td> Convert instruction executed </td><td> 1</td><td>	Group 146 pm_vsu18</td>

</tr>

<tr><td>PM_VSU1_FCONV_GRP146</td><td> Convert instruction executed </td><td> 2</td><td>	Group 146 pm_vsu18</td>

</tr>

<tr><td>PM_INST_CMPL_GRP146</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 146 pm_vsu18</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP146</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 146 pm_vsu18</td>

</tr>

<tr><td>PM_RUN_CYC_GRP146</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 146 pm_vsu18</td>

</tr>

<tr><td>PM_VSU_FRSP_GRP147</td><td> Round to single precision instruction executed </td><td> 0</td><td>	Group 147 pm_vsu19</td>

</tr>

<tr><td>PM_VSU0_FRSP_GRP147</td><td> Round to single precision instruction executed </td><td> 1</td><td>	Group 147 pm_vsu19</td>

</tr>

<tr><td>PM_VSU1_FRSP_GRP147</td><td> Round to single precision instruction executed </td><td> 2</td><td>	Group 147 pm_vsu19</td>

</tr>

<tr><td>PM_INST_CMPL_GRP147</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 147 pm_vsu19</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP147</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 147 pm_vsu19</td>

</tr>

<tr><td>PM_RUN_CYC_GRP147</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 147 pm_vsu19</td>

</tr>

<tr><td>PM_VSU_FEST_GRP148</td><td> Estimate instruction executed </td><td> 0</td><td>	Group 148 pm_vsu20</td>

</tr>

<tr><td>PM_VSU0_FEST_GRP148</td><td> Estimate instruction executed </td><td> 1</td><td>	Group 148 pm_vsu20</td>

</tr>

<tr><td>PM_VSU1_FEST_GRP148</td><td> Estimate instruction executed </td><td> 2</td><td>	Group 148 pm_vsu20</td>

</tr>

<tr><td>PM_INST_CMPL_GRP148</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 148 pm_vsu20</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP148</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 148 pm_vsu20</td>

</tr>

<tr><td>PM_RUN_CYC_GRP148</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 148 pm_vsu20</td>

</tr>

<tr><td>PM_BRU_FIN_GRP149</td><td> The Branch execution unit finished an instruction </td><td> 0</td><td>	Group 149 pm_vsu21</td>

</tr>

<tr><td>PM_RUN_CYC_GRP149</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 1</td><td>	Group 149 pm_vsu21</td>

</tr>

<tr><td>PM_INST_CMPL_GRP149</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 149 pm_vsu21</td>

</tr>

<tr><td>PM_VSU_FIN_GRP149</td><td> VSU0 Finished an instruction </td><td> 3</td><td>	Group 149 pm_vsu21</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP149</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 149 pm_vsu21</td>

</tr>

<tr><td>PM_RUN_CYC_GRP149</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 149 pm_vsu21</td>

</tr>

<tr><td>PM_LSU_LDF_GRP150</td><td> LSU executed Floating Point load instruction. Combined Unit 0 + 1. </td><td> 0</td><td>	Group 150 pm_vsu22</td>

</tr>

<tr><td>PM_VSU_STF_GRP150</td><td> FPU store (SP or DP) issued on Pipe0 </td><td> 1</td><td>	Group 150 pm_vsu22</td>

</tr>

<tr><td>PM_VSU_FMA_GRP150</td><td> two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! </td><td> 2</td><td>	Group 150 pm_vsu22</td>

</tr>

<tr><td>PM_VSU_1FLOP_GRP150</td><td> one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished </td><td> 3</td><td>	Group 150 pm_vsu22</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP150</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 150 pm_vsu22</td>

</tr>

<tr><td>PM_RUN_CYC_GRP150</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 150 pm_vsu22</td>

</tr>

<tr><td>PM_VSU_FSQRT_FDIV_GRP151</td><td> DP vector versions of fdiv,fsqrt </td><td> 0</td><td>	Group 151 pm_vsu23</td>

</tr>

<tr><td>PM_VSU_FIN_GRP151</td><td> VSU0 Finished an instruction </td><td> 1</td><td>	Group 151 pm_vsu23</td>

</tr>

<tr><td>PM_VSU_FMA_GRP151</td><td> two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! </td><td> 2</td><td>	Group 151 pm_vsu23</td>

</tr>

<tr><td>PM_VSU_1FLOP_GRP151</td><td> one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished </td><td> 3</td><td>	Group 151 pm_vsu23</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP151</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 151 pm_vsu23</td>

</tr>

<tr><td>PM_RUN_CYC_GRP151</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 151 pm_vsu23</td>

</tr>

<tr><td>PM_FLOP_GRP152</td><td> A floating point operation has completed </td><td> 0</td><td>	Group 152 pm_vsu24</td>

</tr>

<tr><td>PM_VSU_FIN_GRP152</td><td> VSU0 Finished an instruction </td><td> 1</td><td>	Group 152 pm_vsu24</td>

</tr>

<tr><td>PM_VSU_FEST_GRP152</td><td> Estimate instruction executed </td><td> 2</td><td>	Group 152 pm_vsu24</td>

</tr>

<tr><td>PM_VSU_1FLOP_GRP152</td><td> one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished </td><td> 3</td><td>	Group 152 pm_vsu24</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP152</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 152 pm_vsu24</td>

</tr>

<tr><td>PM_RUN_CYC_GRP152</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 152 pm_vsu24</td>

</tr>

<tr><td>PM_VSU_STF_GRP153</td><td> FPU store (SP or DP) issued on Pipe0 </td><td> 0</td><td>	Group 153 pm_vsu25</td>

</tr>

<tr><td>PM_VSU_FIN_GRP153</td><td> VSU0 Finished an instruction </td><td> 1</td><td>	Group 153 pm_vsu25</td>

</tr>

<tr><td>PM_VSU_FRSP_GRP153</td><td> Round to single precision instruction executed </td><td> 2</td><td>	Group 153 pm_vsu25</td>

</tr>

<tr><td>PM_VSU_FCONV_GRP153</td><td> Convert instruction executed </td><td> 3</td><td>	Group 153 pm_vsu25</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP153</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 153 pm_vsu25</td>

</tr>

<tr><td>PM_RUN_CYC_GRP153</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 153 pm_vsu25</td>

</tr>

<tr><td>PM_LSU_LMQ_FULL_CYC_GRP154</td><td> The Load Miss Queue was full. </td><td> 0</td><td>	Group 154 pm_lsu1</td>

</tr>

<tr><td>PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP154</td><td> Cycles when both the LMQ and SRQ are empty (LSU is idle) </td><td> 1</td><td>	Group 154 pm_lsu1</td>

</tr>

<tr><td>PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC_GRP154</td><td> ALL threads lsu empty (lmq and srq empty) </td><td> 2</td><td>	Group 154 pm_lsu1</td>

</tr>

<tr><td>PM_LSU_SRQ_EMPTY_CYC_GRP154</td><td> The Store Request Queue is empty </td><td> 3</td><td>	Group 154 pm_lsu1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP154</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 154 pm_lsu1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP154</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 154 pm_lsu1</td>

</tr>

<tr><td>PM_LSU_FX_FIN_GRP155</td><td> LSU Finished a FX operation (up to 2 per cycle) </td><td> 0</td><td>	Group 155 pm_lsu2</td>

</tr>

<tr><td>PM_LSU_NCST_GRP155</td><td> Non-cachable Stores sent to nest </td><td> 1</td><td>	Group 155 pm_lsu2</td>

</tr>

<tr><td>PM_LSU_FIN_GRP155</td><td> LSU Finished an instruction (up to 2 per cycle) </td><td> 2</td><td>	Group 155 pm_lsu2</td>

</tr>

<tr><td>PM_LSU_FLUSH_GRP155</td><td> A flush was initiated by the Load Store Unit. </td><td> 3</td><td>	Group 155 pm_lsu2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP155</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 155 pm_lsu2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP155</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 155 pm_lsu2</td>

</tr>

<tr><td>PM_LSU0_LMQ_LHR_MERGE_GRP156</td><td> LS0 Load Merged with another cacheline request </td><td> 0</td><td>	Group 156 pm_lsu_lmq</td>

</tr>

<tr><td>PM_LSU1_LMQ_LHR_MERGE_GRP156</td><td> LS1 Load Merge with another cacheline request </td><td> 1</td><td>	Group 156 pm_lsu_lmq</td>

</tr>

<tr><td>PM_LSU_LMQ_S0_VALID_GRP156</td><td> This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each). </td><td> 2</td><td>	Group 156 pm_lsu_lmq</td>

</tr>

<tr><td>PM_LSU_LMQ_FULL_CYC_GRP156</td><td> The Load Miss Queue was full. </td><td> 3</td><td>	Group 156 pm_lsu_lmq</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP156</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 156 pm_lsu_lmq</td>

</tr>

<tr><td>PM_RUN_CYC_GRP156</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 156 pm_lsu_lmq</td>

</tr>

<tr><td>PM_LSU_SRQ_STFWD_GRP157</td><td> Data from a store instruction was forwarded to a load. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. Combined Unit 0 + 1. </td><td> 0</td><td>	Group 157 pm_lsu_srq1</td>

</tr>

<tr><td>PM_LSU0_SRQ_STFWD_GRP157</td><td> Data from a store instruction was forwarded to a load on unit 0. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. </td><td> 1</td><td>	Group 157 pm_lsu_srq1</td>

</tr>

<tr><td>PM_LSU1_SRQ_STFWD_GRP157</td><td> Data from a store instruction was forwarded to a load on unit 1. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. </td><td> 2</td><td>	Group 157 pm_lsu_srq1</td>

</tr>

<tr><td>PM_INST_CMPL_GRP157</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 157 pm_lsu_srq1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP157</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 157 pm_lsu_srq1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP157</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 157 pm_lsu_srq1</td>

</tr>

<tr><td>PM_LSU_SRQ_SYNC_CYC_GRP158</td><td> Cycles that a sync instruction is active in the Store Request Queue. </td><td> 0</td><td>	Group 158 pm_lsu_srq2</td>

</tr>

<tr><td>PM_LSU_SRQ_SYNC_COUNT_GRP158</td><td> SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC) </td><td> 1</td><td>	Group 158 pm_lsu_srq2</td>

</tr>

<tr><td>PM_LSU_SRQ_S0_VALID_GRP158</td><td> This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the SRQ is split between the two threads (16 entries each). </td><td> 2</td><td>	Group 158 pm_lsu_srq2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP158</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 158 pm_lsu_srq2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP158</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 158 pm_lsu_srq2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP158</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 158 pm_lsu_srq2</td>

</tr>

<tr><td>PM_LSU_SRQ_S0_VALID_GRP159</td><td> This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the SRQ is split between the two threads (16 entries each). </td><td> 0</td><td>	Group 159 pm_lsu_s0_valid</td>

</tr>

<tr><td>PM_LSU_LRQ_S0_VALID_GRP159</td><td> This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each). </td><td> 1</td><td>	Group 159 pm_lsu_s0_valid</td>

</tr>

<tr><td>PM_LSU_LMQ_S0_VALID_GRP159</td><td> This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each). </td><td> 2</td><td>	Group 159 pm_lsu_s0_valid</td>

</tr>

<tr><td>PM_INST_CMPL_GRP159</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 159 pm_lsu_s0_valid</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP159</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 159 pm_lsu_s0_valid</td>

</tr>

<tr><td>PM_RUN_CYC_GRP159</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 159 pm_lsu_s0_valid</td>

</tr>

<tr><td>PM_LSU_LMQ_S0_ALLOC_GRP160</td><td> Slot 0 of LMQ valid </td><td> 0</td><td>	Group 160 pm_lsu_s0_alloc</td>

</tr>

<tr><td>PM_LSU_LRQ_S0_ALLOC_GRP160</td><td> Slot 0 of LRQ valid </td><td> 1</td><td>	Group 160 pm_lsu_s0_alloc</td>

</tr>

<tr><td>PM_LSU_SRQ_S0_ALLOC_GRP160</td><td> Slot 0 of SRQ valid </td><td> 2</td><td>	Group 160 pm_lsu_s0_alloc</td>

</tr>

<tr><td>PM_INST_CMPL_GRP160</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 160 pm_lsu_s0_alloc</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP160</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 160 pm_lsu_s0_alloc</td>

</tr>

<tr><td>PM_RUN_CYC_GRP160</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 160 pm_lsu_s0_alloc</td>

</tr>

<tr><td>PM_L1_PREF_GRP161</td><td> A request to prefetch data into the L1 was made </td><td> 0</td><td>	Group 161 pm_l1_pref</td>

</tr>

<tr><td>PM_LSU0_L1_PREF_GRP161</td><td> LS0 L1 cache data prefetches </td><td> 1</td><td>	Group 161 pm_l1_pref</td>

</tr>

<tr><td>PM_LSU1_L1_PREF_GRP161</td><td> LS1 L1 cache data prefetches </td><td> 2</td><td>	Group 161 pm_l1_pref</td>

</tr>

<tr><td>PM_INST_CMPL_GRP161</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 161 pm_l1_pref</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP161</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 161 pm_l1_pref</td>

</tr>

<tr><td>PM_RUN_CYC_GRP161</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 161 pm_l1_pref</td>

</tr>

<tr><td>PM_L2_LOC_GUESS_CORRECT_GRP162</td><td> L2 guess loc and guess was correct (ie data local) </td><td> 0</td><td>	Group 162 pm_l2_guess_1</td>

</tr>

<tr><td>PM_L2_LOC_GUESS_WRONG_GRP162</td><td> L2 guess loc and guess was not correct (ie data remote) </td><td> 1</td><td>	Group 162 pm_l2_guess_1</td>

</tr>

<tr><td>PM_CYC_GRP162</td><td> Processor Cycles </td><td> 2</td><td>	Group 162 pm_l2_guess_1</td>

</tr>

<tr><td>PM_INST_CMPL_GRP162</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 162 pm_l2_guess_1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP162</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 162 pm_l2_guess_1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP162</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 162 pm_l2_guess_1</td>

</tr>

<tr><td>PM_L2_GLOB_GUESS_CORRECT_GRP163</td><td> L2 guess glb and guess was correct (ie data remote) </td><td> 0</td><td>	Group 163 pm_l2_guess_2</td>

</tr>

<tr><td>PM_L2_GLOB_GUESS_WRONG_GRP163</td><td> L2 guess glb and guess was not correct (ie data local) </td><td> 1</td><td>	Group 163 pm_l2_guess_2</td>

</tr>

<tr><td>PM_CYC_GRP163</td><td> Processor Cycles </td><td> 2</td><td>	Group 163 pm_l2_guess_2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP163</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 163 pm_l2_guess_2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP163</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 163 pm_l2_guess_2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP163</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 163 pm_l2_guess_2</td>

</tr>

<tr><td>PM_INST_IMC_MATCH_CMPL_GRP164</td><td> Number of instructions resulting from the marked instructions expansion that completed. </td><td> 0</td><td>	Group 164 pm_misc1</td>

</tr>

<tr><td>PM_INST_FROM_L1_GRP164</td><td> An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions </td><td> 1</td><td>	Group 164 pm_misc1</td>

</tr>

<tr><td>PM_INST_IMC_MATCH_DISP_GRP164</td><td> IMC Matches dispatched </td><td> 2</td><td>	Group 164 pm_misc1</td>

</tr>

<tr><td>PM_INST_CMPL_GRP164</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 164 pm_misc1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP164</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 164 pm_misc1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP164</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 164 pm_misc1</td>

</tr>

<tr><td>PM_EE_OFF_EXT_INT_GRP165</td><td> Cycles when an interrupt due to an external exception is pending but external exceptions were masked. </td><td> 0</td><td>	Group 165 pm_misc2</td>

</tr>

<tr><td>PM_EXT_INT_GRP165</td><td> An interrupt due to an external exception occurred </td><td> 1</td><td>	Group 165 pm_misc2</td>

</tr>

<tr><td>PM_TB_BIT_TRANS_GRP165</td><td> When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 </td><td> 2</td><td>	Group 165 pm_misc2</td>

</tr>

<tr><td>PM_CYC_GRP165</td><td> Processor Cycles </td><td> 3</td><td>	Group 165 pm_misc2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP165</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 165 pm_misc2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP165</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 165 pm_misc2</td>

</tr>

<tr><td>PM_1PLUS_PPC_CMPL_GRP166</td><td> A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once. </td><td> 0</td><td>	Group 166 pm_misc3</td>

</tr>

<tr><td>PM_HV_CYC_GRP166</td><td> Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0) </td><td> 1</td><td>	Group 166 pm_misc3</td>

</tr>

<tr><td>PM_INST_DISP_GRP166</td><td> Number of PowerPC instructions successfully dispatched. </td><td> 2</td><td>	Group 166 pm_misc3</td>

</tr>

<tr><td>PM_1PLUS_PPC_DISP_GRP166</td><td> A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once. </td><td> 3</td><td>	Group 166 pm_misc3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP166</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 166 pm_misc3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP166</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 166 pm_misc3</td>

</tr>

<tr><td>PM_GRP_IC_MISS_NONSPEC_GRP167</td><td> Number of groups, counted at completion, that have encountered an instruction cache miss. </td><td> 0</td><td>	Group 167 pm_misc4</td>

</tr>

<tr><td>PM_GCT_NOSLOT_IC_MISS_GRP167</td><td> Cycles when the Global Completion Table has no slots from this thread because of an Instruction Cache miss. </td><td> 1</td><td>	Group 167 pm_misc4</td>

</tr>

<tr><td>PM_CYC_GRP167</td><td> Processor Cycles </td><td> 2</td><td>	Group 167 pm_misc4</td>

</tr>

<tr><td>PM_GCT_NOSLOT_BR_MPRED_IC_MISS_GRP167</td><td> No slot in GCT caused by branch mispredict or I cache miss </td><td> 3</td><td>	Group 167 pm_misc4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP167</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 167 pm_misc4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP167</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 167 pm_misc4</td>

</tr>

<tr><td>PM_GRP_BR_MPRED_NONSPEC_GRP168</td><td> Group experienced non-speculative branch redirect </td><td> 0</td><td>	Group 168 pm_misc5</td>

</tr>

<tr><td>PM_BR_MPRED_CR_TA_GRP168</td><td> Branch mispredict - taken/not taken and target </td><td> 1</td><td>	Group 168 pm_misc5</td>

</tr>

<tr><td>PM_BR_MPRED_CCACHE_GRP168</td><td> A branch instruction target was incorrectly predicted by the count cache. This will result in a branch redirect flush if not overwritten by a flush of an older instruction. </td><td> 2</td><td>	Group 168 pm_misc5</td>

</tr>

<tr><td>PM_BR_MPRED_GRP168</td><td> A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both </td><td> 3</td><td>	Group 168 pm_misc5</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP168</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 168 pm_misc5</td>

</tr>

<tr><td>PM_RUN_CYC_GRP168</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 168 pm_misc5</td>

</tr>

<tr><td>PM_L1_DEMAND_WRITE_GRP169</td><td> Instruction Demand sectors wriittent into IL1 </td><td> 0</td><td>	Group 169 pm_misc6</td>

</tr>

<tr><td>PM_IC_PREF_WRITE_GRP169</td><td> Number of Instruction Cache entries written because of prefetch. Prefetch entries are marked least recently used and are candidates for eviction if they are not needed to satify a demand fetch. </td><td> 1</td><td>	Group 169 pm_misc6</td>

</tr>

<tr><td>PM_IC_WRITE_ALL_GRP169</td><td> Icache sectors written, prefetch + demand </td><td> 2</td><td>	Group 169 pm_misc6</td>

</tr>

<tr><td>PM_INST_CMPL_GRP169</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 169 pm_misc6</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP169</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 169 pm_misc6</td>

</tr>

<tr><td>PM_RUN_CYC_GRP169</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 169 pm_misc6</td>

</tr>

<tr><td>PM_THRESH_TIMEO_GRP170</td><td> The threshold timer expired </td><td> 0</td><td>	Group 170 pm_misc7</td>

</tr>

<tr><td>PM_HV_CYC_GRP170</td><td> Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0) </td><td> 1</td><td>	Group 170 pm_misc7</td>

</tr>

<tr><td>PM_CYC_GRP170</td><td> Processor Cycles </td><td> 2</td><td>	Group 170 pm_misc7</td>

</tr>

<tr><td>PM_IFU_FIN_GRP170</td><td> The Instruction Fetch Unit finished an instruction </td><td> 3</td><td>	Group 170 pm_misc7</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP170</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 170 pm_misc7</td>

</tr>

<tr><td>PM_RUN_CYC_GRP170</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 170 pm_misc7</td>

</tr>

<tr><td>PM_BR_MPRED_LSTACK_GRP171</td><td> Branch Mispredict due to Link Stack </td><td> 0</td><td>	Group 171 pm_misc8</td>

</tr>

<tr><td>PM_EXT_INT_GRP171</td><td> An interrupt due to an external exception occurred </td><td> 1</td><td>	Group 171 pm_misc8</td>

</tr>

<tr><td>PM_L1_DCACHE_RELOAD_VALID_GRP171</td><td> The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads. </td><td> 2</td><td>	Group 171 pm_misc8</td>

</tr>

<tr><td>PM_BR_MPRED_GRP171</td><td> A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both </td><td> 3</td><td>	Group 171 pm_misc8</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP171</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 171 pm_misc8</td>

</tr>

<tr><td>PM_RUN_CYC_GRP171</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 171 pm_misc8</td>

</tr>

<tr><td>PM_FLUSH_BR_MPRED_GRP172</td><td> A flush was caused by a branch mispredict. </td><td> 0</td><td>	Group 172 pm_misc9</td>

</tr>

<tr><td>PM_FLUSH_PARTIAL_GRP172</td><td> Partial flush </td><td> 1</td><td>	Group 172 pm_misc9</td>

</tr>

<tr><td>PM_LSU_SET_MPRED_GRP172</td><td> Line already in cache at reload time </td><td> 2</td><td>	Group 172 pm_misc9</td>

</tr>

<tr><td>PM_BR_MPRED_GRP172</td><td> A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both </td><td> 3</td><td>	Group 172 pm_misc9</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP172</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 172 pm_misc9</td>

</tr>

<tr><td>PM_RUN_CYC_GRP172</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 172 pm_misc9</td>

</tr>

<tr><td>PM_LSU_SRQ_FULL_CYC_GRP173</td><td> Cycles the Store Request Queue is full. </td><td> 0</td><td>	Group 173 pm_misc10</td>

</tr>

<tr><td>PM_LSU_DC_PREF_STREAM_ALLOC_GRP173</td><td> D cache new prefetch stream allocated </td><td> 1</td><td>	Group 173 pm_misc10</td>

</tr>

<tr><td>PM_L1_PREF_GRP173</td><td> A request to prefetch data into the L1 was made </td><td> 2</td><td>	Group 173 pm_misc10</td>

</tr>

<tr><td>PM_IBUF_FULL_CYC_GRP173</td><td> Cycles with the Instruction Buffer was full. The Instruction Buffer is a circular queue of 64 instructions per thread, organized as 16 groups of 4 instructions. </td><td> 3</td><td>	Group 173 pm_misc10</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP173</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 173 pm_misc10</td>

</tr>

<tr><td>PM_RUN_CYC_GRP173</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 173 pm_misc10</td>

</tr>

<tr><td>PM_FLOP_GRP174</td><td> A floating point operation has completed </td><td> 0</td><td>	Group 174 pm_misc11</td>

</tr>

<tr><td>PM_CYC_GRP174</td><td> Processor Cycles </td><td> 1</td><td>	Group 174 pm_misc11</td>

</tr>

<tr><td>PM_GRP_CMPL_GRP174</td><td> A group completed. Microcoded instructions that span multiple groups will generate this event once per group. </td><td> 2</td><td>	Group 174 pm_misc11</td>

</tr>

<tr><td>PM_INST_CMPL_GRP174</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 174 pm_misc11</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP174</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 174 pm_misc11</td>

</tr>

<tr><td>PM_RUN_CYC_GRP174</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 174 pm_misc11</td>

</tr>

<tr><td>PM_INST_CMPL_GRP175</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 175 pm_misc_12</td>

</tr>

<tr><td>PM_ST_FIN_GRP175</td><td> Store requests sent to the nest. </td><td> 1</td><td>	Group 175 pm_misc_12</td>

</tr>

<tr><td>PM_TB_BIT_TRANS_GRP175</td><td> When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 </td><td> 2</td><td>	Group 175 pm_misc_12</td>

</tr>

<tr><td>PM_FLUSH_GRP175</td><td> Flushes occurred including LSU and Branch flushes. </td><td> 3</td><td>	Group 175 pm_misc_12</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP175</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 175 pm_misc_12</td>

</tr>

<tr><td>PM_RUN_CYC_GRP175</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 175 pm_misc_12</td>

</tr>

<tr><td>PM_GCT_NOSLOT_CYC_GRP176</td><td> Cycles when the Global Completion Table has no slots from this thread. </td><td> 0</td><td>	Group 176 pm_misc_13</td>

</tr>

<tr><td>PM_ST_FIN_GRP176</td><td> Store requests sent to the nest. </td><td> 1</td><td>	Group 176 pm_misc_13</td>

</tr>

<tr><td>PM_DTLB_MISS_GRP176</td><td> Data TLB misses, all page sizes. </td><td> 2</td><td>	Group 176 pm_misc_13</td>

</tr>

<tr><td>PM_BR_MPRED_GRP176</td><td> A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both </td><td> 3</td><td>	Group 176 pm_misc_13</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP176</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 176 pm_misc_13</td>

</tr>

<tr><td>PM_RUN_CYC_GRP176</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 176 pm_misc_13</td>

</tr>

<tr><td>PM_CYC_GRP177</td><td> Processor Cycles </td><td> 0</td><td>	Group 177 pm_misc_14</td>

</tr>

<tr><td>PM_CYC_GRP177</td><td> Processor Cycles </td><td> 1</td><td>	Group 177 pm_misc_14</td>

</tr>

<tr><td>PM_INST_CMPL_GRP177</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 177 pm_misc_14</td>

</tr>

<tr><td>PM_IFU_FIN_GRP177</td><td> The Instruction Fetch Unit finished an instruction </td><td> 3</td><td>	Group 177 pm_misc_14</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP177</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 177 pm_misc_14</td>

</tr>

<tr><td>PM_RUN_CYC_GRP177</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 177 pm_misc_14</td>

</tr>

<tr><td>PM_LSU_DCACHE_RELOAD_VALID_GRP178</td><td> count per sector of lines reloaded in L1 (demand + prefetch) </td><td> 0</td><td>	Group 178 pm_misc_15</td>

</tr>

<tr><td>PM_CMPLU_STALL_STORE_GRP178</td><td> Completion stall due to store instruction </td><td> 1</td><td>	Group 178 pm_misc_15</td>

</tr>

<tr><td>PM_L1_DCACHE_RELOAD_VALID_GRP178</td><td> The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads. </td><td> 2</td><td>	Group 178 pm_misc_15</td>

</tr>

<tr><td>PM_CMPLU_STALL_VECTOR_LONG_GRP178</td><td> completion stall due to long latency vector instruction </td><td> 3</td><td>	Group 178 pm_misc_15</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP178</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 178 pm_misc_15</td>

</tr>

<tr><td>PM_RUN_CYC_GRP178</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 178 pm_misc_15</td>

</tr>

<tr><td>PM_CMPLU_STALL_END_GCT_NOSLOT_GRP179</td><td> Count ended because GCT went empty </td><td> 0</td><td>	Group 179 pm_misc_16</td>

</tr>

<tr><td>PM_LSU0_L1_SW_PREF_GRP179</td><td> LSU0 Software L1 Prefetches, including SW Transient Prefetches </td><td> 1</td><td>	Group 179 pm_misc_16</td>

</tr>

<tr><td>PM_LSU1_L1_SW_PREF_GRP179</td><td> LSU1 Software L1 Prefetches, including SW Transient Prefetches </td><td> 2</td><td>	Group 179 pm_misc_16</td>

</tr>

<tr><td>PM_CMPLU_STALL_IFU_GRP179</td><td> Completion stall due to IFU </td><td> 3</td><td>	Group 179 pm_misc_16</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP179</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 179 pm_misc_16</td>

</tr>

<tr><td>PM_RUN_CYC_GRP179</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 179 pm_misc_16</td>

</tr>

<tr><td>PM_BRU_FIN_GRP180</td><td> The Branch execution unit finished an instruction </td><td> 0</td><td>	Group 180 pm_misc_17</td>

</tr>

<tr><td>PM_ST_FIN_GRP180</td><td> Store requests sent to the nest. </td><td> 1</td><td>	Group 180 pm_misc_17</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_DL2L3_SHR_GRP180</td><td> A Page Table Entry was loaded into the ERAT from memory attached to a different module than this processor is located on due to a marked load or store. </td><td> 2</td><td>	Group 180 pm_misc_17</td>

</tr>

<tr><td>PM_CMPLU_STALL_BRU_GRP180</td><td> Completion stall due to BRU </td><td> 3</td><td>	Group 180 pm_misc_17</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP180</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 180 pm_misc_17</td>

</tr>

<tr><td>PM_RUN_CYC_GRP180</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 180 pm_misc_17</td>

</tr>

<tr><td>PM_SUSPENDED_GRP181</td><td> The counter is suspended (does not count) </td><td> 0</td><td>	Group 181 pm_suspend</td>

</tr>

<tr><td>PM_CYC_GRP181</td><td> Processor Cycles </td><td> 1</td><td>	Group 181 pm_suspend</td>

</tr>

<tr><td>PM_LWSYNC_GRP181</td><td> lwsync count (easier to use than IMC) </td><td> 2</td><td>	Group 181 pm_suspend</td>

</tr>

<tr><td>PM_INST_CMPL_GRP181</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 181 pm_suspend</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP181</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 181 pm_suspend</td>

</tr>

<tr><td>PM_RUN_CYC_GRP181</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 181 pm_suspend</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP182</td><td> Number of internal operations that completed. </td><td> 0</td><td>	Group 182 pm_iops</td>

</tr>

<tr><td>PM_CYC_GRP182</td><td> Processor Cycles </td><td> 1</td><td>	Group 182 pm_iops</td>

</tr>

<tr><td>PM_IOPS_DISP_GRP182</td><td> IOPS dispatched </td><td> 2</td><td>	Group 182 pm_iops</td>

</tr>

<tr><td>PM_INST_CMPL_GRP182</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 182 pm_iops</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP182</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 182 pm_iops</td>

</tr>

<tr><td>PM_RUN_CYC_GRP182</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 182 pm_iops</td>

</tr>

<tr><td>PM_LWSYNC_GRP183</td><td> lwsync count (easier to use than IMC) </td><td> 0</td><td>	Group 183 pm_sync</td>

</tr>

<tr><td>PM_CYC_GRP183</td><td> Processor Cycles </td><td> 1</td><td>	Group 183 pm_sync</td>

</tr>

<tr><td>PM_LWSYNC_HELD_GRP183</td><td> Cycles a LWSYNC instruction was held at dispatch. LWSYNC instructions are held at dispatch until all previous loads are done and all previous stores have issued. LWSYNC enters the Store Request Queue and is sent to the storage subsystem but does not wait for a response. </td><td> 2</td><td>	Group 183 pm_sync</td>

</tr>

<tr><td>PM_INST_CMPL_GRP183</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 183 pm_sync</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP183</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 183 pm_sync</td>

</tr>

<tr><td>PM_RUN_CYC_GRP183</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 183 pm_sync</td>

</tr>

<tr><td>PM_CYC_GRP184</td><td> Processor Cycles </td><td> 0</td><td>	Group 184 pm_seg</td>

</tr>

<tr><td>PM_SEG_EXCEPTION_GRP184</td><td> ISEG + DSEG Exception </td><td> 1</td><td>	Group 184 pm_seg</td>

</tr>

<tr><td>PM_ISEG_GRP184</td><td> ISEG Exception </td><td> 2</td><td>	Group 184 pm_seg</td>

</tr>

<tr><td>PM_DSEG_GRP184</td><td> DSEG Exception </td><td> 3</td><td>	Group 184 pm_seg</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP184</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 184 pm_seg</td>

</tr>

<tr><td>PM_RUN_CYC_GRP184</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 184 pm_seg</td>

</tr>

<tr><td>PM_L3_HIT_GRP185</td><td> L3 Hits </td><td> 0</td><td>	Group 185 pm_l3_hit</td>

</tr>

<tr><td>PM_L3_LD_HIT_GRP185</td><td> L3 demand LD Hits </td><td> 1</td><td>	Group 185 pm_l3_hit</td>

</tr>

<tr><td>PM_L3_PREF_HIT_GRP185</td><td> L3 Prefetch Directory Hit </td><td> 2</td><td>	Group 185 pm_l3_hit</td>

</tr>

<tr><td>PM_L3_CO_L31_GRP185</td><td> L3 Castouts to L3.1 </td><td> 3</td><td>	Group 185 pm_l3_hit</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP185</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 185 pm_l3_hit</td>

</tr>

<tr><td>PM_RUN_CYC_GRP185</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 185 pm_l3_hit</td>

</tr>

<tr><td>PM_SHL_DEALLOCATED_GRP186</td><td> SHL Table entry deallocated </td><td> 0</td><td>	Group 186 pm_shl</td>

</tr>

<tr><td>PM_SHL_CREATED_GRP186</td><td> SHL table entry Created </td><td> 1</td><td>	Group 186 pm_shl</td>

</tr>

<tr><td>PM_SHL_MERGED_GRP186</td><td> SHL table entry merged with existing </td><td> 2</td><td>	Group 186 pm_shl</td>

</tr>

<tr><td>PM_SHL_MATCH_GRP186</td><td> SHL Table Match </td><td> 3</td><td>	Group 186 pm_shl</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP186</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 186 pm_shl</td>

</tr>

<tr><td>PM_RUN_CYC_GRP186</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 186 pm_shl</td>

</tr>

<tr><td>PM_L3_PREF_LD_GRP187</td><td> L3 cache LD prefetches </td><td> 0</td><td>	Group 187 pm_l3_pref</td>

</tr>

<tr><td>PM_L3_PREF_ST_GRP187</td><td> L3 cache ST prefetches </td><td> 1</td><td>	Group 187 pm_l3_pref</td>

</tr>

<tr><td>PM_L3_PREF_LDST_GRP187</td><td> L3 cache prefetches LD + ST </td><td> 2</td><td>	Group 187 pm_l3_pref</td>

</tr>

<tr><td>PM_L1_PREF_GRP187</td><td> A request to prefetch data into the L1 was made </td><td> 3</td><td>	Group 187 pm_l3_pref</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP187</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 187 pm_l3_pref</td>

</tr>

<tr><td>PM_RUN_CYC_GRP187</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 187 pm_l3_pref</td>

</tr>

<tr><td>PM_L3_MISS_GRP188</td><td> L3 Misses </td><td> 0</td><td>	Group 188 pm_l3</td>

</tr>

<tr><td>PM_L3_LD_MISS_GRP188</td><td> L3 demand LD Miss </td><td> 1</td><td>	Group 188 pm_l3</td>

</tr>

<tr><td>PM_L3_PREF_MISS_GRP188</td><td> L3 Prefetch Directory Miss </td><td> 2</td><td>	Group 188 pm_l3</td>

</tr>

<tr><td>PM_L3_CO_MEM_GRP188</td><td> L3 Castouts to Memory </td><td> 3</td><td>	Group 188 pm_l3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP188</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 188 pm_l3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP188</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 188 pm_l3</td>

</tr>

<tr><td>PM_CYC_GRP189</td><td> Processor Cycles </td><td> 0</td><td>	Group 189 pm_streams1</td>

</tr>

<tr><td>PM_LSU_DC_PREF_STREAM_CONFIRM_GRP189</td><td> Dcache new prefetch stream confirmed </td><td> 1</td><td>	Group 189 pm_streams1</td>

</tr>

<tr><td>PM_LSU0_DC_PREF_STREAM_CONFIRM_GRP189</td><td> LS0 Dcache prefetch stream confirmed </td><td> 2</td><td>	Group 189 pm_streams1</td>

</tr>

<tr><td>PM_LSU1_DC_PREF_STREAM_CONFIRM_GRP189</td><td> LS1 'Dcache prefetch stream confirmed </td><td> 3</td><td>	Group 189 pm_streams1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP189</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 189 pm_streams1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP189</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 189 pm_streams1</td>

</tr>

<tr><td>PM_CYC_GRP190</td><td> Processor Cycles </td><td> 0</td><td>	Group 190 pm_streams2</td>

</tr>

<tr><td>PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM_GRP190</td><td> Dcache Strided prefetch stream confirmed (software + hardware) </td><td> 1</td><td>	Group 190 pm_streams2</td>

</tr>

<tr><td>PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE_GRP190</td><td> LS0 Dcache Strided prefetch stream confirmed </td><td> 2</td><td>	Group 190 pm_streams2</td>

</tr>

<tr><td>PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE_GRP190</td><td> LS1 Dcache Strided prefetch stream confirmed </td><td> 3</td><td>	Group 190 pm_streams2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP190</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 190 pm_streams2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP190</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 190 pm_streams2</td>

</tr>

<tr><td>PM_DC_PREF_DST_GRP191</td><td> A prefetch stream was started using the DST instruction. </td><td> 0</td><td>	Group 191 pm_streams3</td>

</tr>

<tr><td>PM_LSU_DC_PREF_STREAM_ALLOC_GRP191</td><td> D cache new prefetch stream allocated </td><td> 1</td><td>	Group 191 pm_streams3</td>

</tr>

<tr><td>PM_LSU0_DC_PREF_STREAM_ALLOC_GRP191</td><td> LS0 D cache new prefetch stream allocated </td><td> 2</td><td>	Group 191 pm_streams3</td>

</tr>

<tr><td>PM_LSU1_DC_PREF_STREAM_ALLOC_GRP191</td><td> LS 1 D cache new prefetch stream allocated </td><td> 3</td><td>	Group 191 pm_streams3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP191</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 191 pm_streams3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP191</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 191 pm_streams3</td>

</tr>

<tr><td>PM_LARX_LSU0_GRP192</td><td> A larx (lwarx or ldarx) was executed on side 0 </td><td> 0</td><td>	Group 192 pm_larx</td>

</tr>

<tr><td>PM_LARX_LSU1_GRP192</td><td> A larx (lwarx or ldarx) was executed on side 1 </td><td> 1</td><td>	Group 192 pm_larx</td>

</tr>

<tr><td>PM_CYC_GRP192</td><td> Processor Cycles </td><td> 2</td><td>	Group 192 pm_larx</td>

</tr>

<tr><td>PM_LARX_LSU_GRP192</td><td> Larx Finished </td><td> 3</td><td>	Group 192 pm_larx</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP192</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 192 pm_larx</td>

</tr>

<tr><td>PM_RUN_CYC_GRP192</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 192 pm_larx</td>

</tr>

<tr><td>PM_CYC_GRP193</td><td> Processor Cycles </td><td> 0</td><td>	Group 193 pm_ldf</td>

</tr>

<tr><td>PM_LSU_LDF_GRP193</td><td> LSU executed Floating Point load instruction. Combined Unit 0 + 1. </td><td> 1</td><td>	Group 193 pm_ldf</td>

</tr>

<tr><td>PM_LSU0_LDF_GRP193</td><td> A floating point load was executed by LSU0 </td><td> 2</td><td>	Group 193 pm_ldf</td>

</tr>

<tr><td>PM_LSU1_LDF_GRP193</td><td> A floating point load was executed by LSU1 </td><td> 3</td><td>	Group 193 pm_ldf</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP193</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 193 pm_ldf</td>

</tr>

<tr><td>PM_RUN_CYC_GRP193</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 193 pm_ldf</td>

</tr>

<tr><td>PM_CYC_GRP194</td><td> Processor Cycles </td><td> 0</td><td>	Group 194 pm_ldx</td>

</tr>

<tr><td>PM_LSU_LDX_GRP194</td><td> All Vector loads (vsx vector + vmx vector) </td><td> 1</td><td>	Group 194 pm_ldx</td>

</tr>

<tr><td>PM_LSU0_LDX_GRP194</td><td> LS0 Vector Loads </td><td> 2</td><td>	Group 194 pm_ldx</td>

</tr>

<tr><td>PM_LSU1_LDX_GRP194</td><td> LS1 Vector Loads </td><td> 3</td><td>	Group 194 pm_ldx</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP194</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 194 pm_ldx</td>

</tr>

<tr><td>PM_RUN_CYC_GRP194</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 194 pm_ldx</td>

</tr>

<tr><td>PM_L2_LD_GRP195</td><td> Data Load Count </td><td> 0</td><td>	Group 195 pm_l2_ld_st</td>

</tr>

<tr><td>PM_L2_ST_MISS_GRP195</td><td> Data Store Miss </td><td> 1</td><td>	Group 195 pm_l2_ld_st</td>

</tr>

<tr><td>PM_L3_PREF_HIT_GRP195</td><td> L3 Prefetch Directory Hit </td><td> 2</td><td>	Group 195 pm_l2_ld_st</td>

</tr>

<tr><td>PM_CYC_GRP195</td><td> Processor Cycles </td><td> 3</td><td>	Group 195 pm_l2_ld_st</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP195</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 195 pm_l2_ld_st</td>

</tr>

<tr><td>PM_RUN_CYC_GRP195</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 195 pm_l2_ld_st</td>

</tr>

<tr><td>PM_LARX_LSU_GRP196</td><td> Larx Finished </td><td> 0</td><td>	Group 196 pm_stcx</td>

</tr>

<tr><td>PM_LSU_REJECT_LHS_GRP196</td><td> The Load Store Unit rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. Combined Unit 0 + 1 </td><td> 1</td><td>	Group 196 pm_stcx</td>

</tr>

<tr><td>PM_STCX_CMPL_GRP196</td><td> Conditional stores with reservation completed </td><td> 2</td><td>	Group 196 pm_stcx</td>

</tr>

<tr><td>PM_STCX_FAIL_GRP196</td><td> A stcx (stwcx or stdcx) failed </td><td> 3</td><td>	Group 196 pm_stcx</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP196</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 196 pm_stcx</td>

</tr>

<tr><td>PM_RUN_CYC_GRP196</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 196 pm_stcx</td>

</tr>

<tr><td>PM_BTAC_HIT_GRP197</td><td> BTAC Correct Prediction </td><td> 0</td><td>	Group 197 pm_btac</td>

</tr>

<tr><td>PM_BTAC_MISS_GRP197</td><td> BTAC Mispredicted </td><td> 1</td><td>	Group 197 pm_btac</td>

</tr>

<tr><td>PM_STCX_CMPL_GRP197</td><td> Conditional stores with reservation completed </td><td> 2</td><td>	Group 197 pm_btac</td>

</tr>

<tr><td>PM_STCX_FAIL_GRP197</td><td> A stcx (stwcx or stdcx) failed </td><td> 3</td><td>	Group 197 pm_btac</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP197</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 197 pm_btac</td>

</tr>

<tr><td>PM_RUN_CYC_GRP197</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 197 pm_btac</td>

</tr>

<tr><td>PM_BC_PLUS_8_CONV_GRP198</td><td> BC+8 Converted </td><td> 0</td><td>	Group 198 pm_br_bc</td>

</tr>

<tr><td>PM_BC_PLUS_8_RSLV_TAKEN_GRP198</td><td> BC+8 Resolve outcome was Taken, resulting in the conditional instruction being canceled </td><td> 1</td><td>	Group 198 pm_br_bc</td>

</tr>

<tr><td>PM_CYC_GRP198</td><td> Processor Cycles </td><td> 2</td><td>	Group 198 pm_br_bc</td>

</tr>

<tr><td>PM_INST_CMPL_GRP198</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 198 pm_br_bc</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP198</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 198 pm_br_bc</td>

</tr>

<tr><td>PM_RUN_CYC_GRP198</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 198 pm_br_bc</td>

</tr>

<tr><td>PM_INST_IMC_MATCH_CMPL_GRP199</td><td> Number of instructions resulting from the marked instructions expansion that completed. </td><td> 0</td><td>	Group 199 pm_inst_imc</td>

</tr>

<tr><td>PM_INST_DISP_GRP199</td><td> Number of PowerPC instructions successfully dispatched. </td><td> 1</td><td>	Group 199 pm_inst_imc</td>

</tr>

<tr><td>PM_INST_IMC_MATCH_DISP_GRP199</td><td> IMC Matches dispatched </td><td> 2</td><td>	Group 199 pm_inst_imc</td>

</tr>

<tr><td>PM_INST_CMPL_GRP199</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 199 pm_inst_imc</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP199</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 199 pm_inst_imc</td>

</tr>

<tr><td>PM_RUN_CYC_GRP199</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 199 pm_inst_imc</td>

</tr>

<tr><td>PM_L2_LDST_GRP200</td><td> Data Load+Store Count </td><td> 0</td><td>	Group 200 pm_l2_misc1</td>

</tr>

<tr><td>PM_L2_LDST_MISS_GRP200</td><td> Data Load+Store Miss </td><td> 1</td><td>	Group 200 pm_l2_misc1</td>

</tr>

<tr><td>PM_L2_INST_MISS_GRP200</td><td> Instruction Load Misses </td><td> 2</td><td>	Group 200 pm_l2_misc1</td>

</tr>

<tr><td>PM_L2_DISP_ALL_GRP200</td><td> All successful LD/ST dispatches for this thread(i+d) </td><td> 3</td><td>	Group 200 pm_l2_misc1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP200</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 200 pm_l2_misc1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP200</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 200 pm_l2_misc1</td>

</tr>

<tr><td>PM_INST_CMPL_GRP201</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 201 pm_l2_misc2</td>

</tr>

<tr><td>PM_CYC_GRP201</td><td> Processor Cycles </td><td> 1</td><td>	Group 201 pm_l2_misc2</td>

</tr>

<tr><td>PM_L2_INST_GRP201</td><td> Instruction Load Count </td><td> 2</td><td>	Group 201 pm_l2_misc2</td>

</tr>

<tr><td>PM_L2_DISP_ALL_GRP201</td><td> All successful LD/ST dispatches for this thread(i+d) </td><td> 3</td><td>	Group 201 pm_l2_misc2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP201</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 201 pm_l2_misc2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP201</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 201 pm_l2_misc2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP202</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 202 pm_l2_misc3</td>

</tr>

<tr><td>PM_CYC_GRP202</td><td> Processor Cycles </td><td> 1</td><td>	Group 202 pm_l2_misc3</td>

</tr>

<tr><td>PM_L2_SYS_PUMP_GRP202</td><td> RC req that was a global (aka system) pump attempt </td><td> 2</td><td>	Group 202 pm_l2_misc3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP202</td><td> Number of run instructions completed. </td><td> 3</td><td>	Group 202 pm_l2_misc3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP202</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 202 pm_l2_misc3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP202</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 202 pm_l2_misc3</td>

</tr>

<tr><td>PM_INST_CMPL_GRP203</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 203 pm_l2_misc4</td>

</tr>

<tr><td>PM_CYC_GRP203</td><td> Processor Cycles </td><td> 1</td><td>	Group 203 pm_l2_misc4</td>

</tr>

<tr><td>PM_L2_SN_SX_I_DONE_GRP203</td><td> SNP dispatched and went from Sx or Tx to Ix </td><td> 2</td><td>	Group 203 pm_l2_misc4</td>

</tr>

<tr><td>PM_L2_SN_M_WR_DONE_GRP203</td><td> SNP dispatched for a write and was M </td><td> 3</td><td>	Group 203 pm_l2_misc4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP203</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 203 pm_l2_misc4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP203</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 203 pm_l2_misc4</td>

</tr>

<tr><td>PM_INST_CMPL_GRP204</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 204 pm_l2_misc5</td>

</tr>

<tr><td>PM_CYC_GRP204</td><td> Processor Cycles </td><td> 1</td><td>	Group 204 pm_l2_misc5</td>

</tr>

<tr><td>PM_L2_NODE_PUMP_GRP204</td><td> RC req that was a local (aka node) pump attempt </td><td> 2</td><td>	Group 204 pm_l2_misc5</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP204</td><td> Number of run instructions completed. </td><td> 3</td><td>	Group 204 pm_l2_misc5</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP204</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 204 pm_l2_misc5</td>

</tr>

<tr><td>PM_RUN_CYC_GRP204</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 204 pm_l2_misc5</td>

</tr>

<tr><td>PM_INST_CMPL_GRP205</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 205 pm_l2_misc6</td>

</tr>

<tr><td>PM_RUN_CYC_GRP205</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 1</td><td>	Group 205 pm_l2_misc6</td>

</tr>

<tr><td>PM_CYC_GRP205</td><td> Processor Cycles </td><td> 2</td><td>	Group 205 pm_l2_misc6</td>

</tr>

<tr><td>PM_L2_SN_M_RD_DONE_GRP205</td><td> SNP dispatched for a read and was M </td><td> 3</td><td>	Group 205 pm_l2_misc6</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP205</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 205 pm_l2_misc6</td>

</tr>

<tr><td>PM_RUN_CYC_GRP205</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 205 pm_l2_misc6</td>

</tr>

<tr><td>PM_IERAT_MISS_GRP206</td><td> A translation request missed the Instruction Effective to Real Address Translation (ERAT) table </td><td> 0</td><td>	Group 206 pm_ierat</td>

</tr>

<tr><td>PM_IERAT_XLATE_WR_16MPLUS_GRP206</td><td> large page 16M+ </td><td> 1</td><td>	Group 206 pm_ierat</td>

</tr>

<tr><td>PM_IERAT_WR_64K_GRP206</td><td> large page 64k </td><td> 2</td><td>	Group 206 pm_ierat</td>

</tr>

<tr><td>PM_INST_CMPL_GRP206</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 206 pm_ierat</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP206</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 206 pm_ierat</td>

</tr>

<tr><td>PM_RUN_CYC_GRP206</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 206 pm_ierat</td>

</tr>

<tr><td>PM_DISP_CLB_HELD_GRP207</td><td> CLB Hold: Any Reason </td><td> 0</td><td>	Group 207 pm_disp_clb</td>

</tr>

<tr><td>PM_DISP_CLB_HELD_SB_GRP207</td><td> Dispatch/CLB Hold: Scoreboard </td><td> 1</td><td>	Group 207 pm_disp_clb</td>

</tr>

<tr><td>PM_CYC_GRP207</td><td> Processor Cycles </td><td> 2</td><td>	Group 207 pm_disp_clb</td>

</tr>

<tr><td>PM_INST_CMPL_GRP207</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 207 pm_disp_clb</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP207</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 207 pm_disp_clb</td>

</tr>

<tr><td>PM_RUN_CYC_GRP207</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 207 pm_disp_clb</td>

</tr>

<tr><td>PM_CYC_GRP208</td><td> Processor Cycles </td><td> 0</td><td>	Group 208 pm_dpu</td>

</tr>

<tr><td>PM_DPU_HELD_POWER_GRP208</td><td> Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time </td><td> 1</td><td>	Group 208 pm_dpu</td>

</tr>

<tr><td>PM_DISP_WT_GRP208</td><td> Dispatched Starved (not held, nothing to dispatch) </td><td> 2</td><td>	Group 208 pm_dpu</td>

</tr>

<tr><td>PM_INST_CMPL_GRP208</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 208 pm_dpu</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP208</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 208 pm_dpu</td>

</tr>

<tr><td>PM_RUN_CYC_GRP208</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 208 pm_dpu</td>

</tr>

<tr><td>PM_RUN_SPURR_GRP209</td><td> Run SPURR </td><td> 0</td><td>	Group 209 pm_cpu_util</td>

</tr>

<tr><td>PM_RUN_CYC_GRP209</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 1</td><td>	Group 209 pm_cpu_util</td>

</tr>

<tr><td>PM_CYC_GRP209</td><td> Processor Cycles </td><td> 2</td><td>	Group 209 pm_cpu_util</td>

</tr>

<tr><td>PM_RUN_PURR_GRP209</td><td> The Processor Utilization of Resources Register was incremented while the run latch was set. The PURR registers will be incremented roughly in the ratio in which the instructions are dispatched from the two threads. </td><td> 3</td><td>	Group 209 pm_cpu_util</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP209</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 209 pm_cpu_util</td>

</tr>

<tr><td>PM_RUN_CYC_GRP209</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 209 pm_cpu_util</td>

</tr>

<tr><td>PM_PMC4_OVERFLOW_GRP210</td><td> Overflows from PMC4 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. </td><td> 0</td><td>	Group 210 pm_overflow1</td>

</tr>

<tr><td>PM_PMC1_OVERFLOW_GRP210</td><td> Overflows from PMC1 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. </td><td> 1</td><td>	Group 210 pm_overflow1</td>

</tr>

<tr><td>PM_PMC2_OVERFLOW_GRP210</td><td> Overflows from PMC2 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. </td><td> 2</td><td>	Group 210 pm_overflow1</td>

</tr>

<tr><td>PM_PMC3_OVERFLOW_GRP210</td><td> Overflows from PMC3 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. </td><td> 3</td><td>	Group 210 pm_overflow1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP210</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 210 pm_overflow1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP210</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 210 pm_overflow1</td>

</tr>

<tr><td>PM_PMC5_OVERFLOW_GRP211</td><td> Overflows from PMC5 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. </td><td> 0</td><td>	Group 211 pm_overflow2</td>

</tr>

<tr><td>PM_PMC1_OVERFLOW_GRP211</td><td> Overflows from PMC1 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. </td><td> 1</td><td>	Group 211 pm_overflow2</td>

</tr>

<tr><td>PM_PMC6_OVERFLOW_GRP211</td><td> Overflows from PMC6 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. </td><td> 2</td><td>	Group 211 pm_overflow2</td>

</tr>

<tr><td>PM_PMC3_OVERFLOW_GRP211</td><td> Overflows from PMC3 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. </td><td> 3</td><td>	Group 211 pm_overflow2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP211</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 211 pm_overflow2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP211</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 211 pm_overflow2</td>

</tr>

<tr><td>PM_PMC4_REWIND_GRP212</td><td> PMC4 was counting speculatively. The speculative condition was not met and the counter was restored to its previous value. </td><td> 0</td><td>	Group 212 pm_rewind</td>

</tr>

<tr><td>PM_RUN_CYC_GRP212</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 1</td><td>	Group 212 pm_rewind</td>

</tr>

<tr><td>PM_PMC2_REWIND_GRP212</td><td> PMC2 was counting speculatively. The speculative condition was not met and the counter was restored to its previous value. </td><td> 2</td><td>	Group 212 pm_rewind</td>

</tr>

<tr><td>PM_INST_CMPL_GRP212</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 212 pm_rewind</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP212</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 212 pm_rewind</td>

</tr>

<tr><td>PM_RUN_CYC_GRP212</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 212 pm_rewind</td>

</tr>

<tr><td>PM_PMC2_SAVED_GRP213</td><td> PMC2 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register. </td><td> 0</td><td>	Group 213 pm_saved</td>

</tr>

<tr><td>PM_RUN_CYC_GRP213</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 1</td><td>	Group 213 pm_saved</td>

</tr>

<tr><td>PM_PMC4_SAVED_GRP213</td><td> PMC4 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register. </td><td> 2</td><td>	Group 213 pm_saved</td>

</tr>

<tr><td>PM_INST_CMPL_GRP213</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 213 pm_saved</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP213</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 213 pm_saved</td>

</tr>

<tr><td>PM_RUN_CYC_GRP213</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 213 pm_saved</td>

</tr>

<tr><td>PM_FLUSH_DISP_TLBIE_GRP214</td><td> Dispatch Flush: TLBIE </td><td> 0</td><td>	Group 214 pm_tlbie</td>

</tr>

<tr><td>PM_DISP_CLB_HELD_TLBIE_GRP214</td><td> Dispatch Hold: Due to TLBIE </td><td> 1</td><td>	Group 214 pm_tlbie</td>

</tr>

<tr><td>PM_SNOOP_TLBIE_GRP214</td><td> A tlbie was snooped from another processor. </td><td> 2</td><td>	Group 214 pm_tlbie</td>

</tr>

<tr><td>PM_INST_CMPL_GRP214</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 214 pm_tlbie</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP214</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 214 pm_tlbie</td>

</tr>

<tr><td>PM_RUN_CYC_GRP214</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 214 pm_tlbie</td>

</tr>

<tr><td>PM_IERAT_MISS_GRP215</td><td> A translation request missed the Instruction Effective to Real Address Translation (ERAT) table </td><td> 0</td><td>	Group 215 pm_id_miss_erat_l1</td>

</tr>

<tr><td>PM_L1_ICACHE_MISS_GRP215</td><td> An instruction fetch request missed the L1 cache. </td><td> 1</td><td>	Group 215 pm_id_miss_erat_l1</td>

</tr>

<tr><td>PM_ST_MISS_L1_GRP215</td><td> A store missed the dcache. Combined Unit 0 + 1. </td><td> 2</td><td>	Group 215 pm_id_miss_erat_l1</td>

</tr>

<tr><td>PM_LD_MISS_L1_GRP215</td><td> Load references that miss the Level 1 Data cache. Combined unit 0 + 1. </td><td> 3</td><td>	Group 215 pm_id_miss_erat_l1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP215</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 215 pm_id_miss_erat_l1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP215</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 215 pm_id_miss_erat_l1</td>

</tr>

<tr><td>PM_CYC_GRP216</td><td> Processor Cycles </td><td> 0</td><td>	Group 216 pm_id_miss_erat_tlab</td>

</tr>

<tr><td>PM_LSU_DERAT_MISS_GRP216</td><td> Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1. </td><td> 1</td><td>	Group 216 pm_id_miss_erat_tlab</td>

</tr>

<tr><td>PM_DTLB_MISS_GRP216</td><td> Data TLB misses, all page sizes. </td><td> 2</td><td>	Group 216 pm_id_miss_erat_tlab</td>

</tr>

<tr><td>PM_ITLB_MISS_GRP216</td><td> A TLB miss for an Instruction Fetch has occurred </td><td> 3</td><td>	Group 216 pm_id_miss_erat_tlab</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP216</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 216 pm_id_miss_erat_tlab</td>

</tr>

<tr><td>PM_RUN_CYC_GRP216</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 216 pm_id_miss_erat_tlab</td>

</tr>

<tr><td>PM_ANY_THRD_RUN_CYC_GRP217</td><td> One of threads in run_cycles </td><td> 0</td><td>	Group 217 pm_compat_utilization1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP217</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 1</td><td>	Group 217 pm_compat_utilization1</td>

</tr>

<tr><td>PM_CYC_GRP217</td><td> Processor Cycles </td><td> 2</td><td>	Group 217 pm_compat_utilization1</td>

</tr>

<tr><td>PM_RUN_PURR_GRP217</td><td> The Processor Utilization of Resources Register was incremented while the run latch was set. The PURR registers will be incremented roughly in the ratio in which the instructions are dispatched from the two threads. </td><td> 3</td><td>	Group 217 pm_compat_utilization1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP217</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 217 pm_compat_utilization1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP217</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 217 pm_compat_utilization1</td>

</tr>

<tr><td>PM_FLOP_GRP218</td><td> A floating point operation has completed </td><td> 0</td><td>	Group 218 pm_compat_utilization2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP218</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 1</td><td>	Group 218 pm_compat_utilization2</td>

</tr>

<tr><td>PM_CYC_GRP218</td><td> Processor Cycles </td><td> 2</td><td>	Group 218 pm_compat_utilization2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP218</td><td> Number of run instructions completed. </td><td> 3</td><td>	Group 218 pm_compat_utilization2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP218</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 218 pm_compat_utilization2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP218</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 218 pm_compat_utilization2</td>

</tr>

<tr><td>PM_1PLUS_PPC_CMPL_GRP219</td><td> A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once. </td><td> 0</td><td>	Group 219 pm_compat_cpi_1plus_ppc</td>

</tr>

<tr><td>PM_RUN_CYC_GRP219</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 1</td><td>	Group 219 pm_compat_cpi_1plus_ppc</td>

</tr>

<tr><td>PM_INST_DISP_GRP219</td><td> Number of PowerPC instructions successfully dispatched. </td><td> 2</td><td>	Group 219 pm_compat_cpi_1plus_ppc</td>

</tr>

<tr><td>PM_1PLUS_PPC_DISP_GRP219</td><td> A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once. </td><td> 3</td><td>	Group 219 pm_compat_cpi_1plus_ppc</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP219</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 219 pm_compat_cpi_1plus_ppc</td>

</tr>

<tr><td>PM_RUN_CYC_GRP219</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 219 pm_compat_cpi_1plus_ppc</td>

</tr>

<tr><td>PM_INST_CMPL_GRP220</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 220 pm_compat_l1_dcache_load_store_miss</td>

</tr>

<tr><td>PM_ST_FIN_GRP220</td><td> Store requests sent to the nest. </td><td> 1</td><td>	Group 220 pm_compat_l1_dcache_load_store_miss</td>

</tr>

<tr><td>PM_ST_MISS_L1_GRP220</td><td> A store missed the dcache. Combined Unit 0 + 1. </td><td> 2</td><td>	Group 220 pm_compat_l1_dcache_load_store_miss</td>

</tr>

<tr><td>PM_LD_MISS_L1_GRP220</td><td> Load references that miss the Level 1 Data cache. Combined unit 0 + 1. </td><td> 3</td><td>	Group 220 pm_compat_l1_dcache_load_store_miss</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP220</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 220 pm_compat_l1_dcache_load_store_miss</td>

</tr>

<tr><td>PM_RUN_CYC_GRP220</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 220 pm_compat_l1_dcache_load_store_miss</td>

</tr>

<tr><td>PM_INST_CMPL_GRP221</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 221 pm_compat_l1_cache_load</td>

</tr>

<tr><td>PM_DATA_FROM_L2MISS_GRP221</td><td> The processor's Data Cache was reloaded but not from the local L2. </td><td> 1</td><td>	Group 221 pm_compat_l1_cache_load</td>

</tr>

<tr><td>PM_L1_DCACHE_RELOAD_VALID_GRP221</td><td> The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads. </td><td> 2</td><td>	Group 221 pm_compat_l1_cache_load</td>

</tr>

<tr><td>PM_LD_MISS_L1_GRP221</td><td> Load references that miss the Level 1 Data cache. Combined unit 0 + 1. </td><td> 3</td><td>	Group 221 pm_compat_l1_cache_load</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP221</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 221 pm_compat_l1_cache_load</td>

</tr>

<tr><td>PM_RUN_CYC_GRP221</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 221 pm_compat_l1_cache_load</td>

</tr>

<tr><td>PM_IERAT_MISS_GRP222</td><td> A translation request missed the Instruction Effective to Real Address Translation (ERAT) table </td><td> 0</td><td>	Group 222 pm_compat_instruction_directory</td>

</tr>

<tr><td>PM_L1_ICACHE_MISS_GRP222</td><td> An instruction fetch request missed the L1 cache. </td><td> 1</td><td>	Group 222 pm_compat_instruction_directory</td>

</tr>

<tr><td>PM_INST_CMPL_GRP222</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 222 pm_compat_instruction_directory</td>

</tr>

<tr><td>PM_ITLB_MISS_GRP222</td><td> A TLB miss for an Instruction Fetch has occurred </td><td> 3</td><td>	Group 222 pm_compat_instruction_directory</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP222</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 222 pm_compat_instruction_directory</td>

</tr>

<tr><td>PM_RUN_CYC_GRP222</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 222 pm_compat_instruction_directory</td>

</tr>

<tr><td>PM_SUSPENDED_GRP223</td><td> The counter is suspended (does not count) </td><td> 0</td><td>	Group 223 pm_compat_suspend</td>

</tr>

<tr><td>PM_SUSPENDED_GRP223</td><td> The counter is suspended (does not count) </td><td> 1</td><td>	Group 223 pm_compat_suspend</td>

</tr>

<tr><td>PM_SUSPENDED_GRP223</td><td> The counter is suspended (does not count) </td><td> 2</td><td>	Group 223 pm_compat_suspend</td>

</tr>

<tr><td>PM_SUSPENDED_GRP223</td><td> The counter is suspended (does not count) </td><td> 3</td><td>	Group 223 pm_compat_suspend</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP223</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 223 pm_compat_suspend</td>

</tr>

<tr><td>PM_RUN_CYC_GRP223</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 223 pm_compat_suspend</td>

</tr>

<tr><td>PM_INST_CMPL_GRP224</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 224 pm_compat_misc_events1</td>

</tr>

<tr><td>PM_EXT_INT_GRP224</td><td> An interrupt due to an external exception occurred </td><td> 1</td><td>	Group 224 pm_compat_misc_events1</td>

</tr>

<tr><td>PM_TB_BIT_TRANS_GRP224</td><td> When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 </td><td> 2</td><td>	Group 224 pm_compat_misc_events1</td>

</tr>

<tr><td>PM_CYC_GRP224</td><td> Processor Cycles </td><td> 3</td><td>	Group 224 pm_compat_misc_events1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP224</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 224 pm_compat_misc_events1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP224</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 224 pm_compat_misc_events1</td>

</tr>

<tr><td>PM_INST_IMC_MATCH_CMPL_GRP225</td><td> Number of instructions resulting from the marked instructions expansion that completed. </td><td> 0</td><td>	Group 225 pm_compat_misc_events2</td>

</tr>

<tr><td>PM_INST_DISP_GRP225</td><td> Number of PowerPC instructions successfully dispatched. </td><td> 1</td><td>	Group 225 pm_compat_misc_events2</td>

</tr>

<tr><td>PM_THRD_CONC_RUN_INST_GRP225</td><td> Instructions completed by this thread when both threads had their run latches set. </td><td> 2</td><td>	Group 225 pm_compat_misc_events2</td>

</tr>

<tr><td>PM_FLUSH_GRP225</td><td> Flushes occurred including LSU and Branch flushes. </td><td> 3</td><td>	Group 225 pm_compat_misc_events2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP225</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 225 pm_compat_misc_events2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP225</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 225 pm_compat_misc_events2</td>

</tr>

<tr><td>PM_GCT_NOSLOT_CYC_GRP226</td><td> Cycles when the Global Completion Table has no slots from this thread. </td><td> 0</td><td>	Group 226 pm_compat_misc_events3</td>

</tr>

<tr><td>PM_INST_DISP_GRP226</td><td> Number of PowerPC instructions successfully dispatched. </td><td> 1</td><td>	Group 226 pm_compat_misc_events3</td>

</tr>

<tr><td>PM_CYC_GRP226</td><td> Processor Cycles </td><td> 2</td><td>	Group 226 pm_compat_misc_events3</td>

</tr>

<tr><td>PM_BR_MPRED_GRP226</td><td> A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both </td><td> 3</td><td>	Group 226 pm_compat_misc_events3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP226</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 226 pm_compat_misc_events3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP226</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 226 pm_compat_misc_events3</td>

</tr>

<tr><td>PM_MRK_BR_TAKEN_GRP227</td><td> A marked branch was taken </td><td> 0</td><td>	Group 227 pm_mrk_br</td>

</tr>

<tr><td>PM_MRK_LD_MISS_L1_GRP227</td><td> Marked L1 D cache load misses </td><td> 1</td><td>	Group 227 pm_mrk_br</td>

</tr>

<tr><td>PM_MRK_BR_MPRED_GRP227</td><td> A marked branch was mispredicted </td><td> 2</td><td>	Group 227 pm_mrk_br</td>

</tr>

<tr><td>PM_INST_CMPL_GRP227</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 227 pm_mrk_br</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP227</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 227 pm_mrk_br</td>

</tr>

<tr><td>PM_RUN_CYC_GRP227</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 227 pm_mrk_br</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_DMEM_GRP228</td><td> The processor's Data Cache was reloaded with data from memory attached to a distant module due to a marked load. </td><td> 0</td><td>	Group 228 pm_mrk_dsource1</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_DMEM_CYC_GRP228</td><td> Marked ld latency Data Source 1110 (Distant Memory) </td><td> 1</td><td>	Group 228 pm_mrk_dsource1</td>

</tr>

<tr><td>PM_INST_CMPL_GRP228</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 228 pm_mrk_dsource1</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L2MISS_GRP228</td><td> DL1 was reloaded from beyond L2 due to a marked demand load. </td><td> 3</td><td>	Group 228 pm_mrk_dsource1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP228</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 228 pm_mrk_dsource1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP228</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 228 pm_mrk_dsource1</td>

</tr>

<tr><td>PM_MRK_LD_MISS_EXPOSED_CYC_GRP229</td><td> Marked Load exposed Miss </td><td> 0</td><td>	Group 229 pm_mrk_dsource2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP229</td><td> Number of PowerPC Instructions that completed. </td><td> 1</td><td>	Group 229 pm_mrk_dsource2</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L21_MOD_GRP229</td><td> Marked data loaded from another L2 on same chip modified </td><td> 2</td><td>	Group 229 pm_mrk_dsource2</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L21_MOD_CYC_GRP229</td><td> Marked ld latency Data source 0101 (L2.1 M same chip) </td><td> 3</td><td>	Group 229 pm_mrk_dsource2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP229</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 229 pm_mrk_dsource2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP229</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 229 pm_mrk_dsource2</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L3_GRP230</td><td> The processor's Data Cache was reloaded from the local L3 due to a marked load. </td><td> 0</td><td>	Group 230 pm_mrk_dsource3</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L3MISS_GRP230</td><td> DL1 was reloaded from beyond L3 due to a marked load. </td><td> 1</td><td>	Group 230 pm_mrk_dsource3</td>

</tr>

<tr><td>PM_INST_CMPL_GRP230</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 230 pm_mrk_dsource3</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L3_CYC_GRP230</td><td> Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level. </td><td> 3</td><td>	Group 230 pm_mrk_dsource3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP230</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 230 pm_mrk_dsource3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP230</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 230 pm_mrk_dsource3</td>

</tr>

<tr><td>PM_INST_CMPL_GRP231</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 231 pm_mrk_dsource4</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_LMEM_CYC_GRP231</td><td> Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level. </td><td> 1</td><td>	Group 231 pm_mrk_dsource4</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_LMEM_GRP231</td><td> The processor's Data Cache was reloaded due to a marked load from memory attached to the same module this processor is located on. </td><td> 2</td><td>	Group 231 pm_mrk_dsource4</td>

</tr>

<tr><td>PM_DATA_FROM_LMEM_GRP231</td><td> The processor's Data Cache was reloaded from memory attached to the same module this processor is located on. </td><td> 3</td><td>	Group 231 pm_mrk_dsource4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP231</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 231 pm_mrk_dsource4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP231</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 231 pm_mrk_dsource4</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L31_MOD_GRP232</td><td> Marked data loaded from another L3 on same chip modified </td><td> 0</td><td>	Group 232 pm_mrk_dsource5</td>

</tr>

<tr><td>PM_INST_CMPL_GRP232</td><td> Number of PowerPC Instructions that completed. </td><td> 1</td><td>	Group 232 pm_mrk_dsource5</td>

</tr>

<tr><td>PM_MRK_INST_FIN_GRP232</td><td> One of the execution units finished a marked instruction. Instructions that finish may not necessary complete </td><td> 2</td><td>	Group 232 pm_mrk_dsource5</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L31_MOD_CYC_GRP232</td><td> Marked ld latency Data source 0111 (L3.1 M same chip) </td><td> 3</td><td>	Group 232 pm_mrk_dsource5</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP232</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 232 pm_mrk_dsource5</td>

</tr>

<tr><td>PM_RUN_CYC_GRP232</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 232 pm_mrk_dsource5</td>

</tr>

<tr><td>PM_MRK_LD_MISS_EXPOSED_CYC_COUNT_GRP233</td><td> Marked Load exposed Miss (use edge detect to count #) </td><td> 0</td><td>	Group 233 pm_mrk_dsource6</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L21_SHR_CYC_GRP233</td><td> Marked load latency Data source 0100 (L2.1 S) </td><td> 1</td><td>	Group 233 pm_mrk_dsource6</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L21_SHR_GRP233</td><td> Marked data loaded from another L2 on same chip shared </td><td> 2</td><td>	Group 233 pm_mrk_dsource6</td>

</tr>

<tr><td>PM_INST_CMPL_GRP233</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 233 pm_mrk_dsource6</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP233</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 233 pm_mrk_dsource6</td>

</tr>

<tr><td>PM_RUN_CYC_GRP233</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 233 pm_mrk_dsource6</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L2_GRP234</td><td> The processor's Data Cache was reloaded from the local L2 due to a marked load. </td><td> 0</td><td>	Group 234 pm_mrk_dsource7</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L2_CYC_GRP234</td><td> Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level. </td><td> 1</td><td>	Group 234 pm_mrk_dsource7</td>

</tr>

<tr><td>PM_INST_CMPL_GRP234</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 234 pm_mrk_dsource7</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L2MISS_GRP234</td><td> DL1 was reloaded from beyond L2 due to a marked demand load. </td><td> 3</td><td>	Group 234 pm_mrk_dsource7</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP234</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 234 pm_mrk_dsource7</td>

</tr>

<tr><td>PM_RUN_CYC_GRP234</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 234 pm_mrk_dsource7</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_RL2L3_MOD_GRP235</td><td> The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a marked load. </td><td> 0</td><td>	Group 235 pm_mrk_dsource8</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L3MISS_GRP235</td><td> DL1 was reloaded from beyond L3 due to a marked load. </td><td> 1</td><td>	Group 235 pm_mrk_dsource8</td>

</tr>

<tr><td>PM_INST_CMPL_GRP235</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 235 pm_mrk_dsource8</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_RL2L3_MOD_CYC_GRP235</td><td> Marked ld latency Data source 1001 (L2.5/L3.5 M same 4 chip node) </td><td> 3</td><td>	Group 235 pm_mrk_dsource8</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP235</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 235 pm_mrk_dsource8</td>

</tr>

<tr><td>PM_RUN_CYC_GRP235</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 235 pm_mrk_dsource8</td>

</tr>

<tr><td>PM_INST_CMPL_GRP236</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 236 pm_mrk_dsource9</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_DL2L3_SHR_CYC_GRP236</td><td> Marked ld latency Data Source 1010 (Distant L2.75/L3.75 S) </td><td> 1</td><td>	Group 236 pm_mrk_dsource9</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_DL2L3_SHR_GRP236</td><td> The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a marked load. </td><td> 2</td><td>	Group 236 pm_mrk_dsource9</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L2MISS_GRP236</td><td> DL1 was reloaded from beyond L2 due to a marked demand load. </td><td> 3</td><td>	Group 236 pm_mrk_dsource9</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP236</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 236 pm_mrk_dsource9</td>

</tr>

<tr><td>PM_RUN_CYC_GRP236</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 236 pm_mrk_dsource9</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_RL2L3_SHR_GRP237</td><td> The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load </td><td> 0</td><td>	Group 237 pm_mrk_dsource10</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_RL2L3_SHR_CYC_GRP237</td><td> Marked load latency Data Source 1000 (Remote L2.5/L3.5 S) </td><td> 1</td><td>	Group 237 pm_mrk_dsource10</td>

</tr>

<tr><td>PM_DATA_FROM_RMEM_GRP237</td><td> The processor's Data Cache was reloaded from memory attached to a different module than this processor is located on. </td><td> 2</td><td>	Group 237 pm_mrk_dsource10</td>

</tr>

<tr><td>PM_INST_CMPL_GRP237</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 237 pm_mrk_dsource10</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP237</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 237 pm_mrk_dsource10</td>

</tr>

<tr><td>PM_RUN_CYC_GRP237</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 237 pm_mrk_dsource10</td>

</tr>

<tr><td>PM_MRK_LD_MISS_EXPOSED_CYC_GRP238</td><td> Marked Load exposed Miss </td><td> 0</td><td>	Group 238 pm_mrk_dsource11</td>

</tr>

<tr><td>PM_INST_CMPL_GRP238</td><td> Number of PowerPC Instructions that completed. </td><td> 1</td><td>	Group 238 pm_mrk_dsource11</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_RMEM_GRP238</td><td> The processor's Data Cache was reloaded due to a marked load from memory attached to a different module than this processor is located on. </td><td> 2</td><td>	Group 238 pm_mrk_dsource11</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_RMEM_CYC_GRP238</td><td> Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level. </td><td> 3</td><td>	Group 238 pm_mrk_dsource11</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP238</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 238 pm_mrk_dsource11</td>

</tr>

<tr><td>PM_RUN_CYC_GRP238</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 238 pm_mrk_dsource11</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L31_SHR_GRP239</td><td> Marked data loaded from another L3 on same chip shared </td><td> 0</td><td>	Group 239 pm_mrk_dsource12</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L31_SHR_CYC_GRP239</td><td> Marked load latency Data source 0110 (L3.1 S) </td><td> 1</td><td>	Group 239 pm_mrk_dsource12</td>

</tr>

<tr><td>PM_MRK_INST_FIN_GRP239</td><td> One of the execution units finished a marked instruction. Instructions that finish may not necessary complete </td><td> 2</td><td>	Group 239 pm_mrk_dsource12</td>

</tr>

<tr><td>PM_INST_CMPL_GRP239</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 239 pm_mrk_dsource12</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP239</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 239 pm_mrk_dsource12</td>

</tr>

<tr><td>PM_RUN_CYC_GRP239</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 239 pm_mrk_dsource12</td>

</tr>

<tr><td>PM_MRK_LD_MISS_EXPOSED_CYC_COUNT_GRP240</td><td> Marked Load exposed Miss (use edge detect to count #) </td><td> 0</td><td>	Group 240 pm_mrk_dsource13</td>

</tr>

<tr><td>PM_INST_CMPL_GRP240</td><td> Number of PowerPC Instructions that completed. </td><td> 1</td><td>	Group 240 pm_mrk_dsource13</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_DL2L3_MOD_GRP240</td><td> The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a marked load. </td><td> 2</td><td>	Group 240 pm_mrk_dsource13</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_DL2L3_MOD_CYC_GRP240</td><td> Marked ld latency Data source 1011 (L2.75/L3.75 M different 4 chip node) </td><td> 3</td><td>	Group 240 pm_mrk_dsource13</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP240</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 240 pm_mrk_dsource13</td>

</tr>

<tr><td>PM_RUN_CYC_GRP240</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 240 pm_mrk_dsource13</td>

</tr>

<tr><td>PM_MRK_LSU_FLUSH_ULD_GRP241</td><td> A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1) </td><td> 0</td><td>	Group 241 pm_mrk_lsu_flush1</td>

</tr>

<tr><td>PM_MRK_LSU_FLUSH_UST_GRP241</td><td> A marked store was flushed because it was unaligned </td><td> 1</td><td>	Group 241 pm_mrk_lsu_flush1</td>

</tr>

<tr><td>PM_INST_CMPL_GRP241</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 241 pm_mrk_lsu_flush1</td>

</tr>

<tr><td>PM_CYC_GRP241</td><td> Processor Cycles </td><td> 3</td><td>	Group 241 pm_mrk_lsu_flush1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP241</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 241 pm_mrk_lsu_flush1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP241</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 241 pm_mrk_lsu_flush1</td>

</tr>

<tr><td>PM_INST_CMPL_GRP242</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 242 pm_mrk_lsu_flush2</td>

</tr>

<tr><td>PM_CYC_GRP242</td><td> Processor Cycles </td><td> 1</td><td>	Group 242 pm_mrk_lsu_flush2</td>

</tr>

<tr><td>PM_MRK_LSU_FLUSH_LRQ_GRP242</td><td> Load Hit Load or Store Hit Load flush. A marked load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. </td><td> 2</td><td>	Group 242 pm_mrk_lsu_flush2</td>

</tr>

<tr><td>PM_MRK_LSU_FLUSH_SRQ_GRP242</td><td> Load Hit Store flush. A marked load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. </td><td> 3</td><td>	Group 242 pm_mrk_lsu_flush2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP242</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 242 pm_mrk_lsu_flush2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP242</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 242 pm_mrk_lsu_flush2</td>

</tr>

<tr><td>PM_MRK_LSU_REJECT_LHS_GRP243</td><td> The Load Store Unit rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully </td><td> 0</td><td>	Group 243 pm_mrk_rejects</td>

</tr>

<tr><td>PM_MRK_LSU_FLUSH_GRP243</td><td> Marked flush initiated by LSU </td><td> 1</td><td>	Group 243 pm_mrk_rejects</td>

</tr>

<tr><td>PM_INST_CMPL_GRP243</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 243 pm_mrk_rejects</td>

</tr>

<tr><td>PM_MRK_LSU_REJECT_GRP243</td><td> LSU marked reject (up to 2 per cycle) </td><td> 3</td><td>	Group 243 pm_mrk_rejects</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP243</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 243 pm_mrk_rejects</td>

</tr>

<tr><td>PM_RUN_CYC_GRP243</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 243 pm_mrk_rejects</td>

</tr>

<tr><td>PM_MRK_INST_ISSUED_GRP244</td><td> A marked instruction was issued to an execution unit. </td><td> 0</td><td>	Group 244 pm_mrk_inst</td>

</tr>

<tr><td>PM_MRK_INST_DISP_GRP244</td><td> A marked instruction was dispatched </td><td> 1</td><td>	Group 244 pm_mrk_inst</td>

</tr>

<tr><td>PM_MRK_INST_FIN_GRP244</td><td> One of the execution units finished a marked instruction. Instructions that finish may not necessary complete </td><td> 2</td><td>	Group 244 pm_mrk_inst</td>

</tr>

<tr><td>PM_INST_CMPL_GRP244</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 244 pm_mrk_inst</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP244</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 244 pm_mrk_inst</td>

</tr>

<tr><td>PM_RUN_CYC_GRP244</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 244 pm_mrk_inst</td>

</tr>

<tr><td>PM_MRK_ST_CMPL_GRP245</td><td> A sampled store has completed (data home) </td><td> 0</td><td>	Group 245 pm_mrk_st</td>

</tr>

<tr><td>PM_MRK_ST_NEST_GRP245</td><td> A sampled store has been sent to the memory subsystem </td><td> 1</td><td>	Group 245 pm_mrk_st</td>

</tr>

<tr><td>PM_MRK_ST_CMPL_INT_GRP245</td><td> A marked store previously sent to the memory subsystem completed (data home) after requiring intervention </td><td> 2</td><td>	Group 245 pm_mrk_st</td>

</tr>

<tr><td>PM_INST_CMPL_GRP245</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 245 pm_mrk_st</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP245</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 245 pm_mrk_st</td>

</tr>

<tr><td>PM_RUN_CYC_GRP245</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 245 pm_mrk_st</td>

</tr>

<tr><td>PM_INST_CMPL_GRP246</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 246 pm_mrk_dtlb_miss1</td>

</tr>

<tr><td>PM_MRK_DTLB_MISS_4K_GRP246</td><td> Data TLB references to 4KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time. </td><td> 1</td><td>	Group 246 pm_mrk_dtlb_miss1</td>

</tr>

<tr><td>PM_MRK_DTLB_MISS_64K_GRP246</td><td> Data TLB references to 64KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time. </td><td> 2</td><td>	Group 246 pm_mrk_dtlb_miss1</td>

</tr>

<tr><td>PM_MRK_DTLB_MISS_16M_GRP246</td><td> Data TLB references to 16M pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time. </td><td> 3</td><td>	Group 246 pm_mrk_dtlb_miss1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP246</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 246 pm_mrk_dtlb_miss1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP246</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 246 pm_mrk_dtlb_miss1</td>

</tr>

<tr><td>PM_MRK_DTLB_MISS_16G_GRP247</td><td> Data TLB references to 16GB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time. </td><td> 0</td><td>	Group 247 pm_mrk_dtlb_miss2</td>

</tr>

<tr><td>PM_MRK_DTLB_MISS_4K_GRP247</td><td> Data TLB references to 4KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time. </td><td> 1</td><td>	Group 247 pm_mrk_dtlb_miss2</td>

</tr>

<tr><td>PM_MRK_DTLB_MISS_64K_GRP247</td><td> Data TLB references to 64KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time. </td><td> 2</td><td>	Group 247 pm_mrk_dtlb_miss2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP247</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 247 pm_mrk_dtlb_miss2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP247</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 247 pm_mrk_dtlb_miss2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP247</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 247 pm_mrk_dtlb_miss2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP248</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 248 pm_mrk_derat_miss1</td>

</tr>

<tr><td>PM_MRK_DERAT_MISS_64K_GRP248</td><td> A marked data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload. </td><td> 1</td><td>	Group 248 pm_mrk_derat_miss1</td>

</tr>

<tr><td>PM_MRK_DERAT_MISS_16M_GRP248</td><td> A marked data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload. </td><td> 2</td><td>	Group 248 pm_mrk_derat_miss1</td>

</tr>

<tr><td>PM_MRK_DERAT_MISS_16G_GRP248</td><td> A marked data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload. </td><td> 3</td><td>	Group 248 pm_mrk_derat_miss1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP248</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 248 pm_mrk_derat_miss1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP248</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 248 pm_mrk_derat_miss1</td>

</tr>

<tr><td>PM_MRK_DERAT_MISS_4K_GRP249</td><td> A marked data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload. </td><td> 0</td><td>	Group 249 pm_mrk_derat_miss2</td>

</tr>

<tr><td>PM_MRK_DERAT_MISS_64K_GRP249</td><td> A marked data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload. </td><td> 1</td><td>	Group 249 pm_mrk_derat_miss2</td>

</tr>

<tr><td>PM_MRK_DERAT_MISS_16M_GRP249</td><td> A marked data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload. </td><td> 2</td><td>	Group 249 pm_mrk_derat_miss2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP249</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 249 pm_mrk_derat_miss2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP249</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 249 pm_mrk_derat_miss2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP249</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 249 pm_mrk_derat_miss2</td>

</tr>

<tr><td>PM_MRK_LD_MISS_EXPOSED_CYC_GRP250</td><td> Marked Load exposed Miss </td><td> 0</td><td>	Group 250 pm_mrk_misc_miss</td>

</tr>

<tr><td>PM_INST_CMPL_GRP250</td><td> Number of PowerPC Instructions that completed. </td><td> 1</td><td>	Group 250 pm_mrk_misc_miss</td>

</tr>

<tr><td>PM_MRK_LSU_DERAT_MISS_GRP250</td><td> Marked DERAT Miss </td><td> 2</td><td>	Group 250 pm_mrk_misc_miss</td>

</tr>

<tr><td>PM_MRK_LD_MISS_L1_CYC_GRP250</td><td> L1 data load miss cycles </td><td> 3</td><td>	Group 250 pm_mrk_misc_miss</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP250</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 250 pm_mrk_misc_miss</td>

</tr>

<tr><td>PM_RUN_CYC_GRP250</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 250 pm_mrk_misc_miss</td>

</tr>

<tr><td>PM_INST_CMPL_GRP251</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 251 pm_mrk_pteg1</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_DMEM_GRP251</td><td> A Page Table Entry was loaded into the ERAT from memory attached to a different module than this processor is located on due to a marked load or store. </td><td> 1</td><td>	Group 251 pm_mrk_pteg1</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_L21_MOD_GRP251</td><td> Marked PTEG loaded from another L2 on same chip modified </td><td> 2</td><td>	Group 251 pm_mrk_pteg1</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_L21_SHR_GRP251</td><td> Marked PTEG loaded from another L2 on same chip shared </td><td> 3</td><td>	Group 251 pm_mrk_pteg1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP251</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 251 pm_mrk_pteg1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP251</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 251 pm_mrk_pteg1</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_L2_GRP252</td><td> A Page Table Entry was loaded into the ERAT from the local L2 due to a marked load or store. </td><td> 0</td><td>	Group 252 pm_mrk_pteg2</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_RL2L3_SHR_GRP252</td><td> A Page Table Entry was loaded into the ERAT from memory attached to a different module than this processor is located on due to a marked load or store. </td><td> 1</td><td>	Group 252 pm_mrk_pteg2</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_RMEM_GRP252</td><td> A Page Table Entry was loaded into the ERAT. POWER6 does not have a TLB </td><td> 2</td><td>	Group 252 pm_mrk_pteg2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP252</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 252 pm_mrk_pteg2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP252</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 252 pm_mrk_pteg2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP252</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 252 pm_mrk_pteg2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP253</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 253 pm_mrk_pteg3</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_L31_SHR_GRP253</td><td> Marked PTEG loaded from another L3 on same chip shared </td><td> 1</td><td>	Group 253 pm_mrk_pteg3</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_L21_MOD_GRP253</td><td> Marked PTEG loaded from another L2 on same chip modified </td><td> 2</td><td>	Group 253 pm_mrk_pteg3</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_DL2L3_MOD_GRP253</td><td> A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a distant module due to a marked load or store. </td><td> 3</td><td>	Group 253 pm_mrk_pteg3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP253</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 253 pm_mrk_pteg3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP253</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 253 pm_mrk_pteg3</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_L31_MOD_GRP254</td><td> Marked PTEG loaded from another L3 on same chip modified </td><td> 0</td><td>	Group 254 pm_mrk_pteg4</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_L3_GRP254</td><td> A Page Table Entry was loaded into the ERAT from the local L3 due to a marked load or store. </td><td> 1</td><td>	Group 254 pm_mrk_pteg4</td>

</tr>

<tr><td>PM_INST_CMPL_GRP254</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 254 pm_mrk_pteg4</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_L2MISS_GRP254</td><td> A Page Table Entry was loaded into the ERAT but not from the local L2 due to a marked load or store. </td><td> 3</td><td>	Group 254 pm_mrk_pteg4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP254</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 254 pm_mrk_pteg4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP254</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 254 pm_mrk_pteg4</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_RL2L3_MOD_GRP255</td><td> A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load or store. </td><td> 0</td><td>	Group 255 pm_mrk_pteg5</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_L3MISS_GRP255</td><td> A Page Table Entry was loaded into the ERAT from beyond the L3 due to a marked load or store </td><td> 1</td><td>	Group 255 pm_mrk_pteg5</td>

</tr>

<tr><td>PM_INST_CMPL_GRP255</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 255 pm_mrk_pteg5</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_LMEM_GRP255</td><td> A Page Table Entry was loaded into the ERAT from memory attached to the same module this processor is located on due to a marked load or store. </td><td> 3</td><td>	Group 255 pm_mrk_pteg5</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP255</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 255 pm_mrk_pteg5</td>

</tr>

<tr><td>PM_RUN_CYC_GRP255</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 255 pm_mrk_pteg5</td>

</tr>

<tr><td>PM_MRK_STCX_FAIL_GRP256</td><td> A marked stcx (stwcx or stdcx) failed </td><td> 0</td><td>	Group 256 pm_mrk_misc1</td>

</tr>

<tr><td>PM_INST_CMPL_GRP256</td><td> Number of PowerPC Instructions that completed. </td><td> 1</td><td>	Group 256 pm_mrk_misc1</td>

</tr>

<tr><td>PM_MRK_IFU_FIN_GRP256</td><td> The Instruction Fetch Unit finished a marked instruction. </td><td> 2</td><td>	Group 256 pm_mrk_misc1</td>

</tr>

<tr><td>PM_MRK_INST_TIMEO_GRP256</td><td> The number of instructions finished since the last progress indicator from a marked instruction exceeded the threshold. The marked instruction was flushed. </td><td> 3</td><td>	Group 256 pm_mrk_misc1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP256</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 256 pm_mrk_misc1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP256</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 256 pm_mrk_misc1</td>

</tr>

<tr><td>PM_INST_CMPL_GRP257</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 257 pm_mrk_misc2</td>

</tr>

<tr><td>PM_MRK_FXU_FIN_GRP257</td><td> One of the Fixed Point Units finished a marked instruction. Instructions that finish may not necessary complete. </td><td> 1</td><td>	Group 257 pm_mrk_misc2</td>

</tr>

<tr><td>PM_MRK_IFU_FIN_GRP257</td><td> The Instruction Fetch Unit finished a marked instruction. </td><td> 2</td><td>	Group 257 pm_mrk_misc2</td>

</tr>

<tr><td>PM_MRK_LSU_FIN_GRP257</td><td> One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete </td><td> 3</td><td>	Group 257 pm_mrk_misc2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP257</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 257 pm_mrk_misc2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP257</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 257 pm_mrk_misc2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP258</td><td> Number of PowerPC Instructions that completed. </td><td> 0</td><td>	Group 258 pm_mrk_misc3</td>

</tr>

<tr><td>PM_MRK_BRU_FIN_GRP258</td><td> The branch unit finished a marked instruction. Instructions that finish may not necessary complete. </td><td> 1</td><td>	Group 258 pm_mrk_misc3</td>

</tr>

<tr><td>PM_MRK_LSU_PARTIAL_CDF_GRP258</td><td> A partial cacheline was returned from the L3 for a marked load </td><td> 2</td><td>	Group 258 pm_mrk_misc3</td>

</tr>

<tr><td>PM_MRK_LSU_FIN_GRP258</td><td> One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete </td><td> 3</td><td>	Group 258 pm_mrk_misc3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP258</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 258 pm_mrk_misc3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP258</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 258 pm_mrk_misc3</td>

</tr>

<tr><td>PM_MRK_FIN_STALL_CYC_GRP259</td><td> Marked instruction Finish Stall cycles (marked finish after NTC) </td><td> 0</td><td>	Group 259 pm_mrk_misc4</td>

</tr>

<tr><td>PM_INST_CMPL_GRP259</td><td> Number of PowerPC Instructions that completed. </td><td> 1</td><td>	Group 259 pm_mrk_misc4</td>

</tr>

<tr><td>PM_MRK_VSU_FIN_GRP259</td><td> vsu (fpu) marked instr finish </td><td> 2</td><td>	Group 259 pm_mrk_misc4</td>

</tr>

<tr><td>PM_MRK_GRP_IC_MISS_GRP259</td><td> A group containing a marked (sampled) instruction experienced an instruction cache miss. </td><td> 3</td><td>	Group 259 pm_mrk_misc4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP259</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 259 pm_mrk_misc4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP259</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 259 pm_mrk_misc4</td>

</tr>

<tr><td>PM_MRK_FIN_STALL_CYC_COUNT_GRP260</td><td> Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #) </td><td> 0</td><td>	Group 260 pm_mrk_misc5</td>

</tr>

<tr><td>PM_MRK_DFU_FIN_GRP260</td><td> The Decimal Floating Point Unit finished a marked instruction. </td><td> 1</td><td>	Group 260 pm_mrk_misc5</td>

</tr>

<tr><td>PM_MRK_STALL_CMPLU_CYC_COUNT_GRP260</td><td> Marked Group Completion Stall cycles (use edge detect to count #) </td><td> 2</td><td>	Group 260 pm_mrk_misc5</td>

</tr>

<tr><td>PM_INST_CMPL_GRP260</td><td> Number of PowerPC Instructions that completed. </td><td> 3</td><td>	Group 260 pm_mrk_misc5</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP260</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 260 pm_mrk_misc5</td>

</tr>

<tr><td>PM_RUN_CYC_GRP260</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 260 pm_mrk_misc5</td>

</tr>

<tr><td>PM_GRP_MRK_CYC_GRP261</td><td> cycles IDU marked instruction before dispatch </td><td> 0</td><td>	Group 261 pm_mrk_misc6</td>

</tr>

<tr><td>PM_RUN_CYC_GRP261</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 1</td><td>	Group 261 pm_mrk_misc6</td>

</tr>

<tr><td>PM_INST_CMPL_GRP261</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 261 pm_mrk_misc6</td>

</tr>

<tr><td>PM_MRK_GRP_CMPL_GRP261</td><td> A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group. </td><td> 3</td><td>	Group 261 pm_mrk_misc6</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP261</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 261 pm_mrk_misc6</td>

</tr>

<tr><td>PM_RUN_CYC_GRP261</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 261 pm_mrk_misc6</td>

</tr>

<tr><td>PM_MRK_LSU_REJECT_LHS_GRP262</td><td> The Load Store Unit rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully </td><td> 0</td><td>	Group 262 pm_mrk_misc7</td>

</tr>

<tr><td>PM_INST_CMPL_GRP262</td><td> Number of PowerPC Instructions that completed. </td><td> 1</td><td>	Group 262 pm_mrk_misc7</td>

</tr>

<tr><td>PM_MRK_LSU_REJECT_ERAT_MISS_GRP262</td><td> LSU marked reject due to ERAT (up to 2 per cycle) </td><td> 2</td><td>	Group 262 pm_mrk_misc7</td>

</tr>

<tr><td>PM_MRK_LSU_REJECT_GRP262</td><td> LSU marked reject (up to 2 per cycle) </td><td> 3</td><td>	Group 262 pm_mrk_misc7</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP262</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 262 pm_mrk_misc7</td>

</tr>

<tr><td>PM_RUN_CYC_GRP262</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 262 pm_mrk_misc7</td>

</tr>

<tr><td>PM_CYC_GRP263</td><td> Processor Cycles </td><td> 0</td><td>	Group 263 pm_mrk_misc8</td>

</tr>

<tr><td>PM_CYC_GRP263</td><td> Processor Cycles </td><td> 1</td><td>	Group 263 pm_mrk_misc8</td>

</tr>

<tr><td>PM_INST_CMPL_GRP263</td><td> Number of PowerPC Instructions that completed. </td><td> 2</td><td>	Group 263 pm_mrk_misc8</td>

</tr>

<tr><td>PM_MRK_LSU_FIN_GRP263</td><td> One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete </td><td> 3</td><td>	Group 263 pm_mrk_misc8</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP263</td><td> Number of run instructions completed. </td><td> 4</td><td>	Group 263 pm_mrk_misc8</td>

</tr>

<tr><td>PM_RUN_CYC_GRP263</td><td> Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. </td><td> 5</td><td>	Group 263 pm_mrk_misc8</td>

</tr>

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