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<tr><td>CYCLES</td><td>	Processor Cycles </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_RUN_CYC_GRP1</td><td> Run cycles </td><td> 0</td><td>	Group 1 pm_utilization</td>

</tr>

<tr><td>PM_INST_CMPL_GRP1</td><td> Instructions completed </td><td> 1</td><td>	Group 1 pm_utilization</td>

</tr>

<tr><td>PM_INST_DISP_GRP1</td><td> Instructions dispatched </td><td> 2</td><td>	Group 1 pm_utilization</td>

</tr>

<tr><td>PM_CYC_GRP1</td><td> Processor cycles </td><td> 3</td><td>	Group 1 pm_utilization</td>

</tr>

<tr><td>PM_THRD_ONE_RUN_CYC_GRP2</td><td> One of the threads in run cycles </td><td> 0</td><td>	Group 2 pm_utilization_capacity</td>

</tr>

<tr><td>PM_CYC_GRP2</td><td> Processor cycles </td><td> 1</td><td>	Group 2 pm_utilization_capacity</td>

</tr>

<tr><td>PM_THRD_CONC_RUN_INST_GRP2</td><td> Concurrent run instructions </td><td> 2</td><td>	Group 2 pm_utilization_capacity</td>

</tr>

<tr><td>PM_RUN_PURR_GRP2</td><td> Run PURR Event </td><td> 3</td><td>	Group 2 pm_utilization_capacity</td>

</tr>

<tr><td>PM_BR_PRED_CR_GRP3</td><td> A conditional branch was predicted, CR prediction </td><td> 0</td><td>	Group 3 pm_branch</td>

</tr>

<tr><td>PM_BR_MPRED_CR_GRP3</td><td> Branch mispredictions due to CR bit setting </td><td> 1</td><td>	Group 3 pm_branch</td>

</tr>

<tr><td>PM_BR_PRED_GRP3</td><td> A conditional branch was predicted </td><td> 2</td><td>	Group 3 pm_branch</td>

</tr>

<tr><td>PM_BR_MPRED_COUNT_GRP3</td><td> Branch misprediction due to count prediction </td><td> 3</td><td>	Group 3 pm_branch</td>

</tr>

<tr><td>PM_BR_PRED_CCACHE_GRP4</td><td> Branch count cache prediction </td><td> 0</td><td>	Group 4 pm_branch2</td>

</tr>

<tr><td>PM_BR_PRED_LSTACK_GRP4</td><td> A conditional branch was predicted, link stack </td><td> 1</td><td>	Group 4 pm_branch2</td>

</tr>

<tr><td>PM_BR_MPRED_CCACHE_GRP4</td><td> Branch misprediction due to count cache prediction </td><td> 2</td><td>	Group 4 pm_branch2</td>

</tr>

<tr><td>PM_BR_MPRED_TA_GRP4</td><td> Branch mispredictions due to target address </td><td> 3</td><td>	Group 4 pm_branch2</td>

</tr>

<tr><td>PM_BR_PRED_GRP5</td><td> A conditional branch was predicted </td><td> 0</td><td>	Group 5 pm_branch3</td>

</tr>

<tr><td>PM_BR_PRED_CR_GRP5</td><td> A conditional branch was predicted, CR prediction </td><td> 1</td><td>	Group 5 pm_branch3</td>

</tr>

<tr><td>PM_BR_PRED_CCACHE_GRP5</td><td> Branch count cache prediction </td><td> 2</td><td>	Group 5 pm_branch3</td>

</tr>

<tr><td>PM_BR_PRED_LSTACK_GRP5</td><td> A conditional branch was predicted, link stack </td><td> 3</td><td>	Group 5 pm_branch3</td>

</tr>

<tr><td>PM_BR_MPRED_CR_GRP6</td><td> Branch mispredictions due to CR bit setting </td><td> 0</td><td>	Group 6 pm_branch4</td>

</tr>

<tr><td>PM_BR_MPRED_COUNT_GRP6</td><td> Branch misprediction due to count prediction </td><td> 1</td><td>	Group 6 pm_branch4</td>

</tr>

<tr><td>PM_BR_MPRED_TA_GRP6</td><td> Branch mispredictions due to target address </td><td> 2</td><td>	Group 6 pm_branch4</td>

</tr>

<tr><td>PM_BR_MPRED_CCACHE_GRP6</td><td> Branch misprediction due to count cache prediction </td><td> 3</td><td>	Group 6 pm_branch4</td>

</tr>

<tr><td>PM_BR_PRED_GRP7</td><td> A conditional branch was predicted </td><td> 0</td><td>	Group 7 pm_branch5</td>

</tr>

<tr><td>PM_BR_TAKEN_GRP7</td><td> Branches taken </td><td> 1</td><td>	Group 7 pm_branch5</td>

</tr>

<tr><td>PM_BRU_FIN_GRP7</td><td> BRU produced a result </td><td> 2</td><td>	Group 7 pm_branch5</td>

</tr>

<tr><td>PM_BR_MPRED_GRP7</td><td> Branches incorrectly predicted </td><td> 3</td><td>	Group 7 pm_branch5</td>

</tr>

<tr><td>PM_DATA_FROM_L2_GRP8</td><td> Data loaded from L2 </td><td> 0</td><td>	Group 8 pm_dsource</td>

</tr>

<tr><td>PM_DATA_FROM_L21_GRP8</td><td> Data loaded from private L2 other core </td><td> 1</td><td>	Group 8 pm_dsource</td>

</tr>

<tr><td>PM_DATA_FROM_L2MISS_GRP8</td><td> Data loaded missed L2 </td><td> 2</td><td>	Group 8 pm_dsource</td>

</tr>

<tr><td>PM_DATA_FROM_L3MISS_GRP8</td><td> Data loaded from private L3 miss </td><td> 3</td><td>	Group 8 pm_dsource</td>

</tr>

<tr><td>PM_DATA_FROM_L35_MOD_GRP9</td><td> Data loaded from L3.5 modified </td><td> 0</td><td>	Group 9 pm_dsource2</td>

</tr>

<tr><td>PM_DATA_FROM_L35_SHR_GRP9</td><td> Data loaded from L3.5 shared </td><td> 1</td><td>	Group 9 pm_dsource2</td>

</tr>

<tr><td>PM_DATA_FROM_L3_GRP9</td><td> Data loaded from L3 </td><td> 2</td><td>	Group 9 pm_dsource2</td>

</tr>

<tr><td>PM_DATA_FROM_L3MISS_GRP9</td><td> Data loaded from private L3 miss </td><td> 3</td><td>	Group 9 pm_dsource2</td>

</tr>

<tr><td>PM_DATA_FROM_L35_MOD_GRP10</td><td> Data loaded from L3.5 modified </td><td> 0</td><td>	Group 10 pm_dsource3</td>

</tr>

<tr><td>PM_DATA_FROM_L35_SHR_GRP10</td><td> Data loaded from L3.5 shared </td><td> 1</td><td>	Group 10 pm_dsource3</td>

</tr>

<tr><td>PM_DATA_FROM_L25_MOD_GRP10</td><td> Data loaded from L2.5 modified </td><td> 2</td><td>	Group 10 pm_dsource3</td>

</tr>

<tr><td>PM_DATA_FROM_L25_SHR_GRP10</td><td> Data loaded from L2.5 shared </td><td> 3</td><td>	Group 10 pm_dsource3</td>

</tr>

<tr><td>PM_DATA_FROM_RL2L3_MOD_GRP11</td><td> Data loaded from remote L2 or L3 modified </td><td> 0</td><td>	Group 11 pm_dsource4</td>

</tr>

<tr><td>PM_DATA_FROM_RL2L3_SHR_GRP11</td><td> Data loaded from remote L2 or L3 shared </td><td> 1</td><td>	Group 11 pm_dsource4</td>

</tr>

<tr><td>PM_DATA_FROM_DL2L3_SHR_GRP11</td><td> Data loaded from distant L2 or L3 shared </td><td> 2</td><td>	Group 11 pm_dsource4</td>

</tr>

<tr><td>PM_DATA_FROM_DL2L3_MOD_GRP11</td><td> Data loaded from distant L2 or L3 modified </td><td> 3</td><td>	Group 11 pm_dsource4</td>

</tr>

<tr><td>PM_DATA_FROM_MEM_DP_GRP12</td><td> Data loaded from double pump memory </td><td> 0</td><td>	Group 12 pm_dsource5</td>

</tr>

<tr><td>PM_DATA_FROM_DMEM_GRP12</td><td> Data loaded from distant memory </td><td> 1</td><td>	Group 12 pm_dsource5</td>

</tr>

<tr><td>PM_DATA_FROM_RMEM_GRP12</td><td> Data loaded from remote memory </td><td> 2</td><td>	Group 12 pm_dsource5</td>

</tr>

<tr><td>PM_DATA_FROM_LMEM_GRP12</td><td> Data loaded from local memory </td><td> 3</td><td>	Group 12 pm_dsource5</td>

</tr>

<tr><td>PM_LD_MISS_L1_CYC_GRP13</td><td> L1 data load miss cycles </td><td> 0</td><td>	Group 13 pm_dlatencies</td>

</tr>

<tr><td>PM_DATA_FROM_RL2L3_SHR_CYC_GRP13</td><td> Load latency from remote L2 or L3 shared </td><td> 1</td><td>	Group 13 pm_dlatencies</td>

</tr>

<tr><td>PM_CYC_GRP13</td><td> Processor cycles </td><td> 2</td><td>	Group 13 pm_dlatencies</td>

</tr>

<tr><td>PM_DATA_FROM_L25_MOD_CYC_GRP13</td><td> Load latency from L2.5 modified </td><td> 3</td><td>	Group 13 pm_dlatencies</td>

</tr>

<tr><td>PM_INST_CMPL_GRP14</td><td> Instructions completed </td><td> 0</td><td>	Group 14 pm_dlatencies2</td>

</tr>

<tr><td>PM_DATA_FROM_LMEM_CYC_GRP14</td><td> Load latency from local memory </td><td> 1</td><td>	Group 14 pm_dlatencies2</td>

</tr>

<tr><td>PM_CYC_GRP14</td><td> Processor cycles </td><td> 2</td><td>	Group 14 pm_dlatencies2</td>

</tr>

<tr><td>PM_DATA_FROM_DL2L3_MOD_CYC_GRP14</td><td> Load latency from distant L2 or L3 modified </td><td> 3</td><td>	Group 14 pm_dlatencies2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP15</td><td> Instructions completed </td><td> 0</td><td>	Group 15 pm_dlatencies3</td>

</tr>

<tr><td>PM_DATA_FROM_DMEM_CYC_GRP15</td><td> Load latency from distant memory </td><td> 1</td><td>	Group 15 pm_dlatencies3</td>

</tr>

<tr><td>PM_DATA_FROM_RMEM_GRP15</td><td> Data loaded from remote memory </td><td> 2</td><td>	Group 15 pm_dlatencies3</td>

</tr>

<tr><td>PM_DATA_FROM_RMEM_CYC_GRP15</td><td> Load latency from remote memory </td><td> 3</td><td>	Group 15 pm_dlatencies3</td>

</tr>

<tr><td>PM_DATA_FROM_L35_MOD_GRP16</td><td> Data loaded from L3.5 modified </td><td> 0</td><td>	Group 16 pm_dlatencies4</td>

</tr>

<tr><td>PM_DATA_FROM_DL2L3_SHR_CYC_GRP16</td><td> Load latency from distant L2 or L3 shared </td><td> 1</td><td>	Group 16 pm_dlatencies4</td>

</tr>

<tr><td>PM_DATA_FROM_DL2L3_SHR_GRP16</td><td> Data loaded from distant L2 or L3 shared </td><td> 2</td><td>	Group 16 pm_dlatencies4</td>

</tr>

<tr><td>PM_DATA_FROM_L35_MOD_CYC_GRP16</td><td> Load latency from L3.5 modified </td><td> 3</td><td>	Group 16 pm_dlatencies4</td>

</tr>

<tr><td>PM_DATA_FROM_RL2L3_MOD_GRP17</td><td> Data loaded from remote L2 or L3 modified </td><td> 0</td><td>	Group 17 pm_dlatencies5</td>

</tr>

<tr><td>PM_DATA_FROM_L3_CYC_GRP17</td><td> Load latency from L3 </td><td> 1</td><td>	Group 17 pm_dlatencies5</td>

</tr>

<tr><td>PM_DATA_FROM_L3_GRP17</td><td> Data loaded from L3 </td><td> 2</td><td>	Group 17 pm_dlatencies5</td>

</tr>

<tr><td>PM_DATA_FROM_RL2L3_MOD_CYC_GRP17</td><td> Load latency from remote L2 or L3 modified </td><td> 3</td><td>	Group 17 pm_dlatencies5</td>

</tr>

<tr><td>PM_DATA_FROM_MEM_DP_GRP18</td><td> Data loaded from double pump memory </td><td> 0</td><td>	Group 18 pm_dlatencies6</td>

</tr>

<tr><td>PM_DATA_FROM_L25_SHR_CYC_GRP18</td><td> Load latency from L2.5 shared </td><td> 1</td><td>	Group 18 pm_dlatencies6</td>

</tr>

<tr><td>PM_DATA_FROM_L25_MOD_GRP18</td><td> Data loaded from L2.5 modified </td><td> 2</td><td>	Group 18 pm_dlatencies6</td>

</tr>

<tr><td>PM_DATA_FROM_MEM_DP_CYC_GRP18</td><td> Load latency from double pump memory </td><td> 3</td><td>	Group 18 pm_dlatencies6</td>

</tr>

<tr><td>PM_DATA_FROM_L2_GRP19</td><td> Data loaded from L2 </td><td> 0</td><td>	Group 19 pm_dlatencies7</td>

</tr>

<tr><td>PM_DATA_FROM_L2_CYC_GRP19</td><td> Load latency from L2 </td><td> 1</td><td>	Group 19 pm_dlatencies7</td>

</tr>

<tr><td>PM_INST_DISP_GRP19</td><td> Instructions dispatched </td><td> 2</td><td>	Group 19 pm_dlatencies7</td>

</tr>

<tr><td>PM_L1_DCACHE_RELOAD_VALID_GRP19</td><td> L1 reload data source valid </td><td> 3</td><td>	Group 19 pm_dlatencies7</td>

</tr>

<tr><td>PM_FLUSH_GRP20</td><td> Flushes </td><td> 0</td><td>	Group 20 pm_dlatencies8</td>

</tr>

<tr><td>PM_DATA_FROM_L21_GRP20</td><td> Data loaded from private L2 other core </td><td> 1</td><td>	Group 20 pm_dlatencies8</td>

</tr>

<tr><td>PM_CYC_GRP20</td><td> Processor cycles </td><td> 2</td><td>	Group 20 pm_dlatencies8</td>

</tr>

<tr><td>PM_DATA_FROM_L21_CYC_GRP20</td><td> Load latency from private L2 other core </td><td> 3</td><td>	Group 20 pm_dlatencies8</td>

</tr>

<tr><td>PM_1PLUS_PPC_DISP_GRP21</td><td> Cycles at least one instruction dispatched </td><td> 0</td><td>	Group 21 pm_dlatencies9</td>

</tr>

<tr><td>PM_DATA_FROM_LMEM_CYC_GRP21</td><td> Load latency from local memory </td><td> 1</td><td>	Group 21 pm_dlatencies9</td>

</tr>

<tr><td>PM_INST_DISP_GRP21</td><td> Instructions dispatched </td><td> 2</td><td>	Group 21 pm_dlatencies9</td>

</tr>

<tr><td>PM_DATA_FROM_LMEM_GRP21</td><td> Data loaded from local memory </td><td> 3</td><td>	Group 21 pm_dlatencies9</td>

</tr>

<tr><td>PM_DATA_FROM_L35_MOD_GRP22</td><td> Data loaded from L3.5 modified </td><td> 0</td><td>	Group 22 pm_dlatencies10</td>

</tr>

<tr><td>PM_DATA_FROM_L35_SHR_CYC_GRP22</td><td> Load latency from L3.5 shared </td><td> 1</td><td>	Group 22 pm_dlatencies10</td>

</tr>

<tr><td>PM_CYC_GRP22</td><td> Processor cycles </td><td> 2</td><td>	Group 22 pm_dlatencies10</td>

</tr>

<tr><td>PM_DATA_FROM_L35_MOD_CYC_GRP22</td><td> Load latency from L3.5 modified </td><td> 3</td><td>	Group 22 pm_dlatencies10</td>

</tr>

<tr><td>PM_INST_FROM_L2_GRP23</td><td> Instructions fetched from L2 </td><td> 0</td><td>	Group 23 pm_isource</td>

</tr>

<tr><td>PM_INST_FROM_L21_GRP23</td><td> Instruction fetched from private L2 other core </td><td> 1</td><td>	Group 23 pm_isource</td>

</tr>

<tr><td>PM_INST_FROM_L25_MOD_GRP23</td><td> Instruction fetched from L2.5 modified </td><td> 2</td><td>	Group 23 pm_isource</td>

</tr>

<tr><td>PM_INST_FROM_L2MISS_GRP23</td><td> Instructions fetched missed L2 </td><td> 3</td><td>	Group 23 pm_isource</td>

</tr>

<tr><td>PM_INST_FROM_L35_MOD_GRP24</td><td> Instruction fetched from L3.5 modified </td><td> 0</td><td>	Group 24 pm_isource2</td>

</tr>

<tr><td>PM_INST_FROM_L35_SHR_GRP24</td><td> Instruction fetched from L3.5 shared </td><td> 1</td><td>	Group 24 pm_isource2</td>

</tr>

<tr><td>PM_INST_FROM_L3_GRP24</td><td> Instruction fetched from L3 </td><td> 2</td><td>	Group 24 pm_isource2</td>

</tr>

<tr><td>PM_INST_FROM_L25_SHR_GRP24</td><td> Instruction fetched from L2.5 shared </td><td> 3</td><td>	Group 24 pm_isource2</td>

</tr>

<tr><td>PM_INST_FROM_RL2L3_MOD_GRP25</td><td> Instruction fetched from remote L2 or L3 modified </td><td> 0</td><td>	Group 25 pm_isource3</td>

</tr>

<tr><td>PM_INST_FROM_RL2L3_SHR_GRP25</td><td> Instruction fetched from remote L2 or L3 shared </td><td> 1</td><td>	Group 25 pm_isource3</td>

</tr>

<tr><td>PM_INST_FROM_DL2L3_SHR_GRP25</td><td> Instruction fetched from distant L2 or L3 shared </td><td> 2</td><td>	Group 25 pm_isource3</td>

</tr>

<tr><td>PM_INST_FROM_DL2L3_MOD_GRP25</td><td> Instruction fetched from distant L2 or L3 modified </td><td> 3</td><td>	Group 25 pm_isource3</td>

</tr>

<tr><td>PM_INST_FROM_MEM_DP_GRP26</td><td> Instruction fetched from double pump memory </td><td> 0</td><td>	Group 26 pm_isource4</td>

</tr>

<tr><td>PM_INST_FROM_DMEM_GRP26</td><td> Instruction fetched from distant memory </td><td> 1</td><td>	Group 26 pm_isource4</td>

</tr>

<tr><td>PM_INST_FROM_RMEM_GRP26</td><td> Instruction fetched from remote memory </td><td> 2</td><td>	Group 26 pm_isource4</td>

</tr>

<tr><td>PM_INST_FROM_LMEM_GRP26</td><td> Instruction fetched from local memory </td><td> 3</td><td>	Group 26 pm_isource4</td>

</tr>

<tr><td>PM_INST_FROM_L2_GRP27</td><td> Instructions fetched from L2 </td><td> 0</td><td>	Group 27 pm_isource5</td>

</tr>

<tr><td>PM_INST_FROM_L21_GRP27</td><td> Instruction fetched from private L2 other core </td><td> 1</td><td>	Group 27 pm_isource5</td>

</tr>

<tr><td>PM_INST_FROM_L3MISS_GRP27</td><td> Instruction fetched missed L3 </td><td> 2</td><td>	Group 27 pm_isource5</td>

</tr>

<tr><td>PM_INST_FROM_L2MISS_GRP27</td><td> Instructions fetched missed L2 </td><td> 3</td><td>	Group 27 pm_isource5</td>

</tr>

<tr><td>PM_PTEG_FROM_L2_GRP28</td><td> PTEG loaded from L2 </td><td> 0</td><td>	Group 28 pm_pteg</td>

</tr>

<tr><td>PM_PTEG_FROM_L21_GRP28</td><td> PTEG loaded from private L2 other core </td><td> 1</td><td>	Group 28 pm_pteg</td>

</tr>

<tr><td>PM_PTEG_FROM_L25_MOD_GRP28</td><td> PTEG loaded from L2.5 modified </td><td> 2</td><td>	Group 28 pm_pteg</td>

</tr>

<tr><td>PM_PTEG_FROM_L25_SHR_GRP28</td><td> PTEG loaded from L2.5 shared </td><td> 3</td><td>	Group 28 pm_pteg</td>

</tr>

<tr><td>PM_PTEG_FROM_L2MISS_GRP29</td><td> PTEG loaded from L2 miss </td><td> 0</td><td>	Group 29 pm_pteg2</td>

</tr>

<tr><td>PM_PTEG_FROM_L21_GRP29</td><td> PTEG loaded from private L2 other core </td><td> 1</td><td>	Group 29 pm_pteg2</td>

</tr>

<tr><td>PM_PTEG_FROM_L3_GRP29</td><td> PTEG loaded from L3 </td><td> 2</td><td>	Group 29 pm_pteg2</td>

</tr>

<tr><td>PM_PTEG_FROM_DL2L3_MOD_GRP29</td><td> PTEG loaded from distant L2 or L3 modified </td><td> 3</td><td>	Group 29 pm_pteg2</td>

</tr>

<tr><td>PM_PTEG_FROM_L35_MOD_GRP30</td><td> PTEG loaded from L3.5 modified </td><td> 0</td><td>	Group 30 pm_pteg3</td>

</tr>

<tr><td>PM_PTEG_FROM_L35_SHR_GRP30</td><td> PTEG loaded from L3.5 shared </td><td> 1</td><td>	Group 30 pm_pteg3</td>

</tr>

<tr><td>PM_PTEG_FROM_L3MISS_GRP30</td><td> PTEG loaded from L3 miss </td><td> 2</td><td>	Group 30 pm_pteg3</td>

</tr>

<tr><td>PM_PTEG_FROM_LMEM_GRP30</td><td> PTEG loaded from local memory </td><td> 3</td><td>	Group 30 pm_pteg3</td>

</tr>

<tr><td>PM_PTEG_FROM_MEM_DP_GRP31</td><td> PTEG loaded from double pump memory </td><td> 0</td><td>	Group 31 pm_pteg4</td>

</tr>

<tr><td>PM_PTEG_FROM_DMEM_GRP31</td><td> PTEG loaded from distant memory </td><td> 1</td><td>	Group 31 pm_pteg4</td>

</tr>

<tr><td>PM_PTEG_FROM_RMEM_GRP31</td><td> PTEG loaded from remote memory </td><td> 2</td><td>	Group 31 pm_pteg4</td>

</tr>

<tr><td>PM_PTEG_FROM_LMEM_GRP31</td><td> PTEG loaded from local memory </td><td> 3</td><td>	Group 31 pm_pteg4</td>

</tr>

<tr><td>PM_PTEG_FROM_RL2L3_MOD_GRP32</td><td> PTEG loaded from remote L2 or L3 modified </td><td> 0</td><td>	Group 32 pm_pteg5</td>

</tr>

<tr><td>PM_PTEG_FROM_RL2L3_SHR_GRP32</td><td> PTEG loaded from remote L2 or L3 shared </td><td> 1</td><td>	Group 32 pm_pteg5</td>

</tr>

<tr><td>PM_PTEG_FROM_DL2L3_SHR_GRP32</td><td> PTEG loaded from distant L2 or L3 shared </td><td> 2</td><td>	Group 32 pm_pteg5</td>

</tr>

<tr><td>PM_PTEG_RELOAD_VALID_GRP32</td><td> TLB reload valid </td><td> 3</td><td>	Group 32 pm_pteg5</td>

</tr>

<tr><td>PM_DATA_PTEG_1ST_HALF_GRP33</td><td> Data table walk matched in first half primary PTEG </td><td> 0</td><td>	Group 33 pm_data_tablewalk</td>

</tr>

<tr><td>PM_DATA_PTEG_2ND_HALF_GRP33</td><td> Data table walk matched in second half primary PTEG </td><td> 1</td><td>	Group 33 pm_data_tablewalk</td>

</tr>

<tr><td>PM_DATA_PTEG_SECONDARY_GRP33</td><td> Data table walk matched in secondary PTEG </td><td> 2</td><td>	Group 33 pm_data_tablewalk</td>

</tr>

<tr><td>PM_TLB_REF_GRP33</td><td> TLB reference </td><td> 3</td><td>	Group 33 pm_data_tablewalk</td>

</tr>

<tr><td>PM_INST_PTEG_1ST_HALF_GRP34</td><td> Instruction table walk matched in first half primary PTEG </td><td> 0</td><td>	Group 34 pm_inst_tablewalk</td>

</tr>

<tr><td>PM_INST_PTEG_2ND_HALF_GRP34</td><td> Instruction table walk matched in second half primary PTEG </td><td> 1</td><td>	Group 34 pm_inst_tablewalk</td>

</tr>

<tr><td>PM_INST_PTEG_SECONDARY_GRP34</td><td> Instruction table walk matched in secondary PTEG </td><td> 2</td><td>	Group 34 pm_inst_tablewalk</td>

</tr>

<tr><td>PM_INST_TABLEWALK_CYC_GRP34</td><td> Cycles doing instruction tablewalks </td><td> 3</td><td>	Group 34 pm_inst_tablewalk</td>

</tr>

<tr><td>PM_DPU_HELD_THERMAL_GRP35</td><td> DISP unit held due to thermal condition </td><td> 0</td><td>	Group 35 pm_freq</td>

</tr>

<tr><td>PM_DPU_HELD_POWER_GRP35</td><td> DISP unit held due to Power Management </td><td> 1</td><td>	Group 35 pm_freq</td>

</tr>

<tr><td>PM_FREQ_DOWN_GRP35</td><td> Frequency is being slewed down due to Power Management </td><td> 2</td><td>	Group 35 pm_freq</td>

</tr>

<tr><td>PM_FREQ_UP_GRP35</td><td> Frequency is being slewed up due to Power Management </td><td> 3</td><td>	Group 35 pm_freq</td>

</tr>

<tr><td>PM_L1_ICACHE_MISS_GRP36</td><td> L1 I cache miss count </td><td> 0</td><td>	Group 36 pm_disp_wait</td>

</tr>

<tr><td>PM_DPU_WT_IC_MISS_GRP36</td><td> Cycles DISP unit is stalled due to I cache miss </td><td> 1</td><td>	Group 36 pm_disp_wait</td>

</tr>

<tr><td>PM_DPU_WT_GRP36</td><td> Cycles DISP unit is stalled waiting for instructions </td><td> 2</td><td>	Group 36 pm_disp_wait</td>

</tr>

<tr><td>PM_DPU_WT_BR_MPRED_GRP36</td><td> Cycles DISP unit is stalled due to branch misprediction </td><td> 3</td><td>	Group 36 pm_disp_wait</td>

</tr>

<tr><td>PM_DPU_HELD_THERMAL_GRP37</td><td> DISP unit held due to thermal condition </td><td> 0</td><td>	Group 37 pm_disp_held</td>

</tr>

<tr><td>PM_DPU_HELD_POWER_GRP37</td><td> DISP unit held due to Power Management </td><td> 1</td><td>	Group 37 pm_disp_held</td>

</tr>

<tr><td>PM_THERMAL_MAX_GRP37</td><td> Processor in thermal MAX </td><td> 2</td><td>	Group 37 pm_disp_held</td>

</tr>

<tr><td>PM_DPU_HELD_SMT_GRP37</td><td> DISP unit held due to SMT conflicts  </td><td> 3</td><td>	Group 37 pm_disp_held</td>

</tr>

<tr><td>PM_DPU_HELD_GPR_GRP38</td><td> DISP unit held due to GPR dependencies </td><td> 0</td><td>	Group 38 pm_disp_held2</td>

</tr>

<tr><td>PM_DPU_HELD_GRP38</td><td> DISP unit held </td><td> 1</td><td>	Group 38 pm_disp_held2</td>

</tr>

<tr><td>PM_DPU_HELD_CW_GRP38</td><td> DISP unit held due to cache writes  </td><td> 2</td><td>	Group 38 pm_disp_held2</td>

</tr>

<tr><td>PM_DPU_HELD_FPQ_GRP38</td><td> DISP unit held due to FPU issue queue full </td><td> 3</td><td>	Group 38 pm_disp_held2</td>

</tr>

<tr><td>PM_DPU_HELD_XER_GRP39</td><td> DISP unit held due to XER dependency </td><td> 0</td><td>	Group 39 pm_disp_held3</td>

</tr>

<tr><td>PM_DPU_HELD_ISYNC_GRP39</td><td> DISP unit held due to ISYNC  </td><td> 1</td><td>	Group 39 pm_disp_held3</td>

</tr>

<tr><td>PM_DPU_HELD_STCX_CR_GRP39</td><td> DISP unit held due to STCX updating CR  </td><td> 2</td><td>	Group 39 pm_disp_held3</td>

</tr>

<tr><td>PM_DPU_HELD_RU_WQ_GRP39</td><td> DISP unit held due to RU FXU write queue full </td><td> 3</td><td>	Group 39 pm_disp_held3</td>

</tr>

<tr><td>PM_DPU_HELD_FPU_CR_GRP40</td><td> DISP unit held due to FPU updating CR </td><td> 0</td><td>	Group 40 pm_disp_held4</td>

</tr>

<tr><td>PM_DPU_HELD_LSU_GRP40</td><td> DISP unit held due to LSU move or invalidate SLB and SR </td><td> 1</td><td>	Group 40 pm_disp_held4</td>

</tr>

<tr><td>PM_DPU_HELD_ITLB_ISLB_GRP40</td><td> DISP unit held due to SLB or TLB invalidates  </td><td> 2</td><td>	Group 40 pm_disp_held4</td>

</tr>

<tr><td>PM_DPU_HELD_FXU_MULTI_GRP40</td><td> DISP unit held due to FXU multicycle </td><td> 3</td><td>	Group 40 pm_disp_held4</td>

</tr>

<tr><td>PM_DPU_HELD_FP_FX_MULT_GRP41</td><td> DISP unit held due to non fixed multiple/divide after fixed multiply/divide </td><td> 0</td><td>	Group 41 pm_disp_held5</td>

</tr>

<tr><td>PM_DPU_HELD_MULT_GPR_GRP41</td><td> DISP unit held due to multiple/divide multiply/divide GPR dependencies </td><td> 1</td><td>	Group 41 pm_disp_held5</td>

</tr>

<tr><td>PM_DPU_HELD_COMPLETION_GRP41</td><td> DISP unit held due to completion holding dispatch  </td><td> 2</td><td>	Group 41 pm_disp_held5</td>

</tr>

<tr><td>PM_DPU_HELD_GPR_GRP41</td><td> DISP unit held due to GPR dependencies </td><td> 3</td><td>	Group 41 pm_disp_held5</td>

</tr>

<tr><td>PM_DPU_HELD_INT_GRP42</td><td> DISP unit held due to exception </td><td> 0</td><td>	Group 42 pm_disp_held6</td>

</tr>

<tr><td>PM_DPU_HELD_XTHRD_GRP42</td><td> DISP unit held due to cross thread resource conflicts </td><td> 1</td><td>	Group 42 pm_disp_held6</td>

</tr>

<tr><td>PM_DPU_HELD_LLA_END_GRP42</td><td> DISP unit held due to load look ahead ended </td><td> 2</td><td>	Group 42 pm_disp_held6</td>

</tr>

<tr><td>PM_DPU_HELD_RESTART_GRP42</td><td> DISP unit held after restart coming </td><td> 3</td><td>	Group 42 pm_disp_held6</td>

</tr>

<tr><td>PM_DPU_HELD_FXU_SOPS_GRP43</td><td> DISP unit held due to FXU slow ops (mtmsr, scv, rfscv) </td><td> 0</td><td>	Group 43 pm_disp_held7</td>

</tr>

<tr><td>PM_DPU_HELD_THRD_PRIO_GRP43</td><td> DISP unit held due to lower priority thread </td><td> 1</td><td>	Group 43 pm_disp_held7</td>

</tr>

<tr><td>PM_DPU_HELD_SPR_GRP43</td><td> DISP unit held due to MTSPR/MFSPR </td><td> 2</td><td>	Group 43 pm_disp_held7</td>

</tr>

<tr><td>PM_DPU_HELD_CR_LOGICAL_GRP43</td><td> DISP unit held due to CR, LR or CTR updated by CR logical, MTCRF, MTLR or MTCTR </td><td> 3</td><td>	Group 43 pm_disp_held7</td>

</tr>

<tr><td>PM_DPU_HELD_ISYNC_GRP44</td><td> DISP unit held due to ISYNC  </td><td> 0</td><td>	Group 44 pm_disp_held8</td>

</tr>

<tr><td>PM_DPU_HELD_STCX_CR_GRP44</td><td> DISP unit held due to STCX updating CR  </td><td> 1</td><td>	Group 44 pm_disp_held8</td>

</tr>

<tr><td>PM_DPU_HELD_RU_WQ_GRP44</td><td> DISP unit held due to RU FXU write queue full </td><td> 2</td><td>	Group 44 pm_disp_held8</td>

</tr>

<tr><td>PM_DPU_HELD_FPU_CR_GRP44</td><td> DISP unit held due to FPU updating CR </td><td> 3</td><td>	Group 44 pm_disp_held8</td>

</tr>

<tr><td>PM_DPU_HELD_ISYNC_GRP45</td><td> DISP unit held due to ISYNC  </td><td> 0</td><td>	Group 45 pm_disp_held9</td>

</tr>

<tr><td>PM_DPU_HELD_FPU_CR_GRP45</td><td> DISP unit held due to FPU updating CR </td><td> 1</td><td>	Group 45 pm_disp_held9</td>

</tr>

<tr><td>PM_DPU_HELD_MULT_GPR_GRP45</td><td> DISP unit held due to multiple/divide multiply/divide GPR dependencies </td><td> 2</td><td>	Group 45 pm_disp_held9</td>

</tr>

<tr><td>PM_DPU_HELD_COMPLETION_GRP45</td><td> DISP unit held due to completion holding dispatch  </td><td> 3</td><td>	Group 45 pm_disp_held9</td>

</tr>

<tr><td>PM_LWSYNC_GRP46</td><td> Isync instruction completed </td><td> 0</td><td>	Group 46 pm_sync</td>

</tr>

<tr><td>PM_CYC_GRP46</td><td> Processor cycles </td><td> 1</td><td>	Group 46 pm_sync</td>

</tr>

<tr><td>PM_SYNC_CYC_GRP46</td><td> Sync duration </td><td> 2</td><td>	Group 46 pm_sync</td>

</tr>

<tr><td>PM_DPU_HELD_LSU_SOPS_GRP46</td><td> DISP unit held due to LSU slow ops (sync, tlbie, stcx) </td><td> 3</td><td>	Group 46 pm_sync</td>

</tr>

<tr><td>PM_LD_REF_L1_BOTH_GRP47</td><td> Both units L1 D cache load reference </td><td> 0</td><td>	Group 47 pm_L1_ref</td>

</tr>

<tr><td>PM_LD_REF_L1_GRP47</td><td> L1 D cache load references </td><td> 1</td><td>	Group 47 pm_L1_ref</td>

</tr>

<tr><td>PM_ST_REF_L1_GRP47</td><td> L1 D cache store references </td><td> 2</td><td>	Group 47 pm_L1_ref</td>

</tr>

<tr><td>PM_ST_REF_L1_BOTH_GRP47</td><td> Both units L1 D cache store reference </td><td> 3</td><td>	Group 47 pm_L1_ref</td>

</tr>

<tr><td>PM_ST_REF_L1_GRP48</td><td> L1 D cache store references </td><td> 0</td><td>	Group 48 pm_L1_ldst</td>

</tr>

<tr><td>PM_LD_REF_L1_GRP48</td><td> L1 D cache load references </td><td> 1</td><td>	Group 48 pm_L1_ldst</td>

</tr>

<tr><td>PM_ST_MISS_L1_GRP48</td><td> L1 D cache store misses </td><td> 2</td><td>	Group 48 pm_L1_ldst</td>

</tr>

<tr><td>PM_LD_MISS_L1_GRP48</td><td> L1 D cache load misses </td><td> 3</td><td>	Group 48 pm_L1_ldst</td>

</tr>

<tr><td>PM_DC_PREF_OUT_OF_STREAMS_GRP49</td><td> D cache out of streams </td><td> 0</td><td>	Group 49 pm_streams</td>

</tr>

<tr><td>PM_DC_PREF_STREAM_ALLOC_GRP49</td><td> D cache new prefetch stream allocated </td><td> 1</td><td>	Group 49 pm_streams</td>

</tr>

<tr><td>PM_L1_PREF_GRP49</td><td> L1 cache data prefetches </td><td> 2</td><td>	Group 49 pm_streams</td>

</tr>

<tr><td>PM_IBUF_FULL_CYC_GRP49</td><td> Cycles instruction buffer full </td><td> 3</td><td>	Group 49 pm_streams</td>

</tr>

<tr><td>PM_FLUSH_GRP50</td><td> Flushes </td><td> 0</td><td>	Group 50 pm_flush</td>

</tr>

<tr><td>PM_FLUSH_ASYNC_GRP50</td><td> Flush caused by asynchronous exception </td><td> 1</td><td>	Group 50 pm_flush</td>

</tr>

<tr><td>PM_FLUSH_FPU_GRP50</td><td> Flush caused by FPU exception </td><td> 2</td><td>	Group 50 pm_flush</td>

</tr>

<tr><td>PM_FLUSH_FXU_GRP50</td><td> Flush caused by FXU exception </td><td> 3</td><td>	Group 50 pm_flush</td>

</tr>

<tr><td>PM_IC_REQ_GRP51</td><td> I cache demand of prefetch request </td><td> 0</td><td>	Group 51 pm_prefetch</td>

</tr>

<tr><td>PM_IC_PREF_REQ_GRP51</td><td> Instruction prefetch requests </td><td> 1</td><td>	Group 51 pm_prefetch</td>

</tr>

<tr><td>PM_IC_RELOAD_SHR_GRP51</td><td> I cache line reloading to be shared by threads </td><td> 2</td><td>	Group 51 pm_prefetch</td>

</tr>

<tr><td>PM_IC_PREF_WRITE_GRP51</td><td> Instruction prefetch written into I cache </td><td> 3</td><td>	Group 51 pm_prefetch</td>

</tr>

<tr><td>PM_STCX_GRP52</td><td> STCX executed </td><td> 0</td><td>	Group 52 pm_stcx</td>

</tr>

<tr><td>PM_STCX_CANCEL_GRP52</td><td> stcx cancel by core </td><td> 1</td><td>	Group 52 pm_stcx</td>

</tr>

<tr><td>PM_STCX_FAIL_GRP52</td><td> STCX failed </td><td> 2</td><td>	Group 52 pm_stcx</td>

</tr>

<tr><td>PM_LARX_GRP52</td><td> Larx executed </td><td> 3</td><td>	Group 52 pm_stcx</td>

</tr>

<tr><td>PM_LARX_GRP53</td><td> Larx executed </td><td> 0</td><td>	Group 53 pm_larx</td>

</tr>

<tr><td>PM_LARX_L1HIT_GRP53</td><td> larx hits in L1 </td><td> 1</td><td>	Group 53 pm_larx</td>

</tr>

<tr><td>PM_STCX_GRP53</td><td> STCX executed </td><td> 2</td><td>	Group 53 pm_larx</td>

</tr>

<tr><td>PM_STCX_FAIL_GRP53</td><td> STCX failed </td><td> 3</td><td>	Group 53 pm_larx</td>

</tr>

<tr><td>PM_THRD_ONE_RUN_CYC_GRP54</td><td> One of the threads in run cycles </td><td> 0</td><td>	Group 54 pm_thread_cyc</td>

</tr>

<tr><td>PM_THRD_GRP_CMPL_BOTH_CYC_GRP54</td><td> Cycles group completed by both threads </td><td> 1</td><td>	Group 54 pm_thread_cyc</td>

</tr>

<tr><td>PM_THRD_CONC_RUN_INST_GRP54</td><td> Concurrent run instructions </td><td> 2</td><td>	Group 54 pm_thread_cyc</td>

</tr>

<tr><td>PM_THRD_BOTH_RUN_CYC_GRP54</td><td> Both threads in run cycles </td><td> 3</td><td>	Group 54 pm_thread_cyc</td>

</tr>

<tr><td>PM_1PLUS_PPC_CMPL_GRP55</td><td> One or more PPC instruction completed </td><td> 0</td><td>	Group 55 pm_misc</td>

</tr>

<tr><td>PM_HV_CYC_GRP55</td><td> Hypervisor Cycles </td><td> 1</td><td>	Group 55 pm_misc</td>

</tr>

<tr><td>PM_THRESH_TIMEO_GRP55</td><td> Threshold timeout </td><td> 2</td><td>	Group 55 pm_misc</td>

</tr>

<tr><td>PM_THRD_LLA_BOTH_CYC_GRP55</td><td> Both threads in Load Look Ahead </td><td> 3</td><td>	Group 55 pm_misc</td>

</tr>

<tr><td>PM_EE_OFF_EXT_INT_GRP56</td><td> Cycles MSR(EE) bit off and external interrupt pending </td><td> 0</td><td>	Group 56 pm_misc2</td>

</tr>

<tr><td>PM_EXT_INT_GRP56</td><td> External interrupts </td><td> 1</td><td>	Group 56 pm_misc2</td>

</tr>

<tr><td>PM_TB_BIT_TRANS_GRP56</td><td> Time Base bit transition </td><td> 2</td><td>	Group 56 pm_misc2</td>

</tr>

<tr><td>PM_0INST_FETCH_GRP56</td><td> No instructions fetched </td><td> 3</td><td>	Group 56 pm_misc2</td>

</tr>

<tr><td>PM_ST_FIN_GRP57</td><td> Store instructions finished </td><td> 0</td><td>	Group 57 pm_misc3</td>

</tr>

<tr><td>PM_THRD_L2MISS_GRP57</td><td> Thread in L2 miss </td><td> 1</td><td>	Group 57 pm_misc3</td>

</tr>

<tr><td>PM_CYC_GRP57</td><td> Processor cycles </td><td> 2</td><td>	Group 57 pm_misc3</td>

</tr>

<tr><td>PM_INST_CMPL_GRP57</td><td> Instructions completed </td><td> 3</td><td>	Group 57 pm_misc3</td>

</tr>

<tr><td>PM_ISLB_MISS_GRP58</td><td> Instruction SLB misses </td><td> 0</td><td>	Group 58 pm_tlb_slb</td>

</tr>

<tr><td>PM_DSLB_MISS_GRP58</td><td> Data SLB misses </td><td> 1</td><td>	Group 58 pm_tlb_slb</td>

</tr>

<tr><td>PM_TLB_REF_GRP58</td><td> TLB reference </td><td> 2</td><td>	Group 58 pm_tlb_slb</td>

</tr>

<tr><td>PM_ITLB_REF_GRP58</td><td> Instruction TLB reference </td><td> 3</td><td>	Group 58 pm_tlb_slb</td>

</tr>

<tr><td>PM_ISLB_MISS_GRP59</td><td> Instruction SLB misses </td><td> 0</td><td>	Group 59 pm_slb_miss</td>

</tr>

<tr><td>PM_DSLB_MISS_GRP59</td><td> Data SLB misses </td><td> 1</td><td>	Group 59 pm_slb_miss</td>

</tr>

<tr><td>PM_IERAT_MISS_GRP59</td><td> IERAT miss count </td><td> 2</td><td>	Group 59 pm_slb_miss</td>

</tr>

<tr><td>PM_SLB_MISS_GRP59</td><td> SLB misses </td><td> 3</td><td>	Group 59 pm_slb_miss</td>

</tr>

<tr><td>PM_LSU_REJECT_L2_CORR_GRP60</td><td> LSU reject due to L2 correctable error </td><td> 0</td><td>	Group 60 pm_rejects</td>

</tr>

<tr><td>PM_LSU_REJECT_DERAT_MPRED_GRP60</td><td> LSU reject due to mispredicted DERAT </td><td> 1</td><td>	Group 60 pm_rejects</td>

</tr>

<tr><td>PM_LSU_REJECT_FAST_GRP60</td><td> LSU fast reject </td><td> 2</td><td>	Group 60 pm_rejects</td>

</tr>

<tr><td>PM_LSU_REJECT_GRP60</td><td> LSU reject </td><td> 3</td><td>	Group 60 pm_rejects</td>

</tr>

<tr><td>PM_LSU_REJECT_LHS_GRP61</td><td> Load hit store reject </td><td> 0</td><td>	Group 61 pm_rejects2</td>

</tr>

<tr><td>PM_LSU_REJECT_LHS_BOTH_GRP61</td><td> Load hit store reject both units </td><td> 1</td><td>	Group 61 pm_rejects2</td>

</tr>

<tr><td>PM_LSU_REJECT_EXTERN_GRP61</td><td> LSU external reject request  </td><td> 2</td><td>	Group 61 pm_rejects2</td>

</tr>

<tr><td>PM_LSU_REJECT_STEAL_GRP61</td><td> LSU reject due to steal </td><td> 3</td><td>	Group 61 pm_rejects2</td>

</tr>

<tr><td>PM_LSU_REJECT_STQ_FULL_GRP62</td><td> LSU reject due to store queue full </td><td> 0</td><td>	Group 62 pm_rejects3</td>

</tr>

<tr><td>PM_LSU_REJECT_SLOW_GRP62</td><td> LSU slow reject </td><td> 1</td><td>	Group 62 pm_rejects3</td>

</tr>

<tr><td>PM_LSU_REJECT_NO_SCRATCH_GRP62</td><td> LSU reject due to scratch register not available </td><td> 2</td><td>	Group 62 pm_rejects3</td>

</tr>

<tr><td>PM_LSU_REJECT_PARTIAL_SECTOR_GRP62</td><td> LSU reject due to partial sector valid </td><td> 3</td><td>	Group 62 pm_rejects3</td>

</tr>

<tr><td>PM_LSU_REJECT_UST_BOTH_GRP63</td><td> Unaligned store reject both units </td><td> 0</td><td>	Group 63 pm_rejects4</td>

</tr>

<tr><td>PM_LSU_REJECT_UST_GRP63</td><td> Unaligned store reject </td><td> 1</td><td>	Group 63 pm_rejects4</td>

</tr>

<tr><td>PM_LSU0_REJECT_UST_GRP63</td><td> LSU0 unaligned store reject </td><td> 2</td><td>	Group 63 pm_rejects4</td>

</tr>

<tr><td>PM_LSU1_REJECT_UST_GRP63</td><td> LSU1 unaligned store reject </td><td> 3</td><td>	Group 63 pm_rejects4</td>

</tr>

<tr><td>PM_LSU_REJECT_ULD_GRP64</td><td> Unaligned load reject </td><td> 0</td><td>	Group 64 pm_rejects5</td>

</tr>

<tr><td>PM_LSU_REJECT_ULD_BOTH_GRP64</td><td> Unaligned load reject both units </td><td> 1</td><td>	Group 64 pm_rejects5</td>

</tr>

<tr><td>PM_LSU0_REJECT_ULD_GRP64</td><td> LSU0 unaligned load reject </td><td> 2</td><td>	Group 64 pm_rejects5</td>

</tr>

<tr><td>PM_LSU1_REJECT_ULD_GRP64</td><td> LSU1 unaligned load reject </td><td> 3</td><td>	Group 64 pm_rejects5</td>

</tr>

<tr><td>PM_LSU0_REJECT_SET_MPRED_GRP65</td><td> LSU0 reject due to mispredicted set </td><td> 0</td><td>	Group 65 pm_rejects6</td>

</tr>

<tr><td>PM_LSU1_REJECT_SET_MPRED_GRP65</td><td> LSU1 reject due to mispredicted set </td><td> 1</td><td>	Group 65 pm_rejects6</td>

</tr>

<tr><td>PM_LSU_REJECT_SET_MPRED_GRP65</td><td> LSU reject due to mispredicted set </td><td> 2</td><td>	Group 65 pm_rejects6</td>

</tr>

<tr><td>PM_LSU_SRQ_EMPTY_CYC_GRP65</td><td> Cycles SRQ empty </td><td> 3</td><td>	Group 65 pm_rejects6</td>

</tr>

<tr><td>PM_LSU0_REJECT_ULD_GRP66</td><td> LSU0 unaligned load reject </td><td> 0</td><td>	Group 66 pm_rejects_unit</td>

</tr>

<tr><td>PM_LSU1_REJECT_UST_GRP66</td><td> LSU1 unaligned store reject </td><td> 1</td><td>	Group 66 pm_rejects_unit</td>

</tr>

<tr><td>PM_LSU0_REJECT_UST_GRP66</td><td> LSU0 unaligned store reject </td><td> 2</td><td>	Group 66 pm_rejects_unit</td>

</tr>

<tr><td>PM_LSU1_REJECT_ULD_GRP66</td><td> LSU1 unaligned load reject </td><td> 3</td><td>	Group 66 pm_rejects_unit</td>

</tr>

<tr><td>PM_LSU0_REJECT_GRP67</td><td> LSU0 reject </td><td> 0</td><td>	Group 67 pm_rejects_unit2</td>

</tr>

<tr><td>PM_LSU0_REJECT_DERAT_MPRED_GRP67</td><td> LSU0 reject due to mispredicted DERAT </td><td> 1</td><td>	Group 67 pm_rejects_unit2</td>

</tr>

<tr><td>PM_LSU1_REJECT_GRP67</td><td> LSU1 reject </td><td> 2</td><td>	Group 67 pm_rejects_unit2</td>

</tr>

<tr><td>PM_LSU1_REJECT_NO_SCRATCH_GRP67</td><td> LSU1 reject due to scratch register not available </td><td> 3</td><td>	Group 67 pm_rejects_unit2</td>

</tr>

<tr><td>PM_LSU0_REJECT_EXTERN_GRP68</td><td> LSU0 external reject request  </td><td> 0</td><td>	Group 68 pm_rejects_unit3</td>

</tr>

<tr><td>PM_LSU0_REJECT_L2_CORR_GRP68</td><td> LSU0 reject due to L2 correctable error </td><td> 1</td><td>	Group 68 pm_rejects_unit3</td>

</tr>

<tr><td>PM_LSU1_REJECT_EXTERN_GRP68</td><td> LSU1 external reject request  </td><td> 2</td><td>	Group 68 pm_rejects_unit3</td>

</tr>

<tr><td>PM_LSU1_REJECT_L2_CORR_GRP68</td><td> LSU1 reject due to L2 correctable error </td><td> 3</td><td>	Group 68 pm_rejects_unit3</td>

</tr>

<tr><td>PM_LSU0_REJECT_NO_SCRATCH_GRP69</td><td> LSU0 reject due to scratch register not available </td><td> 0</td><td>	Group 69 pm_rejects_unit4</td>

</tr>

<tr><td>PM_LSU0_REJECT_PARTIAL_SECTOR_GRP69</td><td> LSU0 reject due to partial sector valid </td><td> 1</td><td>	Group 69 pm_rejects_unit4</td>

</tr>

<tr><td>PM_LSU1_REJECT_NO_SCRATCH_GRP69</td><td> LSU1 reject due to scratch register not available </td><td> 2</td><td>	Group 69 pm_rejects_unit4</td>

</tr>

<tr><td>PM_LSU1_REJECT_PARTIAL_SECTOR_GRP69</td><td> LSU1 reject due to partial sector valid </td><td> 3</td><td>	Group 69 pm_rejects_unit4</td>

</tr>

<tr><td>PM_LSU0_REJECT_LHS_GRP70</td><td> LSU0 load hit store reject </td><td> 0</td><td>	Group 70 pm_rejects_unit5</td>

</tr>

<tr><td>PM_LSU0_DERAT_MISS_GRP70</td><td> LSU0 DERAT misses </td><td> 1</td><td>	Group 70 pm_rejects_unit5</td>

</tr>

<tr><td>PM_LSU1_REJECT_LHS_GRP70</td><td> LSU1 load hit store reject </td><td> 2</td><td>	Group 70 pm_rejects_unit5</td>

</tr>

<tr><td>PM_LSU1_DERAT_MISS_GRP70</td><td> LSU1 DERAT misses </td><td> 3</td><td>	Group 70 pm_rejects_unit5</td>

</tr>

<tr><td>PM_LSU0_REJECT_STQ_FULL_GRP71</td><td> LSU0 reject due to store queue full </td><td> 0</td><td>	Group 71 pm_rejects_unit6</td>

</tr>

<tr><td>PM_LSU0_REJECT_GRP71</td><td> LSU0 reject </td><td> 1</td><td>	Group 71 pm_rejects_unit6</td>

</tr>

<tr><td>PM_LSU1_REJECT_STQ_FULL_GRP71</td><td> LSU1 reject due to store queue full </td><td> 2</td><td>	Group 71 pm_rejects_unit6</td>

</tr>

<tr><td>PM_LSU1_REJECT_GRP71</td><td> LSU1 reject </td><td> 3</td><td>	Group 71 pm_rejects_unit6</td>

</tr>

<tr><td>PM_LSU0_REJECT_DERAT_MPRED_GRP72</td><td> LSU0 reject due to mispredicted DERAT </td><td> 0</td><td>	Group 72 pm_rejects_unit7</td>

</tr>

<tr><td>PM_LSU0_DERAT_MISS_GRP72</td><td> LSU0 DERAT misses </td><td> 1</td><td>	Group 72 pm_rejects_unit7</td>

</tr>

<tr><td>PM_LSU1_REJECT_DERAT_MPRED_GRP72</td><td> LSU1 reject due to mispredicted DERAT </td><td> 2</td><td>	Group 72 pm_rejects_unit7</td>

</tr>

<tr><td>PM_LSU1_DERAT_MISS_GRP72</td><td> LSU1 DERAT misses </td><td> 3</td><td>	Group 72 pm_rejects_unit7</td>

</tr>

<tr><td>PM_LSU_LDF_BOTH_GRP73</td><td> Both LSU units executed Floating Point load instruction </td><td> 0</td><td>	Group 73 pm_ldf</td>

</tr>

<tr><td>PM_LSU_LDF_GRP73</td><td> LSU executed Floating Point load instruction </td><td> 1</td><td>	Group 73 pm_ldf</td>

</tr>

<tr><td>PM_LSU0_LDF_GRP73</td><td> LSU0 executed Floating Point load instruction </td><td> 2</td><td>	Group 73 pm_ldf</td>

</tr>

<tr><td>PM_LSU1_LDF_GRP73</td><td> LSU1 executed Floating Point load instruction </td><td> 3</td><td>	Group 73 pm_ldf</td>

</tr>

<tr><td>PM_LSU0_NCLD_GRP74</td><td> LSU0 non-cacheable loads </td><td> 0</td><td>	Group 74 pm_lsu_misc</td>

</tr>

<tr><td>PM_LSU0_NCST_GRP74</td><td> LSU0 non-cachable stores </td><td> 1</td><td>	Group 74 pm_lsu_misc</td>

</tr>

<tr><td>PM_LSU_ST_CHAINED_GRP74</td><td> number of chained stores </td><td> 2</td><td>	Group 74 pm_lsu_misc</td>

</tr>

<tr><td>PM_LSU_BOTH_BUS_GRP74</td><td> Both data return buses busy simultaneously </td><td> 3</td><td>	Group 74 pm_lsu_misc</td>

</tr>

<tr><td>PM_LSU_LMQ_FULL_CYC_GRP75</td><td> Cycles LMQ full </td><td> 0</td><td>	Group 75 pm_lsu_lmq</td>

</tr>

<tr><td>PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP75</td><td> Cycles LMQ and SRQ empty </td><td> 1</td><td>	Group 75 pm_lsu_lmq</td>

</tr>

<tr><td>PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC_GRP75</td><td> Cycles both threads LMQ and SRQ empty </td><td> 2</td><td>	Group 75 pm_lsu_lmq</td>

</tr>

<tr><td>PM_LSU0_REJECT_L2MISS_GRP75</td><td> LSU0 L2 miss reject </td><td> 3</td><td>	Group 75 pm_lsu_lmq</td>

</tr>

<tr><td>PM_LSU_DERAT_MISS_CYC_GRP76</td><td> DERAT miss latency </td><td> 0</td><td>	Group 76 pm_lsu_flush_derat_miss</td>

</tr>

<tr><td>PM_LSU_DERAT_MISS_GRP76</td><td> DERAT misses </td><td> 1</td><td>	Group 76 pm_lsu_flush_derat_miss</td>

</tr>

<tr><td>PM_LSU_FLUSH_ALIGN_GRP76</td><td> Flush caused by alignement exception </td><td> 2</td><td>	Group 76 pm_lsu_flush_derat_miss</td>

</tr>

<tr><td>PM_LSU_FLUSH_DSI_GRP76</td><td> Flush caused by DSI </td><td> 3</td><td>	Group 76 pm_lsu_flush_derat_miss</td>

</tr>

<tr><td>PM_INST_DISP_LLA_GRP77</td><td> Instruction dispatched under load look ahead </td><td> 0</td><td>	Group 77 pm_lla</td>

</tr>

<tr><td>PM_DPU_HELD_LLA_END_GRP77</td><td> DISP unit held due to load look ahead ended </td><td> 1</td><td>	Group 77 pm_lla</td>

</tr>

<tr><td>PM_INST_DISP_GRP77</td><td> Instructions dispatched </td><td> 2</td><td>	Group 77 pm_lla</td>

</tr>

<tr><td>PM_THRD_LLA_BOTH_CYC_GRP77</td><td> Both threads in Load Look Ahead </td><td> 3</td><td>	Group 77 pm_lla</td>

</tr>

<tr><td>PM_GCT_NOSLOT_CYC_GRP78</td><td> Cycles no GCT slot allocated </td><td> 0</td><td>	Group 78 pm_gct</td>

</tr>

<tr><td>PM_GCT_EMPTY_CYC_GRP78</td><td> Cycles GCT empty </td><td> 1</td><td>	Group 78 pm_gct</td>

</tr>

<tr><td>PM_GCT_FULL_CYC_GRP78</td><td> Cycles GCT full </td><td> 2</td><td>	Group 78 pm_gct</td>

</tr>

<tr><td>PM_INST_FETCH_CYC_GRP78</td><td> Cycles at least 1 instruction fetched </td><td> 3</td><td>	Group 78 pm_gct</td>

</tr>

<tr><td>PM_THRD_PRIO_0_CYC_GRP79</td><td> Cycles thread running at priority level 0 </td><td> 0</td><td>	Group 79 pm_smt_priorities</td>

</tr>

<tr><td>PM_THRD_PRIO_1_CYC_GRP79</td><td> Cycles thread running at priority level 1 </td><td> 1</td><td>	Group 79 pm_smt_priorities</td>

</tr>

<tr><td>PM_THRD_PRIO_2_CYC_GRP79</td><td> Cycles thread running at priority level 2 </td><td> 2</td><td>	Group 79 pm_smt_priorities</td>

</tr>

<tr><td>PM_THRD_PRIO_3_CYC_GRP79</td><td> Cycles thread running at priority level 3 </td><td> 3</td><td>	Group 79 pm_smt_priorities</td>

</tr>

<tr><td>PM_THRD_PRIO_7_CYC_GRP80</td><td> Cycles thread running at priority level 7 </td><td> 0</td><td>	Group 80 pm_smt_priorities2</td>

</tr>

<tr><td>PM_THRD_PRIO_6_CYC_GRP80</td><td> Cycles thread running at priority level 6 </td><td> 1</td><td>	Group 80 pm_smt_priorities2</td>

</tr>

<tr><td>PM_THRD_PRIO_5_CYC_GRP80</td><td> Cycles thread running at priority level 5 </td><td> 2</td><td>	Group 80 pm_smt_priorities2</td>

</tr>

<tr><td>PM_THRD_PRIO_4_CYC_GRP80</td><td> Cycles thread running at priority level 4 </td><td> 3</td><td>	Group 80 pm_smt_priorities2</td>

</tr>

<tr><td>PM_THRD_PRIO_DIFF_0_CYC_GRP81</td><td> Cycles no thread priority difference </td><td> 0</td><td>	Group 81 pm_smt_priorities3</td>

</tr>

<tr><td>PM_THRD_PRIO_DIFF_1or2_CYC_GRP81</td><td> Cycles thread priority difference is 1 or 2 </td><td> 1</td><td>	Group 81 pm_smt_priorities3</td>

</tr>

<tr><td>PM_THRD_PRIO_DIFF_3or4_CYC_GRP81</td><td> Cycles thread priority difference is 3 or 4 </td><td> 2</td><td>	Group 81 pm_smt_priorities3</td>

</tr>

<tr><td>PM_THRD_PRIO_DIFF_5or6_CYC_GRP81</td><td> Cycles thread priority difference is 5 or 6 </td><td> 3</td><td>	Group 81 pm_smt_priorities3</td>

</tr>

<tr><td>PM_THRD_SEL_T0_GRP82</td><td> Decode selected thread 0 </td><td> 0</td><td>	Group 82 pm_smt_priorities4</td>

</tr>

<tr><td>PM_THRD_PRIO_DIFF_minus1or2_CYC_GRP82</td><td> Cycles thread priority difference is -1 or -2 </td><td> 1</td><td>	Group 82 pm_smt_priorities4</td>

</tr>

<tr><td>PM_THRD_PRIO_DIFF_minus3or4_CYC_GRP82</td><td> Cycles thread priority difference is -3 or -4 </td><td> 2</td><td>	Group 82 pm_smt_priorities4</td>

</tr>

<tr><td>PM_THRD_PRIO_DIFF_minus5or6_CYC_GRP82</td><td> Cycles thread priority difference is -5 or -6 </td><td> 3</td><td>	Group 82 pm_smt_priorities4</td>

</tr>

<tr><td>PM_FXU_IDLE_GRP83</td><td> FXU idle </td><td> 0</td><td>	Group 83 pm_fxu</td>

</tr>

<tr><td>PM_FXU_BUSY_GRP83</td><td> FXU busy </td><td> 1</td><td>	Group 83 pm_fxu</td>

</tr>

<tr><td>PM_FXU0_BUSY_FXU1_IDLE_GRP83</td><td> FXU0 busy FXU1 idle </td><td> 2</td><td>	Group 83 pm_fxu</td>

</tr>

<tr><td>PM_FXU1_BUSY_FXU0_IDLE_GRP83</td><td> FXU1 busy FXU0 idle </td><td> 3</td><td>	Group 83 pm_fxu</td>

</tr>

<tr><td>PM_FXU_PIPELINED_MULT_DIV_GRP84</td><td> Fix point multiply/divide pipelined </td><td> 0</td><td>	Group 84 pm_fxu2</td>

</tr>

<tr><td>PM_IFU_FIN_GRP84</td><td> IFU finished an instruction </td><td> 1</td><td>	Group 84 pm_fxu2</td>

</tr>

<tr><td>PM_FXU0_FIN_GRP84</td><td> FXU0 produced a result </td><td> 2</td><td>	Group 84 pm_fxu2</td>

</tr>

<tr><td>PM_FXU1_FIN_GRP84</td><td> FXU1 produced a result </td><td> 3</td><td>	Group 84 pm_fxu2</td>

</tr>

<tr><td>PM_VMX_COMPLEX_ISUED_GRP85</td><td> VMX instruction issued to complex </td><td> 0</td><td>	Group 85 pm_vmx</td>

</tr>

<tr><td>PM_VMX_FLOAT_ISSUED_GRP85</td><td> VMX instruction issued to float </td><td> 1</td><td>	Group 85 pm_vmx</td>

</tr>

<tr><td>PM_VMX_SIMPLE_ISSUED_GRP85</td><td> VMX instruction issued to simple </td><td> 2</td><td>	Group 85 pm_vmx</td>

</tr>

<tr><td>PM_VMX_PERMUTE_ISSUED_GRP85</td><td> VMX instruction issued to permute </td><td> 3</td><td>	Group 85 pm_vmx</td>

</tr>

<tr><td>PM_VMX0_INST_ISSUED_GRP86</td><td> VMX0 instruction issued </td><td> 0</td><td>	Group 86 pm_vmx2</td>

</tr>

<tr><td>PM_VMX1_INST_ISSUED_GRP86</td><td> VMX1 instruction issued </td><td> 1</td><td>	Group 86 pm_vmx2</td>

</tr>

<tr><td>PM_VMX0_LD_ISSUED_GRP86</td><td> VMX0 load issued </td><td> 2</td><td>	Group 86 pm_vmx2</td>

</tr>

<tr><td>PM_VMX1_LD_ISSUED_GRP86</td><td> VMX1 load issued </td><td> 3</td><td>	Group 86 pm_vmx2</td>

</tr>

<tr><td>PM_VMX0_LD_ISSUED_GRP87</td><td> VMX0 load issued </td><td> 0</td><td>	Group 87 pm_vmx3</td>

</tr>

<tr><td>PM_VMX0_LD_WRBACK_GRP87</td><td> VMX0 load writeback valid </td><td> 1</td><td>	Group 87 pm_vmx3</td>

</tr>

<tr><td>PM_VMX1_LD_ISSUED_GRP87</td><td> VMX1 load issued </td><td> 2</td><td>	Group 87 pm_vmx3</td>

</tr>

<tr><td>PM_VMX1_LD_WRBACK_GRP87</td><td> VMX1 load writeback valid </td><td> 3</td><td>	Group 87 pm_vmx3</td>

</tr>

<tr><td>PM_VMX_FLOAT_MULTICYCLE_GRP88</td><td> VMX multi-cycle floating point instruction issued </td><td> 0</td><td>	Group 88 pm_vmx4</td>

</tr>

<tr><td>PM_VMX_RESULT_SAT_0_1_GRP88</td><td> VMX valid result with sat bit is set (0->1) </td><td> 1</td><td>	Group 88 pm_vmx4</td>

</tr>

<tr><td>PM_VMX_RESULT_SAT_1_GRP88</td><td> VMX valid result with sat=1 </td><td> 2</td><td>	Group 88 pm_vmx4</td>

</tr>

<tr><td>PM_VMX_ST_ISSUED_GRP88</td><td> VMX store issued </td><td> 3</td><td>	Group 88 pm_vmx4</td>

</tr>

<tr><td>PM_VMX_ST_ISSUED_GRP89</td><td> VMX store issued </td><td> 0</td><td>	Group 89 pm_vmx5</td>

</tr>

<tr><td>PM_VMX0_STALL_GRP89</td><td> VMX0 stall </td><td> 1</td><td>	Group 89 pm_vmx5</td>

</tr>

<tr><td>PM_VMX1_STALL_GRP89</td><td> VMX1 stall </td><td> 2</td><td>	Group 89 pm_vmx5</td>

</tr>

<tr><td>PM_VMX_FLOAT_MULTICYCLE_GRP89</td><td> VMX multi-cycle floating point instruction issued </td><td> 3</td><td>	Group 89 pm_vmx5</td>

</tr>

<tr><td>PM_DFU_ADD_GRP90</td><td> DFU add type instruction </td><td> 0</td><td>	Group 90 pm_dfu</td>

</tr>

<tr><td>PM_DFU_ADD_SHIFTED_BOTH_GRP90</td><td> DFU add type with both operands shifted </td><td> 1</td><td>	Group 90 pm_dfu</td>

</tr>

<tr><td>PM_DFU_BACK2BACK_GRP90</td><td> DFU back to back operations executed </td><td> 2</td><td>	Group 90 pm_dfu</td>

</tr>

<tr><td>PM_DFU_CONV_GRP90</td><td> DFU convert from fixed op </td><td> 3</td><td>	Group 90 pm_dfu</td>

</tr>

<tr><td>PM_DFU_ENC_BCD_DPD_GRP91</td><td> DFU Encode BCD to DPD </td><td> 0</td><td>	Group 91 pm_dfu2</td>

</tr>

<tr><td>PM_DFU_EXP_EQ_GRP91</td><td> DFU operand exponents are equal for add type </td><td> 1</td><td>	Group 91 pm_dfu2</td>

</tr>

<tr><td>PM_DFU_FIN_GRP91</td><td> DFU instruction finish </td><td> 2</td><td>	Group 91 pm_dfu2</td>

</tr>

<tr><td>PM_DFU_SUBNORM_GRP91</td><td> DFU result is a subnormal </td><td> 3</td><td>	Group 91 pm_dfu2</td>

</tr>

<tr><td>PM_FAB_CMD_ISSUED_GRP92</td><td> Fabric command issued </td><td> 0</td><td>	Group 92 pm_fab</td>

</tr>

<tr><td>PM_FAB_CMD_RETRIED_GRP92</td><td> Fabric command retried </td><td> 1</td><td>	Group 92 pm_fab</td>

</tr>

<tr><td>PM_FAB_DCLAIM_GRP92</td><td> Dclaim operation, locally mastered </td><td> 2</td><td>	Group 92 pm_fab</td>

</tr>

<tr><td>PM_FAB_DMA_GRP92</td><td> DMA operation, locally mastered </td><td> 3</td><td>	Group 92 pm_fab</td>

</tr>

<tr><td>PM_FAB_NODE_PUMP_GRP93</td><td> Node pump operation, locally mastered </td><td> 0</td><td>	Group 93 pm_fab2</td>

</tr>

<tr><td>PM_FAB_RETRY_NODE_PUMP_GRP93</td><td> Retry of a node pump, locally mastered </td><td> 1</td><td>	Group 93 pm_fab2</td>

</tr>

<tr><td>PM_FAB_RETRY_SYS_PUMP_GRP93</td><td> Retry of a system pump, locally mastered  </td><td> 2</td><td>	Group 93 pm_fab2</td>

</tr>

<tr><td>PM_FAB_SYS_PUMP_GRP93</td><td> System pump operation, locally mastered </td><td> 3</td><td>	Group 93 pm_fab2</td>

</tr>

<tr><td>PM_FAB_CMD_ISSUED_GRP94</td><td> Fabric command issued </td><td> 0</td><td>	Group 94 pm_fab3</td>

</tr>

<tr><td>PM_FAB_CMD_RETRIED_GRP94</td><td> Fabric command retried </td><td> 1</td><td>	Group 94 pm_fab3</td>

</tr>

<tr><td>PM_FAB_ADDR_COLLISION_GRP94</td><td> local node launch collision with off-node address  </td><td> 2</td><td>	Group 94 pm_fab3</td>

</tr>

<tr><td>PM_FAB_MMIO_GRP94</td><td> MMIO operation, locally mastered </td><td> 3</td><td>	Group 94 pm_fab3</td>

</tr>

<tr><td>PM_MEM_DP_RQ_GLOB_LOC_GRP95</td><td> Memory read queue marking cache line double pump state from global to local </td><td> 0</td><td>	Group 95 pm_mem_dblpump</td>

</tr>

<tr><td>PM_MEM_DP_RQ_LOC_GLOB_GRP95</td><td> Memory read queue marking cache line double pump state from local to global </td><td> 1</td><td>	Group 95 pm_mem_dblpump</td>

</tr>

<tr><td>PM_MEM_DP_CL_WR_GLOB_GRP95</td><td> cache line write setting double pump state to global </td><td> 2</td><td>	Group 95 pm_mem_dblpump</td>

</tr>

<tr><td>PM_MEM_DP_CL_WR_LOC_GRP95</td><td> cache line write setting double pump state to local </td><td> 3</td><td>	Group 95 pm_mem_dblpump</td>

</tr>

<tr><td>PM_MEM0_DP_RQ_GLOB_LOC_GRP96</td><td> Memory read queue marking cache line double pump state from global to local side 0 </td><td> 0</td><td>	Group 96 pm_mem0_dblpump</td>

</tr>

<tr><td>PM_MEM0_DP_RQ_LOC_GLOB_GRP96</td><td> Memory read queue marking cache line double pump state from local to global side 0 </td><td> 1</td><td>	Group 96 pm_mem0_dblpump</td>

</tr>

<tr><td>PM_MEM0_DP_CL_WR_GLOB_GRP96</td><td> cacheline write setting dp to global side 0 </td><td> 2</td><td>	Group 96 pm_mem0_dblpump</td>

</tr>

<tr><td>PM_MEM0_DP_CL_WR_LOC_GRP96</td><td> cacheline write setting dp to local side 0 </td><td> 3</td><td>	Group 96 pm_mem0_dblpump</td>

</tr>

<tr><td>PM_MEM1_DP_RQ_GLOB_LOC_GRP97</td><td> Memory read queue marking cache line double pump state from global to local side 1 </td><td> 0</td><td>	Group 97 pm_mem1_dblpump</td>

</tr>

<tr><td>PM_MEM1_DP_RQ_LOC_GLOB_GRP97</td><td> Memory read queue marking cache line double pump state from local to global side 1 </td><td> 1</td><td>	Group 97 pm_mem1_dblpump</td>

</tr>

<tr><td>PM_MEM1_DP_CL_WR_GLOB_GRP97</td><td> cacheline write setting dp to global side 1 </td><td> 2</td><td>	Group 97 pm_mem1_dblpump</td>

</tr>

<tr><td>PM_MEM1_DP_CL_WR_LOC_GRP97</td><td> cacheline write setting dp to local side 1 </td><td> 3</td><td>	Group 97 pm_mem1_dblpump</td>

</tr>

<tr><td>PM_GXO_CYC_BUSY_GRP98</td><td> Outbound GX bus utilizations (# of cycles in use) </td><td> 0</td><td>	Group 98 pm_gxo</td>

</tr>

<tr><td>PM_GXO_ADDR_CYC_BUSY_GRP98</td><td> Outbound GX address utilization (# of cycles address out is valid) </td><td> 1</td><td>	Group 98 pm_gxo</td>

</tr>

<tr><td>PM_GXO_DATA_CYC_BUSY_GRP98</td><td> Outbound GX Data utilization (# of cycles data out is valid) </td><td> 2</td><td>	Group 98 pm_gxo</td>

</tr>

<tr><td>PM_GXI_CYC_BUSY_GRP98</td><td> Inbound GX bus utilizations (# of cycles in use) </td><td> 3</td><td>	Group 98 pm_gxo</td>

</tr>

<tr><td>PM_GXI_CYC_BUSY_GRP99</td><td> Inbound GX bus utilizations (# of cycles in use) </td><td> 0</td><td>	Group 99 pm_gxi</td>

</tr>

<tr><td>PM_GXI_ADDR_CYC_BUSY_GRP99</td><td> Inbound GX address utilization (# of cycle address is in valid) </td><td> 1</td><td>	Group 99 pm_gxi</td>

</tr>

<tr><td>PM_GXI_DATA_CYC_BUSY_GRP99</td><td> Inbound GX Data utilization (# of cycle data in is valid) </td><td> 2</td><td>	Group 99 pm_gxi</td>

</tr>

<tr><td>PM_GXO_CYC_BUSY_GRP99</td><td> Outbound GX bus utilizations (# of cycles in use) </td><td> 3</td><td>	Group 99 pm_gxi</td>

</tr>

<tr><td>PM_GXO_CYC_BUSY_GRP100</td><td> Outbound GX bus utilizations (# of cycles in use) </td><td> 0</td><td>	Group 100 pm_gx_dma</td>

</tr>

<tr><td>PM_GXI_CYC_BUSY_GRP100</td><td> Inbound GX bus utilizations (# of cycles in use) </td><td> 1</td><td>	Group 100 pm_gx_dma</td>

</tr>

<tr><td>PM_GX_DMA_READ_GRP100</td><td> DMA Read Request </td><td> 2</td><td>	Group 100 pm_gx_dma</td>

</tr>

<tr><td>PM_GX_DMA_WRITE_GRP100</td><td> All DMA Write Requests (including dma wrt lgcy) </td><td> 3</td><td>	Group 100 pm_gx_dma</td>

</tr>

<tr><td>PM_INST_FROM_L1_GRP101</td><td> Instruction fetched from L1 </td><td> 0</td><td>	Group 101 pm_L1_misc</td>

</tr>

<tr><td>PM_L1_WRITE_CYC_GRP101</td><td> Cycles writing to instruction L1 </td><td> 1</td><td>	Group 101 pm_L1_misc</td>

</tr>

<tr><td>PM_NO_ITAG_CYC_GRP101</td><td> Cyles no ITAG available </td><td> 2</td><td>	Group 101 pm_L1_misc</td>

</tr>

<tr><td>PM_INST_IMC_MATCH_CMPL_GRP101</td><td> IMC matched instructions completed </td><td> 3</td><td>	Group 101 pm_L1_misc</td>

</tr>

<tr><td>PM_L2_LD_REQ_DATA_GRP102</td><td> L2 data load requests </td><td> 0</td><td>	Group 102 pm_L2_data</td>

</tr>

<tr><td>PM_L2_LD_MISS_DATA_GRP102</td><td> L2 data load misses </td><td> 1</td><td>	Group 102 pm_L2_data</td>

</tr>

<tr><td>PM_L2_ST_REQ_DATA_GRP102</td><td> L2 data store requests </td><td> 2</td><td>	Group 102 pm_L2_data</td>

</tr>

<tr><td>PM_L2_ST_MISS_DATA_GRP102</td><td> L2 data store misses </td><td> 3</td><td>	Group 102 pm_L2_data</td>

</tr>

<tr><td>PM_L2_LD_REQ_INST_GRP103</td><td> L2 instruction load requests </td><td> 0</td><td>	Group 103 pm_L2_ld_inst</td>

</tr>

<tr><td>PM_L2_LD_MISS_INST_GRP103</td><td> L2 instruction load misses </td><td> 1</td><td>	Group 103 pm_L2_ld_inst</td>

</tr>

<tr><td>PM_L2_MISS_GRP103</td><td> L2 cache misses </td><td> 2</td><td>	Group 103 pm_L2_ld_inst</td>

</tr>

<tr><td>PM_L2_PREF_LD_GRP103</td><td> L2 cache prefetches </td><td> 3</td><td>	Group 103 pm_L2_ld_inst</td>

</tr>

<tr><td>PM_L2_CASTOUT_MOD_GRP104</td><td> L2 castouts - Modified (M, Mu, Me) </td><td> 0</td><td>	Group 104 pm_L2_castout_invalidate</td>

</tr>

<tr><td>PM_L2_CASTOUT_SHR_GRP104</td><td> L2 castouts - Shared (T, Te, Si, S) </td><td> 1</td><td>	Group 104 pm_L2_castout_invalidate</td>

</tr>

<tr><td>PM_IC_INV_L2_GRP104</td><td> L1 I cache entries invalidated from L2 </td><td> 2</td><td>	Group 104 pm_L2_castout_invalidate</td>

</tr>

<tr><td>PM_DC_INV_L2_GRP104</td><td> L1 D cache entries invalidated from L2 </td><td> 3</td><td>	Group 104 pm_L2_castout_invalidate</td>

</tr>

<tr><td>PM_LD_REQ_L2_GRP105</td><td> L2 load requests  </td><td> 0</td><td>	Group 105 pm_L2_ldst_reqhit</td>

</tr>

<tr><td>PM_LD_HIT_L2_GRP105</td><td> L2 D cache load hits </td><td> 1</td><td>	Group 105 pm_L2_ldst_reqhit</td>

</tr>

<tr><td>PM_ST_REQ_L2_GRP105</td><td> L2 store requests </td><td> 2</td><td>	Group 105 pm_L2_ldst_reqhit</td>

</tr>

<tr><td>PM_ST_HIT_L2_GRP105</td><td> L2 D cache store hits </td><td> 3</td><td>	Group 105 pm_L2_ldst_reqhit</td>

</tr>

<tr><td>PM_L2SA_LD_REQ_DATA_GRP106</td><td> L2 slice A data load requests </td><td> 0</td><td>	Group 106 pm_L2_ld_data_slice</td>

</tr>

<tr><td>PM_L2SA_LD_MISS_DATA_GRP106</td><td> L2 slice A data load misses </td><td> 1</td><td>	Group 106 pm_L2_ld_data_slice</td>

</tr>

<tr><td>PM_L2SB_LD_REQ_DATA_GRP106</td><td> L2 slice B data load requests </td><td> 2</td><td>	Group 106 pm_L2_ld_data_slice</td>

</tr>

<tr><td>PM_L2SB_LD_MISS_DATA_GRP106</td><td> L2 slice B data load misses </td><td> 3</td><td>	Group 106 pm_L2_ld_data_slice</td>

</tr>

<tr><td>PM_L2SA_LD_REQ_INST_GRP107</td><td> L2 slice A instruction load requests </td><td> 0</td><td>	Group 107 pm_L2_ld_inst_slice</td>

</tr>

<tr><td>PM_L2SA_LD_MISS_INST_GRP107</td><td> L2 slice A instruction load misses </td><td> 1</td><td>	Group 107 pm_L2_ld_inst_slice</td>

</tr>

<tr><td>PM_L2SB_LD_REQ_INST_GRP107</td><td> L2 slice B instruction load requests </td><td> 2</td><td>	Group 107 pm_L2_ld_inst_slice</td>

</tr>

<tr><td>PM_L2SB_LD_MISS_INST_GRP107</td><td> L2 slice B instruction load misses </td><td> 3</td><td>	Group 107 pm_L2_ld_inst_slice</td>

</tr>

<tr><td>PM_L2SA_ST_REQ_GRP108</td><td> L2 slice A store requests </td><td> 0</td><td>	Group 108 pm_L2_st_slice</td>

</tr>

<tr><td>PM_L2SA_ST_MISS_GRP108</td><td> L2 slice A store misses </td><td> 1</td><td>	Group 108 pm_L2_st_slice</td>

</tr>

<tr><td>PM_L2SB_ST_REQ_GRP108</td><td> L2 slice B store requests </td><td> 2</td><td>	Group 108 pm_L2_st_slice</td>

</tr>

<tr><td>PM_L2SB_ST_MISS_GRP108</td><td> L2 slice B store misses </td><td> 3</td><td>	Group 108 pm_L2_st_slice</td>

</tr>

<tr><td>PM_L2SA_MISS_GRP109</td><td> L2 slice A misses </td><td> 0</td><td>	Group 109 pm_L2miss_slice</td>

</tr>

<tr><td>PM_L2_MISS_GRP109</td><td> L2 cache misses </td><td> 1</td><td>	Group 109 pm_L2miss_slice</td>

</tr>

<tr><td>PM_DATA_FROM_L2MISS_GRP109</td><td> Data loaded missed L2 </td><td> 2</td><td>	Group 109 pm_L2miss_slice</td>

</tr>

<tr><td>PM_L2SB_MISS_GRP109</td><td> L2 slice B misses </td><td> 3</td><td>	Group 109 pm_L2miss_slice</td>

</tr>

<tr><td>PM_L2SA_CASTOUT_MOD_GRP110</td><td> L2 slice A castouts - Modified </td><td> 0</td><td>	Group 110 pm_L2_castout_slice</td>

</tr>

<tr><td>PM_L2SA_CASTOUT_SHR_GRP110</td><td> L2 slice A castouts - Shared </td><td> 1</td><td>	Group 110 pm_L2_castout_slice</td>

</tr>

<tr><td>PM_L2SB_CASTOUT_MOD_GRP110</td><td> L2 slice B castouts - Modified </td><td> 2</td><td>	Group 110 pm_L2_castout_slice</td>

</tr>

<tr><td>PM_L2SB_CASTOUT_SHR_GRP110</td><td> L2 slice B castouts - Shared </td><td> 3</td><td>	Group 110 pm_L2_castout_slice</td>

</tr>

<tr><td>PM_L2SA_IC_INV_GRP111</td><td> L2 slice A I cache invalidate </td><td> 0</td><td>	Group 111 pm_L2_invalidate_slice</td>

</tr>

<tr><td>PM_L2SA_DC_INV_GRP111</td><td> L2 slice A D cache invalidate </td><td> 1</td><td>	Group 111 pm_L2_invalidate_slice</td>

</tr>

<tr><td>PM_L2SB_IC_INV_GRP111</td><td> L2 slice B I cache invalidate </td><td> 2</td><td>	Group 111 pm_L2_invalidate_slice</td>

</tr>

<tr><td>PM_L2SB_DC_INV_GRP111</td><td> L2 slice B D cache invalidate </td><td> 3</td><td>	Group 111 pm_L2_invalidate_slice</td>

</tr>

<tr><td>PM_L2SA_LD_REQ_GRP112</td><td> L2 slice A load requests  </td><td> 0</td><td>	Group 112 pm_L2_ld_reqhit_slice</td>

</tr>

<tr><td>PM_L2SA_LD_HIT_GRP112</td><td> L2 slice A load hits </td><td> 1</td><td>	Group 112 pm_L2_ld_reqhit_slice</td>

</tr>

<tr><td>PM_L2SB_LD_REQ_GRP112</td><td> L2 slice B load requests  </td><td> 2</td><td>	Group 112 pm_L2_ld_reqhit_slice</td>

</tr>

<tr><td>PM_L2SB_LD_HIT_GRP112</td><td> L2 slice B load hits </td><td> 3</td><td>	Group 112 pm_L2_ld_reqhit_slice</td>

</tr>

<tr><td>PM_L2SA_ST_REQ_GRP113</td><td> L2 slice A store requests </td><td> 0</td><td>	Group 113 pm_L2_st_reqhit_slice</td>

</tr>

<tr><td>PM_L2SA_ST_HIT_GRP113</td><td> L2 slice A store hits </td><td> 1</td><td>	Group 113 pm_L2_st_reqhit_slice</td>

</tr>

<tr><td>PM_L2SB_ST_REQ_GRP113</td><td> L2 slice B store requests </td><td> 2</td><td>	Group 113 pm_L2_st_reqhit_slice</td>

</tr>

<tr><td>PM_L2SB_ST_HIT_GRP113</td><td> L2 slice B store hits </td><td> 3</td><td>	Group 113 pm_L2_st_reqhit_slice</td>

</tr>

<tr><td>PM_IC_DEMAND_L2_BHT_REDIRECT_GRP114</td><td> L2 I cache demand request due to BHT redirect </td><td> 0</td><td>	Group 114 pm_L2_redir_pref</td>

</tr>

<tr><td>PM_IC_DEMAND_L2_BR_REDIRECT_GRP114</td><td> L2 I cache demand request due to branch redirect </td><td> 1</td><td>	Group 114 pm_L2_redir_pref</td>

</tr>

<tr><td>PM_L2_PREF_ST_GRP114</td><td> L2 cache prefetches </td><td> 2</td><td>	Group 114 pm_L2_redir_pref</td>

</tr>

<tr><td>PM_L2_PREF_LD_GRP114</td><td> L2 cache prefetches </td><td> 3</td><td>	Group 114 pm_L2_redir_pref</td>

</tr>

<tr><td>PM_L3SA_REF_GRP115</td><td> L3 slice A references </td><td> 0</td><td>	Group 115 pm_L3_SliceA</td>

</tr>

<tr><td>PM_L3SA_HIT_GRP115</td><td> L3 slice A hits </td><td> 1</td><td>	Group 115 pm_L3_SliceA</td>

</tr>

<tr><td>PM_DATA_FROM_L3_GRP115</td><td> Data loaded from L3 </td><td> 2</td><td>	Group 115 pm_L3_SliceA</td>

</tr>

<tr><td>PM_L3SA_MISS_GRP115</td><td> L3 slice A misses </td><td> 3</td><td>	Group 115 pm_L3_SliceA</td>

</tr>

<tr><td>PM_L3SB_REF_GRP116</td><td> L3 slice B references </td><td> 0</td><td>	Group 116 pm_L3_SliceB</td>

</tr>

<tr><td>PM_L3SB_HIT_GRP116</td><td> L3 slice B hits </td><td> 1</td><td>	Group 116 pm_L3_SliceB</td>

</tr>

<tr><td>PM_DATA_FROM_L3_GRP116</td><td> Data loaded from L3 </td><td> 2</td><td>	Group 116 pm_L3_SliceB</td>

</tr>

<tr><td>PM_L3SB_MISS_GRP116</td><td> L3 slice B misses </td><td> 3</td><td>	Group 116 pm_L3_SliceB</td>

</tr>

<tr><td>PM_FPU_ISSUE_0_GRP117</td><td> FPU issue 0 per cycle </td><td> 0</td><td>	Group 117 pm_fpu_issue</td>

</tr>

<tr><td>PM_FPU_ISSUE_1_GRP117</td><td> FPU issue 1 per cycle </td><td> 1</td><td>	Group 117 pm_fpu_issue</td>

</tr>

<tr><td>PM_FPU_ISSUE_2_GRP117</td><td> FPU issue 2 per cycle </td><td> 2</td><td>	Group 117 pm_fpu_issue</td>

</tr>

<tr><td>PM_FPU_ISSUE_STEERING_GRP117</td><td> FPU issue steering </td><td> 3</td><td>	Group 117 pm_fpu_issue</td>

</tr>

<tr><td>PM_FPU_ISSUE_OOO_GRP118</td><td> FPU issue out-of-order </td><td> 0</td><td>	Group 118 pm_fpu_issue2</td>

</tr>

<tr><td>PM_FPU_ISSUE_ST_FOLDED_GRP118</td><td> FPU issue a folded store </td><td> 1</td><td>	Group 118 pm_fpu_issue2</td>

</tr>

<tr><td>PM_FPU_ISSUE_DIV_SQRT_OVERLAP_GRP118</td><td> FPU divide/sqrt overlapped with other divide/sqrt </td><td> 2</td><td>	Group 118 pm_fpu_issue2</td>

</tr>

<tr><td>PM_FPU_ISSUE_STALL_ST_GRP118</td><td> FPU issue stalled due to store </td><td> 3</td><td>	Group 118 pm_fpu_issue2</td>

</tr>

<tr><td>PM_FPU_ISSUE_STALL_THRD_GRP119</td><td> FPU issue stalled due to thread resource conflict </td><td> 0</td><td>	Group 119 pm_fpu_issue3</td>

</tr>

<tr><td>PM_FPU_ISSUE_STALL_FPR_GRP119</td><td> FPU issue stalled due to FPR dependencies </td><td> 1</td><td>	Group 119 pm_fpu_issue3</td>

</tr>

<tr><td>PM_FPU_ISSUE_DIV_SQRT_OVERLAP_GRP119</td><td> FPU divide/sqrt overlapped with other divide/sqrt </td><td> 2</td><td>	Group 119 pm_fpu_issue3</td>

</tr>

<tr><td>PM_FPU_ISSUE_STALL_ST_GRP119</td><td> FPU issue stalled due to store </td><td> 3</td><td>	Group 119 pm_fpu_issue3</td>

</tr>

<tr><td>PM_FPU0_1FLOP_GRP120</td><td> FPU0 executed add, mult, sub, cmp or sel instruction </td><td> 0</td><td>	Group 120 pm_fpu0_flop</td>

</tr>

<tr><td>PM_FPU0_FMA_GRP120</td><td> FPU0 executed multiply-add instruction </td><td> 1</td><td>	Group 120 pm_fpu0_flop</td>

</tr>

<tr><td>PM_FPU0_FSQRT_FDIV_GRP120</td><td> FPU0 executed FSQRT or FDIV instruction </td><td> 2</td><td>	Group 120 pm_fpu0_flop</td>

</tr>

<tr><td>PM_FPU0_STF_GRP120</td><td> FPU0 executed store instruction </td><td> 3</td><td>	Group 120 pm_fpu0_flop</td>

</tr>

<tr><td>PM_FPU0_FLOP_GRP121</td><td> FPU0 executed 1FLOP, FMA, FSQRT or FDIV instruction </td><td> 0</td><td>	Group 121 pm_fpu0_misc</td>

</tr>

<tr><td>PM_FPU0_FXDIV_GRP121</td><td> FPU0 executed fixed point division </td><td> 1</td><td>	Group 121 pm_fpu0_misc</td>

</tr>

<tr><td>PM_FPU0_DENORM_GRP121</td><td> FPU0 received denormalized data </td><td> 2</td><td>	Group 121 pm_fpu0_misc</td>

</tr>

<tr><td>PM_FPU0_SINGLE_GRP121</td><td> FPU0 executed single precision instruction </td><td> 3</td><td>	Group 121 pm_fpu0_misc</td>

</tr>

<tr><td>PM_FPU0_FIN_GRP122</td><td> FPU0 produced a result </td><td> 0</td><td>	Group 122 pm_fpu0_misc2</td>

</tr>

<tr><td>PM_FPU0_FEST_GRP122</td><td> FPU0 executed FEST instruction </td><td> 1</td><td>	Group 122 pm_fpu0_misc2</td>

</tr>

<tr><td>PM_FPU0_FPSCR_GRP122</td><td> FPU0 executed FPSCR instruction </td><td> 2</td><td>	Group 122 pm_fpu0_misc2</td>

</tr>

<tr><td>PM_FPU0_FXMULT_GRP122</td><td> FPU0 executed fixed point multiplication </td><td> 3</td><td>	Group 122 pm_fpu0_misc2</td>

</tr>

<tr><td>PM_FPU0_FCONV_GRP123</td><td> FPU0 executed FCONV instruction </td><td> 0</td><td>	Group 123 pm_fpu0_misc3</td>

</tr>

<tr><td>PM_FPU0_FRSP_GRP123</td><td> FPU0 executed FRSP instruction </td><td> 1</td><td>	Group 123 pm_fpu0_misc3</td>

</tr>

<tr><td>PM_FPU0_ST_FOLDED_GRP123</td><td> FPU0 folded store </td><td> 2</td><td>	Group 123 pm_fpu0_misc3</td>

</tr>

<tr><td>PM_FPU0_FEST_GRP123</td><td> FPU0 executed FEST instruction </td><td> 3</td><td>	Group 123 pm_fpu0_misc3</td>

</tr>

<tr><td>PM_FPU1_1FLOP_GRP124</td><td> FPU1 executed add, mult, sub, cmp or sel instruction </td><td> 0</td><td>	Group 124 pm_fpu1_flop</td>

</tr>

<tr><td>PM_FPU1_FMA_GRP124</td><td> FPU1 executed multiply-add instruction </td><td> 1</td><td>	Group 124 pm_fpu1_flop</td>

</tr>

<tr><td>PM_FPU1_FSQRT_FDIV_GRP124</td><td> FPU1 executed FSQRT or FDIV instruction </td><td> 2</td><td>	Group 124 pm_fpu1_flop</td>

</tr>

<tr><td>PM_FPU1_STF_GRP124</td><td> FPU1 executed store instruction </td><td> 3</td><td>	Group 124 pm_fpu1_flop</td>

</tr>

<tr><td>PM_FPU1_FLOP_GRP125</td><td> FPU1 executed 1FLOP, FMA, FSQRT or FDIV instruction </td><td> 0</td><td>	Group 125 pm_fpu1_misc</td>

</tr>

<tr><td>PM_FPU1_FXDIV_GRP125</td><td> FPU1 executed fixed point division </td><td> 1</td><td>	Group 125 pm_fpu1_misc</td>

</tr>

<tr><td>PM_FPU1_DENORM_GRP125</td><td> FPU1 received denormalized data </td><td> 2</td><td>	Group 125 pm_fpu1_misc</td>

</tr>

<tr><td>PM_FPU1_SINGLE_GRP125</td><td> FPU1 executed single precision instruction </td><td> 3</td><td>	Group 125 pm_fpu1_misc</td>

</tr>

<tr><td>PM_FPU1_FIN_GRP126</td><td> FPU1 produced a result </td><td> 0</td><td>	Group 126 pm_fpu1_misc2</td>

</tr>

<tr><td>PM_FPU1_FEST_GRP126</td><td> FPU1 executed FEST instruction </td><td> 1</td><td>	Group 126 pm_fpu1_misc2</td>

</tr>

<tr><td>PM_FPU1_FPSCR_GRP126</td><td> FPU1 executed FPSCR instruction </td><td> 2</td><td>	Group 126 pm_fpu1_misc2</td>

</tr>

<tr><td>PM_FPU1_FXMULT_GRP126</td><td> FPU1 executed fixed point multiplication </td><td> 3</td><td>	Group 126 pm_fpu1_misc2</td>

</tr>

<tr><td>PM_FPU1_FCONV_GRP127</td><td> FPU1 executed FCONV instruction </td><td> 0</td><td>	Group 127 pm_fpu1_misc3</td>

</tr>

<tr><td>PM_FPU1_FRSP_GRP127</td><td> FPU1 executed FRSP instruction </td><td> 1</td><td>	Group 127 pm_fpu1_misc3</td>

</tr>

<tr><td>PM_FPU1_ST_FOLDED_GRP127</td><td> FPU1 folded store </td><td> 2</td><td>	Group 127 pm_fpu1_misc3</td>

</tr>

<tr><td>PM_FPU1_FEST_GRP127</td><td> FPU1 executed FEST instruction </td><td> 3</td><td>	Group 127 pm_fpu1_misc3</td>

</tr>

<tr><td>PM_FPU_1FLOP_GRP128</td><td> FPU executed one flop instruction  </td><td> 0</td><td>	Group 128 pm_fpu_flop</td>

</tr>

<tr><td>PM_FPU_FMA_GRP128</td><td> FPU executed multiply-add instruction </td><td> 1</td><td>	Group 128 pm_fpu_flop</td>

</tr>

<tr><td>PM_FPU_FSQRT_FDIV_GRP128</td><td> FPU executed FSQRT or FDIV instruction </td><td> 2</td><td>	Group 128 pm_fpu_flop</td>

</tr>

<tr><td>PM_FPU_FLOP_GRP128</td><td> FPU executed 1FLOP, FMA, FSQRT or FDIV instruction </td><td> 3</td><td>	Group 128 pm_fpu_flop</td>

</tr>

<tr><td>PM_FPU_FIN_GRP129</td><td> FPU produced a result </td><td> 0</td><td>	Group 129 pm_fpu_misc</td>

</tr>

<tr><td>PM_FPU_FRSP_GRP129</td><td> FPU executed FRSP instruction </td><td> 1</td><td>	Group 129 pm_fpu_misc</td>

</tr>

<tr><td>PM_FPU_FPSCR_GRP129</td><td> FPU executed FPSCR instruction </td><td> 2</td><td>	Group 129 pm_fpu_misc</td>

</tr>

<tr><td>PM_FPU_FXMULT_GRP129</td><td> FPU executed fixed point multiplication </td><td> 3</td><td>	Group 129 pm_fpu_misc</td>

</tr>

<tr><td>PM_FPU_FXDIV_GRP130</td><td> FPU executed fixed point division </td><td> 0</td><td>	Group 130 pm_fpu_misc2</td>

</tr>

<tr><td>PM_FPU_DENORM_GRP130</td><td> FPU received denormalized data </td><td> 1</td><td>	Group 130 pm_fpu_misc2</td>

</tr>

<tr><td>PM_FPU_STF_GRP130</td><td> FPU executed store instruction </td><td> 2</td><td>	Group 130 pm_fpu_misc2</td>

</tr>

<tr><td>PM_FPU_SINGLE_GRP130</td><td> FPU executed single precision instruction </td><td> 3</td><td>	Group 130 pm_fpu_misc2</td>

</tr>

<tr><td>PM_FPU_FCONV_GRP131</td><td> FPU executed FCONV instruction </td><td> 0</td><td>	Group 131 pm_fpu_misc3</td>

</tr>

<tr><td>PM_FPU_FRSP_GRP131</td><td> FPU executed FRSP instruction </td><td> 1</td><td>	Group 131 pm_fpu_misc3</td>

</tr>

<tr><td>PM_FPU_ST_FOLDED_GRP131</td><td> FPU folded store </td><td> 2</td><td>	Group 131 pm_fpu_misc3</td>

</tr>

<tr><td>PM_FPU_FEST_GRP131</td><td> FPU executed FEST instruction </td><td> 3</td><td>	Group 131 pm_fpu_misc3</td>

</tr>

<tr><td>PM_PURR_GRP132</td><td> PURR Event </td><td> 0</td><td>	Group 132 pm_purr</td>

</tr>

<tr><td>PM_RUN_CYC_GRP132</td><td> Run cycles </td><td> 1</td><td>	Group 132 pm_purr</td>

</tr>

<tr><td>PM_CYC_GRP132</td><td> Processor cycles </td><td> 2</td><td>	Group 132 pm_purr</td>

</tr>

<tr><td>PM_INST_CMPL_GRP132</td><td> Instructions completed </td><td> 3</td><td>	Group 132 pm_purr</td>

</tr>

<tr><td>PM_SUSPENDED_GRP133</td><td> Suspended </td><td> 0</td><td>	Group 133 pm_suspend</td>

</tr>

<tr><td>PM_CYC_GRP133</td><td> Processor cycles </td><td> 1</td><td>	Group 133 pm_suspend</td>

</tr>

<tr><td>PM_SYNC_CYC_GRP133</td><td> Sync duration </td><td> 2</td><td>	Group 133 pm_suspend</td>

</tr>

<tr><td>PM_INST_CMPL_GRP133</td><td> Instructions completed </td><td> 3</td><td>	Group 133 pm_suspend</td>

</tr>

<tr><td>PM_LD_MISS_L1_CYC_GRP134</td><td> L1 data load miss cycles </td><td> 0</td><td>	Group 134 pm_dcache</td>

</tr>

<tr><td>PM_LSU_DERAT_MISS_GRP134</td><td> DERAT misses </td><td> 1</td><td>	Group 134 pm_dcache</td>

</tr>

<tr><td>PM_LD_MISS_L1_GRP134</td><td> L1 D cache load misses </td><td> 2</td><td>	Group 134 pm_dcache</td>

</tr>

<tr><td>PM_LSU_DERAT_MISS_CYC_GRP134</td><td> DERAT miss latency </td><td> 3</td><td>	Group 134 pm_dcache</td>

</tr>

<tr><td>PM_DERAT_MISS_4K_GRP135</td><td> DERAT misses for 4K page </td><td> 0</td><td>	Group 135 pm_derat_miss</td>

</tr>

<tr><td>PM_DERAT_MISS_64K_GRP135</td><td> DERAT misses for 64K page </td><td> 1</td><td>	Group 135 pm_derat_miss</td>

</tr>

<tr><td>PM_DERAT_MISS_16M_GRP135</td><td> DERAT misses for 16M page </td><td> 2</td><td>	Group 135 pm_derat_miss</td>

</tr>

<tr><td>PM_DERAT_MISS_16G_GRP135</td><td> DERAT misses for 16G page </td><td> 3</td><td>	Group 135 pm_derat_miss</td>

</tr>

<tr><td>PM_DERAT_REF_4K_GRP136</td><td> DERAT reference for 4K page </td><td> 0</td><td>	Group 136 pm_derat_ref</td>

</tr>

<tr><td>PM_DERAT_REF_64K_GRP136</td><td> DERAT reference for 64K page </td><td> 1</td><td>	Group 136 pm_derat_ref</td>

</tr>

<tr><td>PM_DERAT_REF_16M_GRP136</td><td> DERAT reference for 16M page </td><td> 2</td><td>	Group 136 pm_derat_ref</td>

</tr>

<tr><td>PM_DERAT_REF_16G_GRP136</td><td> DERAT reference for 16G page </td><td> 3</td><td>	Group 136 pm_derat_ref</td>

</tr>

<tr><td>PM_IERAT_MISS_16G_GRP137</td><td> IERAT misses for 16G page </td><td> 0</td><td>	Group 137 pm_ierat_miss</td>

</tr>

<tr><td>PM_IERAT_MISS_16M_GRP137</td><td> IERAT misses for 16M page </td><td> 1</td><td>	Group 137 pm_ierat_miss</td>

</tr>

<tr><td>PM_IERAT_MISS_64K_GRP137</td><td> IERAT misses for 64K page </td><td> 2</td><td>	Group 137 pm_ierat_miss</td>

</tr>

<tr><td>PM_IERAT_MISS_4K_GRP137</td><td> IERAT misses for 4K page </td><td> 3</td><td>	Group 137 pm_ierat_miss</td>

</tr>

<tr><td>PM_MRK_BR_TAKEN_GRP138</td><td> Marked branch taken </td><td> 0</td><td>	Group 138 pm_mrk_br</td>

</tr>

<tr><td>PM_MRK_LD_MISS_L1_GRP138</td><td> Marked L1 D cache load misses </td><td> 1</td><td>	Group 138 pm_mrk_br</td>

</tr>

<tr><td>PM_MRK_BR_MPRED_GRP138</td><td> Marked branch mispredicted </td><td> 2</td><td>	Group 138 pm_mrk_br</td>

</tr>

<tr><td>PM_INST_CMPL_GRP138</td><td> Instructions completed </td><td> 3</td><td>	Group 138 pm_mrk_br</td>

</tr>

<tr><td>PM_INST_CMPL_GRP139</td><td> Instructions completed </td><td> 0</td><td>	Group 139 pm_mrk_dsource</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_DMEM_GRP139</td><td> Marked data loaded from distant memory </td><td> 1</td><td>	Group 139 pm_mrk_dsource</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_DL2L3_SHR_GRP139</td><td> Marked data loaded from distant L2 or L3 shared </td><td> 2</td><td>	Group 139 pm_mrk_dsource</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_DL2L3_MOD_GRP139</td><td> Marked data loaded from distant L2 or L3 modified </td><td> 3</td><td>	Group 139 pm_mrk_dsource</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L2_GRP140</td><td> Marked data loaded from L2 </td><td> 0</td><td>	Group 140 pm_mrk_dsource2</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L21_GRP140</td><td> Marked data loaded from private L2 other core </td><td> 1</td><td>	Group 140 pm_mrk_dsource2</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L25_MOD_GRP140</td><td> Marked data loaded from L2.5 modified </td><td> 2</td><td>	Group 140 pm_mrk_dsource2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP140</td><td> Instructions completed </td><td> 3</td><td>	Group 140 pm_mrk_dsource2</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L2MISS_GRP141</td><td> Marked data loaded missed L2 </td><td> 0</td><td>	Group 141 pm_mrk_dsource3</td>

</tr>

<tr><td>PM_INST_CMPL_GRP141</td><td> Instructions completed </td><td> 1</td><td>	Group 141 pm_mrk_dsource3</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L3_GRP141</td><td> Marked data loaded from L3 </td><td> 2</td><td>	Group 141 pm_mrk_dsource3</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L25_SHR_GRP141</td><td> Marked data loaded from L2.5 shared </td><td> 3</td><td>	Group 141 pm_mrk_dsource3</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L35_MOD_GRP142</td><td> Marked data loaded from L3.5 modified </td><td> 0</td><td>	Group 142 pm_mrk_dsource4</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L35_SHR_GRP142</td><td> Marked data loaded from L3.5 shared </td><td> 1</td><td>	Group 142 pm_mrk_dsource4</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L3MISS_GRP142</td><td> Marked data loaded from L3 miss </td><td> 2</td><td>	Group 142 pm_mrk_dsource4</td>

</tr>

<tr><td>PM_INST_CMPL_GRP142</td><td> Instructions completed </td><td> 3</td><td>	Group 142 pm_mrk_dsource4</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_MEM_DP_GRP143</td><td> Marked data loaded from double pump memory </td><td> 0</td><td>	Group 143 pm_mrk_dsource5</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_RL2L3_SHR_GRP143</td><td> Marked data loaded from remote L2 or L3 shared </td><td> 1</td><td>	Group 143 pm_mrk_dsource5</td>

</tr>

<tr><td>PM_INST_CMPL_GRP143</td><td> Instructions completed </td><td> 2</td><td>	Group 143 pm_mrk_dsource5</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_LMEM_GRP143</td><td> Marked data loaded from local memory </td><td> 3</td><td>	Group 143 pm_mrk_dsource5</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_RL2L3_MOD_GRP144</td><td> Marked data loaded from remote L2 or L3 modified </td><td> 0</td><td>	Group 144 pm_mrk_dsource6</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_RL2L3_SHR_GRP144</td><td> Marked data loaded from remote L2 or L3 shared </td><td> 1</td><td>	Group 144 pm_mrk_dsource6</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_RMEM_GRP144</td><td> Marked data loaded from remote memory </td><td> 2</td><td>	Group 144 pm_mrk_dsource6</td>

</tr>

<tr><td>PM_INST_CMPL_GRP144</td><td> Instructions completed </td><td> 3</td><td>	Group 144 pm_mrk_dsource6</td>

</tr>

<tr><td>PM_MRK_LSU_REJECT_ULD_GRP145</td><td> Marked unaligned load reject </td><td> 0</td><td>	Group 145 pm_mrk_rejects</td>

</tr>

<tr><td>PM_MRK_LSU_REJECT_UST_GRP145</td><td> Marked unaligned store reject </td><td> 1</td><td>	Group 145 pm_mrk_rejects</td>

</tr>

<tr><td>PM_INST_CMPL_GRP145</td><td> Instructions completed </td><td> 2</td><td>	Group 145 pm_mrk_rejects</td>

</tr>

<tr><td>PM_MRK_LSU_REJECT_LHS_GRP145</td><td> Marked load hit store reject </td><td> 3</td><td>	Group 145 pm_mrk_rejects</td>

</tr>

<tr><td>PM_MRK_LSU0_REJECT_LHS_GRP146</td><td> LSU0 marked load hit store reject </td><td> 0</td><td>	Group 146 pm_mrk_rejects2</td>

</tr>

<tr><td>PM_MRK_LSU0_REJECT_ULD_GRP146</td><td> LSU0 marked unaligned load reject </td><td> 1</td><td>	Group 146 pm_mrk_rejects2</td>

</tr>

<tr><td>PM_MRK_LSU0_REJECT_UST_GRP146</td><td> LSU0 marked unaligned store reject </td><td> 2</td><td>	Group 146 pm_mrk_rejects2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP146</td><td> Instructions completed </td><td> 3</td><td>	Group 146 pm_mrk_rejects2</td>

</tr>

<tr><td>PM_MRK_LSU1_REJECT_LHS_GRP147</td><td> LSU1 marked load hit store reject </td><td> 0</td><td>	Group 147 pm_mrk_rejects3</td>

</tr>

<tr><td>PM_MRK_LSU1_REJECT_ULD_GRP147</td><td> LSU1 marked unaligned load reject </td><td> 1</td><td>	Group 147 pm_mrk_rejects3</td>

</tr>

<tr><td>PM_MRK_LSU1_REJECT_UST_GRP147</td><td> LSU1 marked unaligned store reject </td><td> 2</td><td>	Group 147 pm_mrk_rejects3</td>

</tr>

<tr><td>PM_INST_CMPL_GRP147</td><td> Instructions completed </td><td> 3</td><td>	Group 147 pm_mrk_rejects3</td>

</tr>

<tr><td>PM_MRK_INST_ISSUED_GRP148</td><td> Marked instruction issued </td><td> 0</td><td>	Group 148 pm_mrk_inst</td>

</tr>

<tr><td>PM_MRK_INST_DISP_GRP148</td><td> Marked instruction dispatched </td><td> 1</td><td>	Group 148 pm_mrk_inst</td>

</tr>

<tr><td>PM_MRK_INST_FIN_GRP148</td><td> Marked instruction finished </td><td> 2</td><td>	Group 148 pm_mrk_inst</td>

</tr>

<tr><td>PM_INST_CMPL_GRP148</td><td> Instructions completed </td><td> 3</td><td>	Group 148 pm_mrk_inst</td>

</tr>

<tr><td>PM_MRK_FPU0_FIN_GRP149</td><td> Marked instruction FPU0 processing finished </td><td> 0</td><td>	Group 149 pm_mrk_fpu_fin</td>

</tr>

<tr><td>PM_MRK_FPU1_FIN_GRP149</td><td> Marked instruction FPU1 processing finished </td><td> 1</td><td>	Group 149 pm_mrk_fpu_fin</td>

</tr>

<tr><td>PM_MRK_FPU_FIN_GRP149</td><td> Marked instruction FPU processing finished </td><td> 2</td><td>	Group 149 pm_mrk_fpu_fin</td>

</tr>

<tr><td>PM_INST_CMPL_GRP149</td><td> Instructions completed </td><td> 3</td><td>	Group 149 pm_mrk_fpu_fin</td>

</tr>

<tr><td>PM_MRK_LSU_REJECT_ULD_GRP150</td><td> Marked unaligned load reject </td><td> 0</td><td>	Group 150 pm_mrk_misc</td>

</tr>

<tr><td>PM_MRK_FXU_FIN_GRP150</td><td> Marked instruction FXU processing finished </td><td> 1</td><td>	Group 150 pm_mrk_misc</td>

</tr>

<tr><td>PM_MRK_DFU_FIN_GRP150</td><td> DFU marked instruction finish </td><td> 2</td><td>	Group 150 pm_mrk_misc</td>

</tr>

<tr><td>PM_INST_CMPL_GRP150</td><td> Instructions completed </td><td> 3</td><td>	Group 150 pm_mrk_misc</td>

</tr>

<tr><td>PM_MRK_STCX_FAIL_GRP151</td><td> Marked STCX failed </td><td> 0</td><td>	Group 151 pm_mrk_misc2</td>

</tr>

<tr><td>PM_MRK_IFU_FIN_GRP151</td><td> Marked instruction IFU processing finished </td><td> 1</td><td>	Group 151 pm_mrk_misc2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP151</td><td> Instructions completed </td><td> 2</td><td>	Group 151 pm_mrk_misc2</td>

</tr>

<tr><td>PM_MRK_INST_TIMEO_GRP151</td><td> Marked Instruction finish timeout  </td><td> 3</td><td>	Group 151 pm_mrk_misc2</td>

</tr>

<tr><td>PM_MRK_VMX_ST_ISSUED_GRP152</td><td> Marked VMX store issued </td><td> 0</td><td>	Group 152 pm_mrk_misc3</td>

</tr>

<tr><td>PM_MRK_LSU0_REJECT_L2MISS_GRP152</td><td> LSU0 marked L2 miss reject </td><td> 1</td><td>	Group 152 pm_mrk_misc3</td>

</tr>

<tr><td>PM_INST_CMPL_GRP152</td><td> Instructions completed </td><td> 2</td><td>	Group 152 pm_mrk_misc3</td>

</tr>

<tr><td>PM_MRK_LSU_DERAT_MISS_GRP152</td><td> Marked DERAT miss </td><td> 3</td><td>	Group 152 pm_mrk_misc3</td>

</tr>

<tr><td>PM_CYC_GRP153</td><td> Processor cycles </td><td> 0</td><td>	Group 153 pm_mrk_misc4</td>

</tr>

<tr><td>PM_CYC_GRP153</td><td> Processor cycles </td><td> 1</td><td>	Group 153 pm_mrk_misc4</td>

</tr>

<tr><td>PM_INST_CMPL_GRP153</td><td> Instructions completed </td><td> 2</td><td>	Group 153 pm_mrk_misc4</td>

</tr>

<tr><td>PM_MRK_LSU_FIN_GRP153</td><td> Marked instruction LSU processing finished </td><td> 3</td><td>	Group 153 pm_mrk_misc4</td>

</tr>

<tr><td>PM_MRK_ST_CMPL_GRP154</td><td> Marked store instruction completed </td><td> 0</td><td>	Group 154 pm_mrk_st</td>

</tr>

<tr><td>PM_MRK_ST_GPS_GRP154</td><td> Marked store sent to GPS </td><td> 1</td><td>	Group 154 pm_mrk_st</td>

</tr>

<tr><td>PM_MRK_ST_CMPL_INT_GRP154</td><td> Marked store completed with intervention </td><td> 2</td><td>	Group 154 pm_mrk_st</td>

</tr>

<tr><td>PM_INST_CMPL_GRP154</td><td> Instructions completed </td><td> 3</td><td>	Group 154 pm_mrk_st</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_L2_GRP155</td><td> Marked PTEG loaded from L2.5 modified </td><td> 0</td><td>	Group 155 pm_mrk_pteg</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_DMEM_GRP155</td><td> Marked PTEG loaded from distant memory </td><td> 1</td><td>	Group 155 pm_mrk_pteg</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_DL2L3_SHR_GRP155</td><td> Marked PTEG loaded from distant L2 or L3 shared </td><td> 2</td><td>	Group 155 pm_mrk_pteg</td>

</tr>

<tr><td>PM_INST_CMPL_GRP155</td><td> Instructions completed </td><td> 3</td><td>	Group 155 pm_mrk_pteg</td>

</tr>

<tr><td>PM_INST_CMPL_GRP156</td><td> Instructions completed </td><td> 0</td><td>	Group 156 pm_mrk_pteg2</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_L21_GRP156</td><td> Marked PTEG loaded from private L2 other core </td><td> 1</td><td>	Group 156 pm_mrk_pteg2</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_L25_MOD_GRP156</td><td> Marked PTEG loaded from L2.5 modified </td><td> 2</td><td>	Group 156 pm_mrk_pteg2</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_DL2L3_MOD_GRP156</td><td> Marked PTEG loaded from distant L2 or L3 modified </td><td> 3</td><td>	Group 156 pm_mrk_pteg2</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_L35_MOD_GRP157</td><td> Marked PTEG loaded from L3.5 modified </td><td> 0</td><td>	Group 157 pm_mrk_pteg3</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_L35_SHR_GRP157</td><td> Marked PTEG loaded from L3.5 shared </td><td> 1</td><td>	Group 157 pm_mrk_pteg3</td>

</tr>

<tr><td>PM_INST_CMPL_GRP157</td><td> Instructions completed </td><td> 2</td><td>	Group 157 pm_mrk_pteg3</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_L25_SHR_GRP157</td><td> Marked PTEG loaded from L2.5 shared </td><td> 3</td><td>	Group 157 pm_mrk_pteg3</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_MEM_DP_GRP158</td><td> Marked PTEG loaded from double pump memory </td><td> 0</td><td>	Group 158 pm_mrk_pteg4</td>

</tr>

<tr><td>PM_INST_CMPL_GRP158</td><td> Instructions completed </td><td> 1</td><td>	Group 158 pm_mrk_pteg4</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_L3_GRP158</td><td> Marked PTEG loaded from L3 </td><td> 2</td><td>	Group 158 pm_mrk_pteg4</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_L2MISS_GRP158</td><td> Marked PTEG loaded from L2 miss </td><td> 3</td><td>	Group 158 pm_mrk_pteg4</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_RL2L3_MOD_GRP159</td><td> Marked PTEG loaded from remote L2 or L3 modified </td><td> 0</td><td>	Group 159 pm_mrk_pteg5</td>

</tr>

<tr><td>PM_INST_CMPL_GRP159</td><td> Instructions completed </td><td> 1</td><td>	Group 159 pm_mrk_pteg5</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_L3MISS_GRP159</td><td> Marked PTEG loaded from L3 miss </td><td> 2</td><td>	Group 159 pm_mrk_pteg5</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_LMEM_GRP159</td><td> Marked PTEG loaded from local memory </td><td> 3</td><td>	Group 159 pm_mrk_pteg5</td>

</tr>

<tr><td>PM_CYC_GRP160</td><td> Processor cycles </td><td> 0</td><td>	Group 160 pm_mrk_pteg6</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_RL2L3_SHR_GRP160</td><td> Marked PTEG loaded from remote L2 or L3 shared </td><td> 1</td><td>	Group 160 pm_mrk_pteg6</td>

</tr>

<tr><td>PM_MRK_PTEG_FROM_RMEM_GRP160</td><td> Marked PTEG loaded from remote memory </td><td> 2</td><td>	Group 160 pm_mrk_pteg6</td>

</tr>

<tr><td>PM_INST_CMPL_GRP160</td><td> Instructions completed </td><td> 3</td><td>	Group 160 pm_mrk_pteg6</td>

</tr>

<tr><td>PM_MRK_VMX_COMPLEX_ISSUED_GRP161</td><td> Marked VMX instruction issued to complex </td><td> 0</td><td>	Group 161 pm_mrk_vmx</td>

</tr>

<tr><td>PM_MRK_VMX_FLOAT_ISSUED_GRP161</td><td> Marked VMX instruction issued to float </td><td> 1</td><td>	Group 161 pm_mrk_vmx</td>

</tr>

<tr><td>PM_MRK_VMX_PERMUTE_ISSUED_GRP161</td><td> Marked VMX instruction issued to permute </td><td> 2</td><td>	Group 161 pm_mrk_vmx</td>

</tr>

<tr><td>PM_INST_CMPL_GRP161</td><td> Instructions completed </td><td> 3</td><td>	Group 161 pm_mrk_vmx</td>

</tr>

<tr><td>PM_MRK_VMX0_LD_WRBACK_GRP162</td><td> Marked VMX0 load writeback valid </td><td> 0</td><td>	Group 162 pm_mrk_vmx2</td>

</tr>

<tr><td>PM_MRK_VMX1_LD_WRBACK_GRP162</td><td> Marked VMX1 load writeback valid </td><td> 1</td><td>	Group 162 pm_mrk_vmx2</td>

</tr>

<tr><td>PM_MRK_DTLB_REF_GRP162</td><td> Marked Data TLB reference </td><td> 2</td><td>	Group 162 pm_mrk_vmx2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP162</td><td> Instructions completed </td><td> 3</td><td>	Group 162 pm_mrk_vmx2</td>

</tr>

<tr><td>PM_MRK_VMX_SIMPLE_ISSUED_GRP163</td><td> Marked VMX instruction issued to simple </td><td> 0</td><td>	Group 163 pm_mrk_vmx3</td>

</tr>

<tr><td>PM_VMX_SIMPLE_ISSUED_GRP163</td><td> VMX instruction issued to simple </td><td> 1</td><td>	Group 163 pm_mrk_vmx3</td>

</tr>

<tr><td>PM_CYC_GRP163</td><td> Processor cycles </td><td> 2</td><td>	Group 163 pm_mrk_vmx3</td>

</tr>

<tr><td>PM_INST_CMPL_GRP163</td><td> Instructions completed </td><td> 3</td><td>	Group 163 pm_mrk_vmx3</td>

</tr>

<tr><td>PM_MRK_FPU0_FIN_GRP164</td><td> Marked instruction FPU0 processing finished </td><td> 0</td><td>	Group 164 pm_mrk_fp</td>

</tr>

<tr><td>PM_MRK_FPU_FIN_GRP164</td><td> Marked instruction FPU processing finished </td><td> 1</td><td>	Group 164 pm_mrk_fp</td>

</tr>

<tr><td>PM_MRK_FPU1_FIN_GRP164</td><td> Marked instruction FPU1 processing finished </td><td> 2</td><td>	Group 164 pm_mrk_fp</td>

</tr>

<tr><td>PM_INST_CMPL_GRP164</td><td> Instructions completed </td><td> 3</td><td>	Group 164 pm_mrk_fp</td>

</tr>

<tr><td>PM_MRK_DERAT_REF_64K_GRP165</td><td> Marked DERAT reference for 64K page </td><td> 0</td><td>	Group 165 pm_mrk_derat_ref</td>

</tr>

<tr><td>PM_MRK_DERAT_REF_4K_GRP165</td><td> Marked DERAT reference for 4K page </td><td> 1</td><td>	Group 165 pm_mrk_derat_ref</td>

</tr>

<tr><td>PM_MRK_DERAT_REF_16M_GRP165</td><td> Marked DERAT reference for 16M page </td><td> 2</td><td>	Group 165 pm_mrk_derat_ref</td>

</tr>

<tr><td>PM_INST_CMPL_GRP165</td><td> Instructions completed </td><td> 3</td><td>	Group 165 pm_mrk_derat_ref</td>

</tr>

<tr><td>PM_MRK_DERAT_MISS_64K_GRP166</td><td> Marked DERAT misses for 64K page </td><td> 0</td><td>	Group 166 pm_mrk_derat_miss</td>

</tr>

<tr><td>PM_MRK_DERAT_MISS_4K_GRP166</td><td> Marked DERAT misses for 4K page </td><td> 1</td><td>	Group 166 pm_mrk_derat_miss</td>

</tr>

<tr><td>PM_MRK_DERAT_MISS_16M_GRP166</td><td> Marked DERAT misses for 16M page </td><td> 2</td><td>	Group 166 pm_mrk_derat_miss</td>

</tr>

<tr><td>PM_INST_CMPL_GRP166</td><td> Instructions completed </td><td> 3</td><td>	Group 166 pm_mrk_derat_miss</td>

</tr>

<tr><td>PM_LD_MISS_L1_GRP167</td><td> L1 D cache load misses </td><td> 0</td><td>	Group 167 pm_dcache_edge</td>

</tr>

<tr><td>PM_LSU_DERAT_MISS_GRP167</td><td> DERAT misses </td><td> 1</td><td>	Group 167 pm_dcache_edge</td>

</tr>

<tr><td>PM_LD_MISS_L1_GRP167</td><td> L1 D cache load misses </td><td> 2</td><td>	Group 167 pm_dcache_edge</td>

</tr>

<tr><td>PM_LSU_DERAT_MISS_GRP167</td><td> DERAT misses </td><td> 3</td><td>	Group 167 pm_dcache_edge</td>

</tr>

<tr><td>PM_LSU_LMQ_FULL_CYC_GRP168</td><td> Cycles LMQ full </td><td> 0</td><td>	Group 168 pm_lsu_lmq_edge</td>

</tr>

<tr><td>PM_LSU_LMQ_SRQ_EMPTY_COUNT_GRP168</td><td> Periods LMQ and SRQ empty </td><td> 1</td><td>	Group 168 pm_lsu_lmq_edge</td>

</tr>

<tr><td>PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT_GRP168</td><td> Periods both threads LMQ and SRQ empty </td><td> 2</td><td>	Group 168 pm_lsu_lmq_edge</td>

</tr>

<tr><td>PM_LSU0_REJECT_L2MISS_GRP168</td><td> LSU0 L2 miss reject </td><td> 3</td><td>	Group 168 pm_lsu_lmq_edge</td>

</tr>

<tr><td>PM_GCT_NOSLOT_COUNT_GRP169</td><td> Periods no GCT slot allocated </td><td> 0</td><td>	Group 169 pm_gct_edge</td>

</tr>

<tr><td>PM_GCT_EMPTY_COUNT_GRP169</td><td> Periods GCT empty </td><td> 1</td><td>	Group 169 pm_gct_edge</td>

</tr>

<tr><td>PM_GCT_FULL_COUNT_GRP169</td><td> Periods GCT full </td><td> 2</td><td>	Group 169 pm_gct_edge</td>

</tr>

<tr><td>PM_INST_FETCH_CYC_GRP169</td><td> Cycles at least 1 instruction fetched </td><td> 3</td><td>	Group 169 pm_gct_edge</td>

</tr>

<tr><td>PM_DPU_HELD_THERMAL_COUNT_GRP170</td><td> Periods DISP unit held due to thermal condition </td><td> 0</td><td>	Group 170 pm_freq_edge</td>

</tr>

<tr><td>PM_DPU_HELD_POWER_COUNT_GRP170</td><td> Periods DISP unit held due to Power Management </td><td> 1</td><td>	Group 170 pm_freq_edge</td>

</tr>

<tr><td>PM_FREQ_DOWN_GRP170</td><td> Frequency is being slewed down due to Power Management </td><td> 2</td><td>	Group 170 pm_freq_edge</td>

</tr>

<tr><td>PM_FREQ_UP_GRP170</td><td> Frequency is being slewed up due to Power Management </td><td> 3</td><td>	Group 170 pm_freq_edge</td>

</tr>

<tr><td>PM_L1_ICACHE_MISS_GRP171</td><td> L1 I cache miss count </td><td> 0</td><td>	Group 171 pm_disp_wait_edge</td>

</tr>

<tr><td>PM_DPU_WT_IC_MISS_COUNT_GRP171</td><td> Periods DISP unit is stalled due to I cache miss </td><td> 1</td><td>	Group 171 pm_disp_wait_edge</td>

</tr>

<tr><td>PM_DPU_WT_COUNT_GRP171</td><td> Periods DISP unit is stalled waiting for instructions </td><td> 2</td><td>	Group 171 pm_disp_wait_edge</td>

</tr>

<tr><td>PM_DPU_WT_BR_MPRED_COUNT_GRP171</td><td> Periods DISP unit is stalled due to branch misprediction </td><td> 3</td><td>	Group 171 pm_disp_wait_edge</td>

</tr>

<tr><td>PM_LD_MISS_L1_GRP172</td><td> L1 D cache load misses </td><td> 0</td><td>	Group 172 pm_edge1</td>

</tr>

<tr><td>PM_DPU_WT_IC_MISS_GRP172</td><td> Cycles DISP unit is stalled due to I cache miss </td><td> 1</td><td>	Group 172 pm_edge1</td>

</tr>

<tr><td>PM_LLA_COUNT_GRP172</td><td> Transitions into Load Look Ahead mode </td><td> 2</td><td>	Group 172 pm_edge1</td>

</tr>

<tr><td>PM_LLA_CYC_GRP172</td><td> Load Look Ahead Active </td><td> 3</td><td>	Group 172 pm_edge1</td>

</tr>

<tr><td>PM_0INST_FETCH_COUNT_GRP173</td><td> Periods with no instructions fetched </td><td> 0</td><td>	Group 173 pm_edge2</td>

</tr>

<tr><td>PM_0INST_FETCH_GRP173</td><td> No instructions fetched </td><td> 1</td><td>	Group 173 pm_edge2</td>

</tr>

<tr><td>PM_IBUF_FULL_COUNT_GRP173</td><td> Periods instruction buffer full </td><td> 2</td><td>	Group 173 pm_edge2</td>

</tr>

<tr><td>PM_IBUF_FULL_CYC_GRP173</td><td> Cycles instruction buffer full </td><td> 3</td><td>	Group 173 pm_edge2</td>

</tr>

<tr><td>PM_RUN_COUNT_GRP174</td><td> Run Periods </td><td> 0</td><td>	Group 174 pm_edge3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP174</td><td> Run cycles </td><td> 1</td><td>	Group 174 pm_edge3</td>

</tr>

<tr><td>PM_INST_TABLEWALK_COUNT_GRP174</td><td> Periods doing instruction tablewalks </td><td> 2</td><td>	Group 174 pm_edge3</td>

</tr>

<tr><td>PM_INST_TABLEWALK_CYC_GRP174</td><td> Cycles doing instruction tablewalks </td><td> 3</td><td>	Group 174 pm_edge3</td>

</tr>

<tr><td>PM_GCT_FULL_COUNT_GRP175</td><td> Periods GCT full </td><td> 0</td><td>	Group 175 pm_edge4</td>

</tr>

<tr><td>PM_GCT_FULL_CYC_GRP175</td><td> Cycles GCT full </td><td> 1</td><td>	Group 175 pm_edge4</td>

</tr>

<tr><td>PM_NO_ITAG_COUNT_GRP175</td><td> Periods no ITAG available </td><td> 2</td><td>	Group 175 pm_edge4</td>

</tr>

<tr><td>PM_NO_ITAG_CYC_GRP175</td><td> Cyles no ITAG available </td><td> 3</td><td>	Group 175 pm_edge4</td>

</tr>

<tr><td>PM_THRD_ONE_RUN_COUNT_GRP176</td><td> Periods one of the threads in run cycles </td><td> 0</td><td>	Group 176 pm_edge5</td>

</tr>

<tr><td>PM_HV_COUNT_GRP176</td><td> Hypervisor Periods </td><td> 1</td><td>	Group 176 pm_edge5</td>

</tr>

<tr><td>PM_SYNC_COUNT_GRP176</td><td> SYNC instructions completed </td><td> 2</td><td>	Group 176 pm_edge5</td>

</tr>

<tr><td>PM_SYNC_CYC_GRP176</td><td> Sync duration </td><td> 3</td><td>	Group 176 pm_edge5</td>

</tr>

<tr><td>PM_THRD_ONE_RUN_CYC_GRP177</td><td> One of the threads in run cycles </td><td> 0</td><td>	Group 177 pm_noedge5</td>

</tr>

<tr><td>PM_HV_CYC_GRP177</td><td> Hypervisor Cycles </td><td> 1</td><td>	Group 177 pm_noedge5</td>

</tr>

<tr><td>PM_SYNC_COUNT_GRP177</td><td> SYNC instructions completed </td><td> 2</td><td>	Group 177 pm_noedge5</td>

</tr>

<tr><td>PM_SYNC_CYC_GRP177</td><td> Sync duration </td><td> 3</td><td>	Group 177 pm_noedge5</td>

</tr>

<tr><td>PM_DPU_HELD_THERMAL_COUNT_GRP178</td><td> Periods DISP unit held due to thermal condition </td><td> 0</td><td>	Group 178 pm_edge6</td>

</tr>

<tr><td>PM_DPU_HELD_COUNT_GRP178</td><td> Periods DISP unit held </td><td> 1</td><td>	Group 178 pm_edge6</td>

</tr>

<tr><td>PM_DPU_WT_COUNT_GRP178</td><td> Periods DISP unit is stalled waiting for instructions </td><td> 2</td><td>	Group 178 pm_edge6</td>

</tr>

<tr><td>PM_DPU_WT_BR_MPRED_COUNT_GRP178</td><td> Periods DISP unit is stalled due to branch misprediction </td><td> 3</td><td>	Group 178 pm_edge6</td>

</tr>

<tr><td>PM_DPU_HELD_THERMAL_GRP179</td><td> DISP unit held due to thermal condition </td><td> 0</td><td>	Group 179 pm_noedge6</td>

</tr>

<tr><td>PM_DPU_HELD_GRP179</td><td> DISP unit held </td><td> 1</td><td>	Group 179 pm_noedge6</td>

</tr>

<tr><td>PM_DPU_WT_GRP179</td><td> Cycles DISP unit is stalled waiting for instructions </td><td> 2</td><td>	Group 179 pm_noedge6</td>

</tr>

<tr><td>PM_DPU_WT_BR_MPRED_GRP179</td><td> Cycles DISP unit is stalled due to branch misprediction </td><td> 3</td><td>	Group 179 pm_noedge6</td>

</tr>

<tr><td>PM_GCT_NOSLOT_COUNT_GRP180</td><td> Periods no GCT slot allocated </td><td> 0</td><td>	Group 180 pm_edge7</td>

</tr>

<tr><td>PM_GCT_EMPTY_COUNT_GRP180</td><td> Periods GCT empty </td><td> 1</td><td>	Group 180 pm_edge7</td>

</tr>

<tr><td>PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT_GRP180</td><td> Periods both threads LMQ and SRQ empty </td><td> 2</td><td>	Group 180 pm_edge7</td>

</tr>

<tr><td>PM_LSU_SRQ_EMPTY_COUNT_GRP180</td><td> Periods SRQ empty </td><td> 3</td><td>	Group 180 pm_edge7</td>

</tr>

<tr><td>PM_GCT_NOSLOT_CYC_GRP181</td><td> Cycles no GCT slot allocated </td><td> 0</td><td>	Group 181 pm_noedge7</td>

</tr>

<tr><td>PM_GCT_EMPTY_CYC_GRP181</td><td> Cycles GCT empty </td><td> 1</td><td>	Group 181 pm_noedge7</td>

</tr>

<tr><td>PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC_GRP181</td><td> Cycles both threads LMQ and SRQ empty </td><td> 2</td><td>	Group 181 pm_noedge7</td>

</tr>

<tr><td>PM_LSU_SRQ_EMPTY_CYC_GRP181</td><td> Cycles SRQ empty </td><td> 3</td><td>	Group 181 pm_noedge7</td>

</tr>

<tr><td>PM_SYNC_COUNT_GRP182</td><td> SYNC instructions completed </td><td> 0</td><td>	Group 182 pm_edge8</td>

</tr>

<tr><td>PM_LSU_LMQ_SRQ_EMPTY_COUNT_GRP182</td><td> Periods LMQ and SRQ empty </td><td> 1</td><td>	Group 182 pm_edge8</td>

</tr>

<tr><td>PM_SYNC_CYC_GRP182</td><td> Sync duration </td><td> 2</td><td>	Group 182 pm_edge8</td>

</tr>

<tr><td>PM_LSU_DERAT_MISS_GRP182</td><td> DERAT misses </td><td> 3</td><td>	Group 182 pm_edge8</td>

</tr>

<tr><td>PM_SYNC_CYC_GRP183</td><td> Sync duration </td><td> 0</td><td>	Group 183 pm_noedge8</td>

</tr>

<tr><td>PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP183</td><td> Cycles LMQ and SRQ empty </td><td> 1</td><td>	Group 183 pm_noedge8</td>

</tr>

<tr><td>PM_SYNC_COUNT_GRP183</td><td> SYNC instructions completed </td><td> 2</td><td>	Group 183 pm_noedge8</td>

</tr>

<tr><td>PM_LSU_DERAT_MISS_CYC_GRP183</td><td> DERAT miss latency </td><td> 3</td><td>	Group 183 pm_noedge8</td>

</tr>

<tr><td>PM_ST_MISS_L1_GRP184</td><td> L1 D cache store misses </td><td> 0</td><td>	Group 184 pm_edge9</td>

</tr>

<tr><td>PM_DPU_WT_IC_MISS_COUNT_GRP184</td><td> Periods DISP unit is stalled due to I cache miss </td><td> 1</td><td>	Group 184 pm_edge9</td>

</tr>

<tr><td>PM_LD_MISS_L1_GRP184</td><td> L1 D cache load misses </td><td> 2</td><td>	Group 184 pm_edge9</td>

</tr>

<tr><td>PM_LD_REF_L1_GRP184</td><td> L1 D cache load references </td><td> 3</td><td>	Group 184 pm_edge9</td>

</tr>

<tr><td>PM_DPU_HELD_COMPLETION_GRP185</td><td> DISP unit held due to completion holding dispatch  </td><td> 0</td><td>	Group 185 pm_edge10</td>

</tr>

<tr><td>PM_DPU_HELD_POWER_COUNT_GRP185</td><td> Periods DISP unit held due to Power Management </td><td> 1</td><td>	Group 185 pm_edge10</td>

</tr>

<tr><td>PM_DPU_HELD_CR_LOGICAL_GRP185</td><td> DISP unit held due to CR, LR or CTR updated by CR logical, MTCRF, MTLR or MTCTR </td><td> 2</td><td>	Group 185 pm_edge10</td>

</tr>

<tr><td>PM_THRD_BOTH_RUN_COUNT_GRP185</td><td> Periods both threads in run cycles </td><td> 3</td><td>	Group 185 pm_edge10</td>

</tr>

<tr><td>PM_DPU_HELD_COMPLETION_GRP186</td><td> DISP unit held due to completion holding dispatch  </td><td> 0</td><td>	Group 186 pm_noedge10</td>

</tr>

<tr><td>PM_DPU_HELD_POWER_GRP186</td><td> DISP unit held due to Power Management </td><td> 1</td><td>	Group 186 pm_noedge10</td>

</tr>

<tr><td>PM_DPU_HELD_CR_LOGICAL_GRP186</td><td> DISP unit held due to CR, LR or CTR updated by CR logical, MTCRF, MTLR or MTCTR </td><td> 2</td><td>	Group 186 pm_noedge10</td>

</tr>

<tr><td>PM_THRD_BOTH_RUN_CYC_GRP186</td><td> Both threads in run cycles </td><td> 3</td><td>	Group 186 pm_noedge10</td>

</tr>

<tr><td>PM_FPU_1FLOP_GRP187</td><td> FPU executed one flop instruction  </td><td> 0</td><td>	Group 187 pm_hpm1</td>

</tr>

<tr><td>PM_FPU_FMA_GRP187</td><td> FPU executed multiply-add instruction </td><td> 1</td><td>	Group 187 pm_hpm1</td>

</tr>

<tr><td>PM_FPU_FSQRT_FDIV_GRP187</td><td> FPU executed FSQRT or FDIV instruction </td><td> 2</td><td>	Group 187 pm_hpm1</td>

</tr>

<tr><td>PM_CYC_GRP187</td><td> Processor cycles </td><td> 3</td><td>	Group 187 pm_hpm1</td>

</tr>

<tr><td>PM_INST_CMPL_GRP188</td><td> Instructions completed </td><td> 0</td><td>	Group 188 pm_hpm2</td>

</tr>

<tr><td>PM_LSU_LDF_GRP188</td><td> LSU executed Floating Point load instruction </td><td> 1</td><td>	Group 188 pm_hpm2</td>

</tr>

<tr><td>PM_FPU_STF_GRP188</td><td> FPU executed store instruction </td><td> 2</td><td>	Group 188 pm_hpm2</td>

</tr>

<tr><td>PM_CYC_GRP188</td><td> Processor cycles </td><td> 3</td><td>	Group 188 pm_hpm2</td>

</tr>

<tr><td>PM_CYC_GRP189</td><td> Processor cycles </td><td> 0</td><td>	Group 189 pm_hpm3</td>

</tr>

<tr><td>PM_LD_MISS_L1_GRP189</td><td> L1 D cache load misses </td><td> 1</td><td>	Group 189 pm_hpm3</td>

</tr>

<tr><td>PM_ST_MISS_L1_GRP189</td><td> L1 D cache store misses </td><td> 2</td><td>	Group 189 pm_hpm3</td>

</tr>

<tr><td>PM_INST_CMPL_GRP189</td><td> Instructions completed </td><td> 3</td><td>	Group 189 pm_hpm3</td>

</tr>

<tr><td>PM_INST_CMPL_GRP190</td><td> Instructions completed </td><td> 0</td><td>	Group 190 pm_hpm4</td>

</tr>

<tr><td>PM_INST_DISP_GRP190</td><td> Instructions dispatched </td><td> 1</td><td>	Group 190 pm_hpm4</td>

</tr>

<tr><td>PM_LD_REF_L1_GRP190</td><td> L1 D cache load references </td><td> 2</td><td>	Group 190 pm_hpm4</td>

</tr>

<tr><td>PM_ST_REF_L1_GRP190</td><td> L1 D cache store references </td><td> 3</td><td>	Group 190 pm_hpm4</td>

</tr>

<tr><td>PM_FPU_FIN_GRP191</td><td> FPU produced a result </td><td> 0</td><td>	Group 191 pm_hpm5</td>

</tr>

<tr><td>PM_CYC_GRP191</td><td> Processor cycles </td><td> 1</td><td>	Group 191 pm_hpm5</td>

</tr>

<tr><td>PM_FXU0_FIN_GRP191</td><td> FXU0 produced a result </td><td> 2</td><td>	Group 191 pm_hpm5</td>

</tr>

<tr><td>PM_FXU1_FIN_GRP191</td><td> FXU1 produced a result </td><td> 3</td><td>	Group 191 pm_hpm5</td>

</tr>

<tr><td>PM_DATA_FROM_L2_GRP192</td><td> Data loaded from L2 </td><td> 0</td><td>	Group 192 pm_hpm6</td>

</tr>

<tr><td>PM_DATA_FROM_L21_GRP192</td><td> Data loaded from private L2 other core </td><td> 1</td><td>	Group 192 pm_hpm6</td>

</tr>

<tr><td>PM_DATA_FROM_L25_MOD_GRP192</td><td> Data loaded from L2.5 modified </td><td> 2</td><td>	Group 192 pm_hpm6</td>

</tr>

<tr><td>PM_DATA_FROM_L25_SHR_GRP192</td><td> Data loaded from L2.5 shared </td><td> 3</td><td>	Group 192 pm_hpm6</td>

</tr>

<tr><td>PM_DATA_FROM_L35_MOD_GRP193</td><td> Data loaded from L3.5 modified </td><td> 0</td><td>	Group 193 pm_hpm7</td>

</tr>

<tr><td>PM_DATA_FROM_L35_SHR_GRP193</td><td> Data loaded from L3.5 shared </td><td> 1</td><td>	Group 193 pm_hpm7</td>

</tr>

<tr><td>PM_DATA_FROM_L3_GRP193</td><td> Data loaded from L3 </td><td> 2</td><td>	Group 193 pm_hpm7</td>

</tr>

<tr><td>PM_CYC_GRP193</td><td> Processor cycles </td><td> 3</td><td>	Group 193 pm_hpm7</td>

</tr>

<tr><td>PM_FPU_1FLOP_GRP194</td><td> FPU executed one flop instruction  </td><td> 0</td><td>	Group 194 pm_hpm8</td>

</tr>

<tr><td>PM_FPU_FMA_GRP194</td><td> FPU executed multiply-add instruction </td><td> 1</td><td>	Group 194 pm_hpm8</td>

</tr>

<tr><td>PM_FPU_STF_GRP194</td><td> FPU executed store instruction </td><td> 2</td><td>	Group 194 pm_hpm8</td>

</tr>

<tr><td>PM_LD_MISS_L1_GRP194</td><td> L1 D cache load misses </td><td> 3</td><td>	Group 194 pm_hpm8</td>

</tr>

<tr><td>PM_LD_MISS_L1_GRP195</td><td> L1 D cache load misses </td><td> 0</td><td>	Group 195 pm_hpm9</td>

</tr>

<tr><td>PM_CYC_GRP195</td><td> Processor cycles </td><td> 1</td><td>	Group 195 pm_hpm9</td>

</tr>

<tr><td>PM_LSU_LDF_GRP195</td><td> LSU executed Floating Point load instruction </td><td> 2</td><td>	Group 195 pm_hpm9</td>

</tr>

<tr><td>PM_ST_MISS_L1_GRP195</td><td> L1 D cache store misses </td><td> 3</td><td>	Group 195 pm_hpm9</td>

</tr>

<tr><td>PM_INST_CMPL_GRP196</td><td> Instructions completed </td><td> 0</td><td>	Group 196 pm_hpm10</td>

</tr>

<tr><td>PM_L2_MISS_GRP196</td><td> L2 cache misses </td><td> 1</td><td>	Group 196 pm_hpm10</td>

</tr>

<tr><td>PM_INST_FROM_L3MISS_GRP196</td><td> Instruction fetched missed L3 </td><td> 2</td><td>	Group 196 pm_hpm10</td>

</tr>

<tr><td>PM_DATA_FROM_L3MISS_GRP196</td><td> Data loaded from private L3 miss </td><td> 3</td><td>	Group 196 pm_hpm10</td>

</tr>

<tr><td>PM_MRK_DERAT_REF_64K_GRP197</td><td> Marked DERAT reference for 64K page </td><td> 0</td><td>	Group 197 pm_mrk_derat_ref2</td>

</tr>

<tr><td>PM_MRK_DERAT_REF_4K_GRP197</td><td> Marked DERAT reference for 4K page </td><td> 1</td><td>	Group 197 pm_mrk_derat_ref2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP197</td><td> Instructions completed </td><td> 2</td><td>	Group 197 pm_mrk_derat_ref2</td>

</tr>

<tr><td>PM_MRK_DERAT_REF_16G_GRP197</td><td> Marked DERAT reference for 16G page </td><td> 3</td><td>	Group 197 pm_mrk_derat_ref2</td>

</tr>

<tr><td>PM_MRK_DERAT_MISS_64K_GRP198</td><td> Marked DERAT misses for 64K page </td><td> 0</td><td>	Group 198 pm_mrk_derat_miss2</td>

</tr>

<tr><td>PM_MRK_DERAT_MISS_4K_GRP198</td><td> Marked DERAT misses for 4K page </td><td> 1</td><td>	Group 198 pm_mrk_derat_miss2</td>

</tr>

<tr><td>PM_INST_CMPL_GRP198</td><td> Instructions completed </td><td> 2</td><td>	Group 198 pm_mrk_derat_miss2</td>

</tr>

<tr><td>PM_MRK_DERAT_MISS_16G_GRP198</td><td> Marked DERAT misses for 16G page </td><td> 3</td><td>	Group 198 pm_mrk_derat_miss2</td>

</tr>

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