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<tr><td>CYCLES</td><td>	Processor Cycles using continuous sampling </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_RUN_CYC_GRP1</td><td> Run cycles </td><td> 0</td><td>	Group 1 pm_utilization</td>

</tr>

<tr><td>PM_INST_CMPL_GRP1</td><td> Instructions completed </td><td> 1</td><td>	Group 1 pm_utilization</td>

</tr>

<tr><td>PM_INST_DISP_GRP1</td><td> Instructions dispatched </td><td> 2</td><td>	Group 1 pm_utilization</td>

</tr>

<tr><td>PM_CYC_GRP1</td><td> Processor cycles </td><td> 3</td><td>	Group 1 pm_utilization</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP1</td><td> Run instructions completed </td><td> 4</td><td>	Group 1 pm_utilization</td>

</tr>

<tr><td>PM_RUN_CYC_GRP1</td><td> Run cycles </td><td> 5</td><td>	Group 1 pm_utilization</td>

</tr>

<tr><td>PM_1PLUS_PPC_CMPL_GRP2</td><td> One or more PPC instruction completed </td><td> 0</td><td>	Group 2 pm_completion</td>

</tr>

<tr><td>PM_GCT_EMPTY_CYC_GRP2</td><td> Cycles GCT empty </td><td> 1</td><td>	Group 2 pm_completion</td>

</tr>

<tr><td>PM_GRP_CMPL_GRP2</td><td> Group completed </td><td> 2</td><td>	Group 2 pm_completion</td>

</tr>

<tr><td>PM_CYC_GRP2</td><td> Processor cycles </td><td> 3</td><td>	Group 2 pm_completion</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP2</td><td> Run instructions completed </td><td> 4</td><td>	Group 2 pm_completion</td>

</tr>

<tr><td>PM_RUN_CYC_GRP2</td><td> Run cycles </td><td> 5</td><td>	Group 2 pm_completion</td>

</tr>

<tr><td>PM_GRP_DISP_VALID_GRP3</td><td> Group dispatch valid </td><td> 0</td><td>	Group 3 pm_group_dispatch</td>

</tr>

<tr><td>PM_GRP_DISP_REJECT_GRP3</td><td> Group dispatch rejected </td><td> 1</td><td>	Group 3 pm_group_dispatch</td>

</tr>

<tr><td>PM_GRP_DISP_BLK_SB_CYC_GRP3</td><td> Cycles group dispatch blocked by scoreboard </td><td> 2</td><td>	Group 3 pm_group_dispatch</td>

</tr>

<tr><td>PM_INST_DISP_GRP3</td><td> Instructions dispatched </td><td> 3</td><td>	Group 3 pm_group_dispatch</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP3</td><td> Run instructions completed </td><td> 4</td><td>	Group 3 pm_group_dispatch</td>

</tr>

<tr><td>PM_RUN_CYC_GRP3</td><td> Run cycles </td><td> 5</td><td>	Group 3 pm_group_dispatch</td>

</tr>

<tr><td>PM_0INST_CLB_CYC_GRP4</td><td> Cycles no instructions in CLB </td><td> 0</td><td>	Group 4 pm_clb1</td>

</tr>

<tr><td>PM_2INST_CLB_CYC_GRP4</td><td> Cycles 2 instructions in CLB </td><td> 1</td><td>	Group 4 pm_clb1</td>

</tr>

<tr><td>PM_CLB_EMPTY_CYC_GRP4</td><td> Cycles CLB empty </td><td> 2</td><td>	Group 4 pm_clb1</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L35_MOD_CYC_GRP4</td><td> Marked load latency from L3.5 modified </td><td> 3</td><td>	Group 4 pm_clb1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP4</td><td> Run instructions completed </td><td> 4</td><td>	Group 4 pm_clb1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP4</td><td> Run cycles </td><td> 5</td><td>	Group 4 pm_clb1</td>

</tr>

<tr><td>PM_5INST_CLB_CYC_GRP5</td><td> Cycles 5 instructions in CLB </td><td> 0</td><td>	Group 5 pm_clb2</td>

</tr>

<tr><td>PM_6INST_CLB_CYC_GRP5</td><td> Cycles 6 instructions in CLB </td><td> 1</td><td>	Group 5 pm_clb2</td>

</tr>

<tr><td>PM_MRK_LSU_SRQ_INST_VALID_GRP5</td><td> Marked instruction valid in SRQ </td><td> 2</td><td>	Group 5 pm_clb2</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP5</td><td> IOPS instructions completed </td><td> 3</td><td>	Group 5 pm_clb2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP5</td><td> Run instructions completed </td><td> 4</td><td>	Group 5 pm_clb2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP5</td><td> Run cycles </td><td> 5</td><td>	Group 5 pm_clb2</td>

</tr>

<tr><td>PM_GCT_NOSLOT_CYC_GRP6</td><td> Cycles no GCT slot allocated </td><td> 0</td><td>	Group 6 pm_gct_empty</td>

</tr>

<tr><td>PM_GCT_NOSLOT_IC_MISS_GRP6</td><td> No slot in GCT caused by I cache miss </td><td> 1</td><td>	Group 6 pm_gct_empty</td>

</tr>

<tr><td>PM_GCT_NOSLOT_SRQ_FULL_GRP6</td><td> No slot in GCT caused by SRQ full </td><td> 2</td><td>	Group 6 pm_gct_empty</td>

</tr>

<tr><td>PM_GCT_NOSLOT_BR_MPRED_GRP6</td><td> No slot in GCT caused by branch mispredict </td><td> 3</td><td>	Group 6 pm_gct_empty</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP6</td><td> Run instructions completed </td><td> 4</td><td>	Group 6 pm_gct_empty</td>

</tr>

<tr><td>PM_RUN_CYC_GRP6</td><td> Run cycles </td><td> 5</td><td>	Group 6 pm_gct_empty</td>

</tr>

<tr><td>PM_GCT_USAGE_00to59_CYC_GRP7</td><td> Cycles GCT less than 60% full </td><td> 0</td><td>	Group 7 pm_gct_usage</td>

</tr>

<tr><td>PM_GCT_USAGE_60to79_CYC_GRP7</td><td> Cycles GCT 60-79% full </td><td> 1</td><td>	Group 7 pm_gct_usage</td>

</tr>

<tr><td>PM_GCT_USAGE_80to99_CYC_GRP7</td><td> Cycles GCT 80-99% full </td><td> 2</td><td>	Group 7 pm_gct_usage</td>

</tr>

<tr><td>PM_GCT_FULL_CYC_GRP7</td><td> Cycles GCT full </td><td> 3</td><td>	Group 7 pm_gct_usage</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP7</td><td> Run instructions completed </td><td> 4</td><td>	Group 7 pm_gct_usage</td>

</tr>

<tr><td>PM_RUN_CYC_GRP7</td><td> Run cycles </td><td> 5</td><td>	Group 7 pm_gct_usage</td>

</tr>

<tr><td>PM_LSU_LRQ_S0_ALLOC_GRP8</td><td> LRQ slot 0 allocated </td><td> 0</td><td>	Group 8 pm_lsu1</td>

</tr>

<tr><td>PM_LSU_LRQ_S0_VALID_GRP8</td><td> LRQ slot 0 valid </td><td> 1</td><td>	Group 8 pm_lsu1</td>

</tr>

<tr><td>PM_LSU_LMQ_S0_ALLOC_GRP8</td><td> LMQ slot 0 allocated </td><td> 2</td><td>	Group 8 pm_lsu1</td>

</tr>

<tr><td>PM_LSU_LMQ_S0_VALID_GRP8</td><td> LMQ slot 0 valid </td><td> 3</td><td>	Group 8 pm_lsu1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP8</td><td> Run instructions completed </td><td> 4</td><td>	Group 8 pm_lsu1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP8</td><td> Run cycles </td><td> 5</td><td>	Group 8 pm_lsu1</td>

</tr>

<tr><td>PM_LSU_SRQ_S0_ALLOC_GRP9</td><td> SRQ slot 0 allocated </td><td> 0</td><td>	Group 9 pm_lsu2</td>

</tr>

<tr><td>PM_LSU_SRQ_S0_VALID_GRP9</td><td> SRQ slot 0 valid </td><td> 1</td><td>	Group 9 pm_lsu2</td>

</tr>

<tr><td>PM_LSU_SRQ_SYNC_CYC_GRP9</td><td> SRQ sync duration </td><td> 2</td><td>	Group 9 pm_lsu2</td>

</tr>

<tr><td>PM_LSU_SRQ_FULL_CYC_GRP9</td><td> Cycles SRQ full </td><td> 3</td><td>	Group 9 pm_lsu2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP9</td><td> Run instructions completed </td><td> 4</td><td>	Group 9 pm_lsu2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP9</td><td> Run cycles </td><td> 5</td><td>	Group 9 pm_lsu2</td>

</tr>

<tr><td>PM_LSU_LMQ_LHR_MERGE_GRP10</td><td> LMQ LHR merges </td><td> 0</td><td>	Group 10 pm_lsu3</td>

</tr>

<tr><td>PM_LSU_SRQ_STFWD_GRP10</td><td> SRQ store forwarded </td><td> 1</td><td>	Group 10 pm_lsu3</td>

</tr>

<tr><td>PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP10</td><td> Cycles LMQ and SRQ empty </td><td> 2</td><td>	Group 10 pm_lsu3</td>

</tr>

<tr><td>PM_LSU_SRQ_EMPTY_CYC_GRP10</td><td> Cycles SRQ empty </td><td> 3</td><td>	Group 10 pm_lsu3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP10</td><td> Run instructions completed </td><td> 4</td><td>	Group 10 pm_lsu3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP10</td><td> Run cycles </td><td> 5</td><td>	Group 10 pm_lsu3</td>

</tr>

<tr><td>PM_LSU_LMQ_FULL_CYC_GRP11</td><td> Cycles LMQ full </td><td> 0</td><td>	Group 11 pm_lsu4</td>

</tr>

<tr><td>PM_LSU_SRQ_FULL_CYC_GRP11</td><td> Cycles SRQ full </td><td> 1</td><td>	Group 11 pm_lsu4</td>

</tr>

<tr><td>PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP11</td><td> Cycles LMQ and SRQ empty </td><td> 2</td><td>	Group 11 pm_lsu4</td>

</tr>

<tr><td>PM_LSU_SRQ_EMPTY_CYC_GRP11</td><td> Cycles SRQ empty </td><td> 3</td><td>	Group 11 pm_lsu4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP11</td><td> Run instructions completed </td><td> 4</td><td>	Group 11 pm_lsu4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP11</td><td> Run cycles </td><td> 5</td><td>	Group 11 pm_lsu4</td>

</tr>

<tr><td>PM_INST_FROM_L2MISS_GRP12</td><td> Instructions fetched missed L2 </td><td> 0</td><td>	Group 12 pm_prefetch1</td>

</tr>

<tr><td>PM_INST_FETCH_CYC_GRP12</td><td> Cycles at least 1 instruction fetched </td><td> 1</td><td>	Group 12 pm_prefetch1</td>

</tr>

<tr><td>PM_DC_OUT_OF_STREAMS_GRP12</td><td> LSU Data prefetch out of streams </td><td> 2</td><td>	Group 12 pm_prefetch1</td>

</tr>

<tr><td>PM_DC_PREF_STREAM_ALLOC_GRP12</td><td> D cache new prefetch stream allocated </td><td> 3</td><td>	Group 12 pm_prefetch1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP12</td><td> Run instructions completed </td><td> 4</td><td>	Group 12 pm_prefetch1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP12</td><td> Run cycles </td><td> 5</td><td>	Group 12 pm_prefetch1</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP13</td><td> IOPS instructions completed </td><td> 0</td><td>	Group 13 pm_prefetch2</td>

</tr>

<tr><td>PM_CLB_FULL_CYC_GRP13</td><td> Cycles CLB full </td><td> 1</td><td>	Group 13 pm_prefetch2</td>

</tr>

<tr><td>PM_L1_PREF_GRP13</td><td> L1 cache data prefetches </td><td> 2</td><td>	Group 13 pm_prefetch2</td>

</tr>

<tr><td>PM_IC_PREF_INSTALL_GRP13</td><td> Instruction prefetched installed in prefetch </td><td> 3</td><td>	Group 13 pm_prefetch2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP13</td><td> Run instructions completed </td><td> 4</td><td>	Group 13 pm_prefetch2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP13</td><td> Run cycles </td><td> 5</td><td>	Group 13 pm_prefetch2</td>

</tr>

<tr><td>PM_1INST_CLB_CYC_GRP14</td><td> Cycles 1 instruction in CLB </td><td> 0</td><td>	Group 14 pm_prefetch3</td>

</tr>

<tr><td>PM_LSU_BUSY_REJECT_GRP14</td><td> LSU busy due to reject </td><td> 1</td><td>	Group 14 pm_prefetch3</td>

</tr>

<tr><td>PM_L2_PREF_GRP14</td><td> L2 cache prefetches </td><td> 2</td><td>	Group 14 pm_prefetch3</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP14</td><td> IOPS instructions completed </td><td> 3</td><td>	Group 14 pm_prefetch3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP14</td><td> Run instructions completed </td><td> 4</td><td>	Group 14 pm_prefetch3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP14</td><td> Run cycles </td><td> 5</td><td>	Group 14 pm_prefetch3</td>

</tr>

<tr><td>PM_LSU0_REJECT_SRQ_LHS_GRP15</td><td> LSU0 SRQ rejects </td><td> 0</td><td>	Group 15 pm_prefetch4</td>

</tr>

<tr><td>PM_LSU1_REJECT_SRQ_LHS_GRP15</td><td> LSU1 SRQ rejects </td><td> 1</td><td>	Group 15 pm_prefetch4</td>

</tr>

<tr><td>PM_DC_PREF_DST_GRP15</td><td> DST (Data Stream Touch) stream start </td><td> 2</td><td>	Group 15 pm_prefetch4</td>

</tr>

<tr><td>PM_L2_PREF_GRP15</td><td> L2 cache prefetches </td><td> 3</td><td>	Group 15 pm_prefetch4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP15</td><td> Run instructions completed </td><td> 4</td><td>	Group 15 pm_prefetch4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP15</td><td> Run cycles </td><td> 5</td><td>	Group 15 pm_prefetch4</td>

</tr>

<tr><td>PM_LSU_REJECT_ERAT_MISS_GRP16</td><td> LSU reject due to ERAT miss </td><td> 0</td><td>	Group 16 pm_lsu_reject1</td>

</tr>

<tr><td>PM_LSU_REJECT_LMQ_FULL_GRP16</td><td> LSU reject due to LMQ full or missed data coming </td><td> 1</td><td>	Group 16 pm_lsu_reject1</td>

</tr>

<tr><td>PM_FLUSH_IMBAL_GRP16</td><td> Flush caused by thread GCT imbalance </td><td> 2</td><td>	Group 16 pm_lsu_reject1</td>

</tr>

<tr><td>PM_MRK_LSU_FLUSH_SRQ_GRP16</td><td> Marked SRQ flushes </td><td> 3</td><td>	Group 16 pm_lsu_reject1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP16</td><td> Run instructions completed </td><td> 4</td><td>	Group 16 pm_lsu_reject1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP16</td><td> Run cycles </td><td> 5</td><td>	Group 16 pm_lsu_reject1</td>

</tr>

<tr><td>PM_LSU0_REJECT_RELOAD_CDF_GRP17</td><td> LSU0 reject due to reload CDF or tag update collision </td><td> 0</td><td>	Group 17 pm_lsu_reject2</td>

</tr>

<tr><td>PM_LSU1_REJECT_RELOAD_CDF_GRP17</td><td> LSU1 reject due to reload CDF or tag update collision </td><td> 1</td><td>	Group 17 pm_lsu_reject2</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP17</td><td> IOPS instructions completed </td><td> 2</td><td>	Group 17 pm_lsu_reject2</td>

</tr>

<tr><td>PM_L1_WRITE_CYC_GRP17</td><td> Cycles writing to instruction L1 </td><td> 3</td><td>	Group 17 pm_lsu_reject2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP17</td><td> Run instructions completed </td><td> 4</td><td>	Group 17 pm_lsu_reject2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP17</td><td> Run cycles </td><td> 5</td><td>	Group 17 pm_lsu_reject2</td>

</tr>

<tr><td>PM_LSU0_REJECT_ERAT_MISS_GRP18</td><td> LSU0 reject due to ERAT miss </td><td> 0</td><td>	Group 18 pm_lsu_reject3</td>

</tr>

<tr><td>PM_LSU1_REJECT_ERAT_MISS_GRP18</td><td> LSU1 reject due to ERAT miss </td><td> 1</td><td>	Group 18 pm_lsu_reject3</td>

</tr>

<tr><td>PM_LWSYNC_HELD_GRP18</td><td> LWSYNC held at dispatch </td><td> 2</td><td>	Group 18 pm_lsu_reject3</td>

</tr>

<tr><td>PM_TLBIE_HELD_GRP18</td><td> TLBIE held at dispatch </td><td> 3</td><td>	Group 18 pm_lsu_reject3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP18</td><td> Run instructions completed </td><td> 4</td><td>	Group 18 pm_lsu_reject3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP18</td><td> Run cycles </td><td> 5</td><td>	Group 18 pm_lsu_reject3</td>

</tr>

<tr><td>PM_LSU0_REJECT_LMQ_FULL_GRP19</td><td> LSU0 reject due to LMQ full or missed data coming </td><td> 0</td><td>	Group 19 pm_lsu_reject4</td>

</tr>

<tr><td>PM_LSU1_REJECT_LMQ_FULL_GRP19</td><td> LSU1 reject due to LMQ full or missed data coming </td><td> 1</td><td>	Group 19 pm_lsu_reject4</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP19</td><td> IOPS instructions completed </td><td> 2</td><td>	Group 19 pm_lsu_reject4</td>

</tr>

<tr><td>PM_BR_ISSUED_GRP19</td><td> Branches issued </td><td> 3</td><td>	Group 19 pm_lsu_reject4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP19</td><td> Run instructions completed </td><td> 4</td><td>	Group 19 pm_lsu_reject4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP19</td><td> Run cycles </td><td> 5</td><td>	Group 19 pm_lsu_reject4</td>

</tr>

<tr><td>PM_LSU_REJECT_SRQ_LHS_GRP20</td><td> LSU SRQ rejects </td><td> 0</td><td>	Group 20 pm_lsu_reject5</td>

</tr>

<tr><td>PM_LSU_REJECT_RELOAD_CDF_GRP20</td><td> LSU reject due to reload CDF or tag update collision </td><td> 1</td><td>	Group 20 pm_lsu_reject5</td>

</tr>

<tr><td>PM_LSU_FLUSH_GRP20</td><td> Flush initiated by LSU </td><td> 2</td><td>	Group 20 pm_lsu_reject5</td>

</tr>

<tr><td>PM_FLUSH_GRP20</td><td> Flushes </td><td> 3</td><td>	Group 20 pm_lsu_reject5</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP20</td><td> Run instructions completed </td><td> 4</td><td>	Group 20 pm_lsu_reject5</td>

</tr>

<tr><td>PM_RUN_CYC_GRP20</td><td> Run cycles </td><td> 5</td><td>	Group 20 pm_lsu_reject5</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP21</td><td> IOPS instructions completed </td><td> 0</td><td>	Group 21 pm_flush1</td>

</tr>

<tr><td>PM_LSU_FLUSH_UST_GRP21</td><td> SRQ unaligned store flushes </td><td> 1</td><td>	Group 21 pm_flush1</td>

</tr>

<tr><td>PM_FLUSH_IMBAL_GRP21</td><td> Flush caused by thread GCT imbalance </td><td> 2</td><td>	Group 21 pm_flush1</td>

</tr>

<tr><td>PM_DC_INV_L2_GRP21</td><td> L1 D cache entries invalidated from L2 </td><td> 3</td><td>	Group 21 pm_flush1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP21</td><td> Run instructions completed </td><td> 4</td><td>	Group 21 pm_flush1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP21</td><td> Run cycles </td><td> 5</td><td>	Group 21 pm_flush1</td>

</tr>

<tr><td>PM_ITLB_MISS_GRP22</td><td> Instruction TLB misses </td><td> 0</td><td>	Group 22 pm_flush2</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP22</td><td> IOPS instructions completed </td><td> 1</td><td>	Group 22 pm_flush2</td>

</tr>

<tr><td>PM_FLUSH_SB_GRP22</td><td> Flush caused by scoreboard operation </td><td> 2</td><td>	Group 22 pm_flush2</td>

</tr>

<tr><td>PM_FLUSH_SYNC_GRP22</td><td> Flush caused by sync </td><td> 3</td><td>	Group 22 pm_flush2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP22</td><td> Run instructions completed </td><td> 4</td><td>	Group 22 pm_flush2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP22</td><td> Run cycles </td><td> 5</td><td>	Group 22 pm_flush2</td>

</tr>

<tr><td>PM_LSU_FLUSH_SRQ_GRP23</td><td> SRQ flushes </td><td> 0</td><td>	Group 23 pm_lsu_flush_srq_lrq</td>

</tr>

<tr><td>PM_LSU_FLUSH_LRQ_GRP23</td><td> LRQ flushes </td><td> 1</td><td>	Group 23 pm_lsu_flush_srq_lrq</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP23</td><td> IOPS instructions completed </td><td> 2</td><td>	Group 23 pm_lsu_flush_srq_lrq</td>

</tr>

<tr><td>PM_LSU_FLUSH_GRP23</td><td> Flush initiated by LSU </td><td> 3</td><td>	Group 23 pm_lsu_flush_srq_lrq</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP23</td><td> Run instructions completed </td><td> 4</td><td>	Group 23 pm_lsu_flush_srq_lrq</td>

</tr>

<tr><td>PM_RUN_CYC_GRP23</td><td> Run cycles </td><td> 5</td><td>	Group 23 pm_lsu_flush_srq_lrq</td>

</tr>

<tr><td>PM_LSU0_FLUSH_LRQ_GRP24</td><td> LSU0 LRQ flushes </td><td> 0</td><td>	Group 24 pm_lsu_flush_lrq</td>

</tr>

<tr><td>PM_LSU1_FLUSH_LRQ_GRP24</td><td> LSU1 LRQ flushes </td><td> 1</td><td>	Group 24 pm_lsu_flush_lrq</td>

</tr>

<tr><td>PM_LSU_FLUSH_GRP24</td><td> Flush initiated by LSU </td><td> 2</td><td>	Group 24 pm_lsu_flush_lrq</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP24</td><td> IOPS instructions completed </td><td> 3</td><td>	Group 24 pm_lsu_flush_lrq</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP24</td><td> Run instructions completed </td><td> 4</td><td>	Group 24 pm_lsu_flush_lrq</td>

</tr>

<tr><td>PM_RUN_CYC_GRP24</td><td> Run cycles </td><td> 5</td><td>	Group 24 pm_lsu_flush_lrq</td>

</tr>

<tr><td>PM_LSU0_FLUSH_SRQ_GRP25</td><td> LSU0 SRQ flushes </td><td> 0</td><td>	Group 25 pm_lsu_flush_srq</td>

</tr>

<tr><td>PM_LSU1_FLUSH_SRQ_GRP25</td><td> LSU1 SRQ flushes </td><td> 1</td><td>	Group 25 pm_lsu_flush_srq</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP25</td><td> IOPS instructions completed </td><td> 2</td><td>	Group 25 pm_lsu_flush_srq</td>

</tr>

<tr><td>PM_LSU_FLUSH_GRP25</td><td> Flush initiated by LSU </td><td> 3</td><td>	Group 25 pm_lsu_flush_srq</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP25</td><td> Run instructions completed </td><td> 4</td><td>	Group 25 pm_lsu_flush_srq</td>

</tr>

<tr><td>PM_RUN_CYC_GRP25</td><td> Run cycles </td><td> 5</td><td>	Group 25 pm_lsu_flush_srq</td>

</tr>

<tr><td>PM_LSU_FLUSH_ULD_GRP26</td><td> LRQ unaligned load flushes </td><td> 0</td><td>	Group 26 pm_lsu_flush_unaligned</td>

</tr>

<tr><td>PM_LSU_FLUSH_UST_GRP26</td><td> SRQ unaligned store flushes </td><td> 1</td><td>	Group 26 pm_lsu_flush_unaligned</td>

</tr>

<tr><td>PM_BR_ISSUED_GRP26</td><td> Branches issued </td><td> 2</td><td>	Group 26 pm_lsu_flush_unaligned</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP26</td><td> IOPS instructions completed </td><td> 3</td><td>	Group 26 pm_lsu_flush_unaligned</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP26</td><td> Run instructions completed </td><td> 4</td><td>	Group 26 pm_lsu_flush_unaligned</td>

</tr>

<tr><td>PM_RUN_CYC_GRP26</td><td> Run cycles </td><td> 5</td><td>	Group 26 pm_lsu_flush_unaligned</td>

</tr>

<tr><td>PM_LSU0_FLUSH_ULD_GRP27</td><td> LSU0 unaligned load flushes </td><td> 0</td><td>	Group 27 pm_lsu_flush_uld</td>

</tr>

<tr><td>PM_LSU1_FLUSH_ULD_GRP27</td><td> LSU1 unaligned load flushes </td><td> 1</td><td>	Group 27 pm_lsu_flush_uld</td>

</tr>

<tr><td>PM_LSU_FLUSH_GRP27</td><td> Flush initiated by LSU </td><td> 2</td><td>	Group 27 pm_lsu_flush_uld</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP27</td><td> IOPS instructions completed </td><td> 3</td><td>	Group 27 pm_lsu_flush_uld</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP27</td><td> Run instructions completed </td><td> 4</td><td>	Group 27 pm_lsu_flush_uld</td>

</tr>

<tr><td>PM_RUN_CYC_GRP27</td><td> Run cycles </td><td> 5</td><td>	Group 27 pm_lsu_flush_uld</td>

</tr>

<tr><td>PM_LSU0_FLUSH_UST_GRP28</td><td> LSU0 unaligned store flushes </td><td> 0</td><td>	Group 28 pm_lsu_flush_ust</td>

</tr>

<tr><td>PM_LSU1_FLUSH_UST_GRP28</td><td> LSU1 unaligned store flushes </td><td> 1</td><td>	Group 28 pm_lsu_flush_ust</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP28</td><td> IOPS instructions completed </td><td> 2</td><td>	Group 28 pm_lsu_flush_ust</td>

</tr>

<tr><td>PM_LSU_FLUSH_GRP28</td><td> Flush initiated by LSU </td><td> 3</td><td>	Group 28 pm_lsu_flush_ust</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP28</td><td> Run instructions completed </td><td> 4</td><td>	Group 28 pm_lsu_flush_ust</td>

</tr>

<tr><td>PM_RUN_CYC_GRP28</td><td> Run cycles </td><td> 5</td><td>	Group 28 pm_lsu_flush_ust</td>

</tr>

<tr><td>PM_LSU_FLUSH_LRQ_FULL_GRP29</td><td> Flush caused by LRQ full </td><td> 0</td><td>	Group 29 pm_lsu_flush_full</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP29</td><td> IOPS instructions completed </td><td> 1</td><td>	Group 29 pm_lsu_flush_full</td>

</tr>

<tr><td>PM_MRK_LSU_FLUSH_LRQ_GRP29</td><td> Marked LRQ flushes </td><td> 2</td><td>	Group 29 pm_lsu_flush_full</td>

</tr>

<tr><td>PM_LSU_FLUSH_SRQ_FULL_GRP29</td><td> Flush caused by SRQ full </td><td> 3</td><td>	Group 29 pm_lsu_flush_full</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP29</td><td> Run instructions completed </td><td> 4</td><td>	Group 29 pm_lsu_flush_full</td>

</tr>

<tr><td>PM_RUN_CYC_GRP29</td><td> Run cycles </td><td> 5</td><td>	Group 29 pm_lsu_flush_full</td>

</tr>

<tr><td>PM_GRP_MRK_GRP30</td><td> Group marked in IDU </td><td> 0</td><td>	Group 30 pm_lsu_stall1</td>

</tr>

<tr><td>PM_CMPLU_STALL_LSU_GRP30</td><td> Completion stall caused by LSU instruction </td><td> 1</td><td>	Group 30 pm_lsu_stall1</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP30</td><td> IOPS instructions completed </td><td> 2</td><td>	Group 30 pm_lsu_stall1</td>

</tr>

<tr><td>PM_CMPLU_STALL_REJECT_GRP30</td><td> Completion stall caused by reject </td><td> 3</td><td>	Group 30 pm_lsu_stall1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP30</td><td> Run instructions completed </td><td> 4</td><td>	Group 30 pm_lsu_stall1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP30</td><td> Run cycles </td><td> 5</td><td>	Group 30 pm_lsu_stall1</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP31</td><td> IOPS instructions completed </td><td> 0</td><td>	Group 31 pm_lsu_stall2</td>

</tr>

<tr><td>PM_CMPLU_STALL_DCACHE_MISS_GRP31</td><td> Completion stall caused by D cache miss </td><td> 1</td><td>	Group 31 pm_lsu_stall2</td>

</tr>

<tr><td>PM_CYC_GRP31</td><td> Processor cycles </td><td> 2</td><td>	Group 31 pm_lsu_stall2</td>

</tr>

<tr><td>PM_CMPLU_STALL_ERAT_MISS_GRP31</td><td> Completion stall caused by ERAT miss </td><td> 3</td><td>	Group 31 pm_lsu_stall2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP31</td><td> Run instructions completed </td><td> 4</td><td>	Group 31 pm_lsu_stall2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP31</td><td> Run cycles </td><td> 5</td><td>	Group 31 pm_lsu_stall2</td>

</tr>

<tr><td>PM_GRP_IC_MISS_BR_REDIR_NONSPEC_GRP32</td><td> Group experienced non-speculative I cache miss or branch redirect </td><td> 0</td><td>	Group 32 pm_fxu_stall</td>

</tr>

<tr><td>PM_CMPLU_STALL_FXU_GRP32</td><td> Completion stall caused by FXU instruction </td><td> 1</td><td>	Group 32 pm_fxu_stall</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP32</td><td> IOPS instructions completed </td><td> 2</td><td>	Group 32 pm_fxu_stall</td>

</tr>

<tr><td>PM_CMPLU_STALL_DIV_GRP32</td><td> Completion stall caused by DIV instruction </td><td> 3</td><td>	Group 32 pm_fxu_stall</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP32</td><td> Run instructions completed </td><td> 4</td><td>	Group 32 pm_fxu_stall</td>

</tr>

<tr><td>PM_RUN_CYC_GRP32</td><td> Run cycles </td><td> 5</td><td>	Group 32 pm_fxu_stall</td>

</tr>

<tr><td>PM_FPU_FULL_CYC_GRP33</td><td> Cycles FPU issue queue full </td><td> 0</td><td>	Group 33 pm_fpu_stall</td>

</tr>

<tr><td>PM_CMPLU_STALL_FDIV_GRP33</td><td> Completion stall caused by FDIV or FQRT instruction </td><td> 1</td><td>	Group 33 pm_fpu_stall</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP33</td><td> IOPS instructions completed </td><td> 2</td><td>	Group 33 pm_fpu_stall</td>

</tr>

<tr><td>PM_CMPLU_STALL_FPU_GRP33</td><td> Completion stall caused by FPU instruction </td><td> 3</td><td>	Group 33 pm_fpu_stall</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP33</td><td> Run instructions completed </td><td> 4</td><td>	Group 33 pm_fpu_stall</td>

</tr>

<tr><td>PM_RUN_CYC_GRP33</td><td> Run cycles </td><td> 5</td><td>	Group 33 pm_fpu_stall</td>

</tr>

<tr><td>PM_LARX_LSU0_GRP34</td><td> Larx executed on LSU0 </td><td> 0</td><td>	Group 34 pm_queue_full</td>

</tr>

<tr><td>PM_BRQ_FULL_CYC_GRP34</td><td> Cycles branch queue full </td><td> 1</td><td>	Group 34 pm_queue_full</td>

</tr>

<tr><td>PM_LSU_LRQ_FULL_CYC_GRP34</td><td> Cycles LRQ full </td><td> 2</td><td>	Group 34 pm_queue_full</td>

</tr>

<tr><td>PM_LSU_LMQ_FULL_CYC_GRP34</td><td> Cycles LMQ full </td><td> 3</td><td>	Group 34 pm_queue_full</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP34</td><td> Run instructions completed </td><td> 4</td><td>	Group 34 pm_queue_full</td>

</tr>

<tr><td>PM_RUN_CYC_GRP34</td><td> Run cycles </td><td> 5</td><td>	Group 34 pm_queue_full</td>

</tr>

<tr><td>PM_FPU0_FULL_CYC_GRP35</td><td> Cycles FPU0 issue queue full </td><td> 0</td><td>	Group 35 pm_issueq_full</td>

</tr>

<tr><td>PM_FPU1_FULL_CYC_GRP35</td><td> Cycles FPU1 issue queue full </td><td> 1</td><td>	Group 35 pm_issueq_full</td>

</tr>

<tr><td>PM_FXLS0_FULL_CYC_GRP35</td><td> Cycles FXU0/LS0 queue full </td><td> 2</td><td>	Group 35 pm_issueq_full</td>

</tr>

<tr><td>PM_FXLS1_FULL_CYC_GRP35</td><td> Cycles FXU1/LS1 queue full </td><td> 3</td><td>	Group 35 pm_issueq_full</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP35</td><td> Run instructions completed </td><td> 4</td><td>	Group 35 pm_issueq_full</td>

</tr>

<tr><td>PM_RUN_CYC_GRP35</td><td> Run cycles </td><td> 5</td><td>	Group 35 pm_issueq_full</td>

</tr>

<tr><td>PM_CR_MAP_FULL_CYC_GRP36</td><td> Cycles CR logical operation mapper full </td><td> 0</td><td>	Group 36 pm_mapper_full1</td>

</tr>

<tr><td>PM_LR_CTR_MAP_FULL_CYC_GRP36</td><td> Cycles LR/CTR mapper full </td><td> 1</td><td>	Group 36 pm_mapper_full1</td>

</tr>

<tr><td>PM_GPR_MAP_FULL_CYC_GRP36</td><td> Cycles GPR mapper full </td><td> 2</td><td>	Group 36 pm_mapper_full1</td>

</tr>

<tr><td>PM_CRQ_FULL_CYC_GRP36</td><td> Cycles CR issue queue full </td><td> 3</td><td>	Group 36 pm_mapper_full1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP36</td><td> Run instructions completed </td><td> 4</td><td>	Group 36 pm_mapper_full1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP36</td><td> Run cycles </td><td> 5</td><td>	Group 36 pm_mapper_full1</td>

</tr>

<tr><td>PM_FPR_MAP_FULL_CYC_GRP37</td><td> Cycles FPR mapper full </td><td> 0</td><td>	Group 37 pm_mapper_full2</td>

</tr>

<tr><td>PM_XER_MAP_FULL_CYC_GRP37</td><td> Cycles XER mapper full </td><td> 1</td><td>	Group 37 pm_mapper_full2</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L2MISS_GRP37</td><td> Marked data loaded missed L2 </td><td> 2</td><td>	Group 37 pm_mapper_full2</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP37</td><td> IOPS instructions completed </td><td> 3</td><td>	Group 37 pm_mapper_full2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP37</td><td> Run instructions completed </td><td> 4</td><td>	Group 37 pm_mapper_full2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP37</td><td> Run cycles </td><td> 5</td><td>	Group 37 pm_mapper_full2</td>

</tr>

<tr><td>PM_STCX_FAIL_GRP38</td><td> STCX failed </td><td> 0</td><td>	Group 38 pm_misc_load</td>

</tr>

<tr><td>PM_STCX_PASS_GRP38</td><td> Stcx passes </td><td> 1</td><td>	Group 38 pm_misc_load</td>

</tr>

<tr><td>PM_LSU0_NCLD_GRP38</td><td> LSU0 non-cacheable loads </td><td> 2</td><td>	Group 38 pm_misc_load</td>

</tr>

<tr><td>PM_LSU1_NCLD_GRP38</td><td> LSU1 non-cacheable loads </td><td> 3</td><td>	Group 38 pm_misc_load</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP38</td><td> Run instructions completed </td><td> 4</td><td>	Group 38 pm_misc_load</td>

</tr>

<tr><td>PM_RUN_CYC_GRP38</td><td> Run cycles </td><td> 5</td><td>	Group 38 pm_misc_load</td>

</tr>

<tr><td>PM_LSU0_BUSY_REJECT_GRP39</td><td> LSU0 busy due to reject </td><td> 0</td><td>	Group 39 pm_ic_demand</td>

</tr>

<tr><td>PM_LSU1_BUSY_REJECT_GRP39</td><td> LSU1 busy due to reject </td><td> 1</td><td>	Group 39 pm_ic_demand</td>

</tr>

<tr><td>PM_IC_DEMAND_L2_BHT_REDIRECT_GRP39</td><td> L2 I cache demand request due to BHT redirect </td><td> 2</td><td>	Group 39 pm_ic_demand</td>

</tr>

<tr><td>PM_IC_DEMAND_L2_BR_REDIRECT_GRP39</td><td> L2 I cache demand request due to branch redirect </td><td> 3</td><td>	Group 39 pm_ic_demand</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP39</td><td> Run instructions completed </td><td> 4</td><td>	Group 39 pm_ic_demand</td>

</tr>

<tr><td>PM_RUN_CYC_GRP39</td><td> Run cycles </td><td> 5</td><td>	Group 39 pm_ic_demand</td>

</tr>

<tr><td>PM_IERAT_XLATE_WR_GRP40</td><td> Translation written to ierat </td><td> 0</td><td>	Group 40 pm_ic_pref</td>

</tr>

<tr><td>PM_IC_PREF_REQ_GRP40</td><td> Instruction prefetch requests </td><td> 1</td><td>	Group 40 pm_ic_pref</td>

</tr>

<tr><td>PM_IC_PREF_INSTALL_GRP40</td><td> Instruction prefetched installed in prefetch </td><td> 2</td><td>	Group 40 pm_ic_pref</td>

</tr>

<tr><td>PM_0INST_FETCH_GRP40</td><td> No instructions fetched </td><td> 3</td><td>	Group 40 pm_ic_pref</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP40</td><td> Run instructions completed </td><td> 4</td><td>	Group 40 pm_ic_pref</td>

</tr>

<tr><td>PM_RUN_CYC_GRP40</td><td> Run cycles </td><td> 5</td><td>	Group 40 pm_ic_pref</td>

</tr>

<tr><td>PM_GRP_IC_MISS_NONSPEC_GRP41</td><td> Group experienced non-speculative I cache miss </td><td> 0</td><td>	Group 41 pm_ic_miss</td>

</tr>

<tr><td>PM_GRP_IC_MISS_GRP41</td><td> Group experienced I cache miss </td><td> 1</td><td>	Group 41 pm_ic_miss</td>

</tr>

<tr><td>PM_L1_DCACHE_RELOAD_VALID_GRP41</td><td> L1 reload data source valid </td><td> 2</td><td>	Group 41 pm_ic_miss</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP41</td><td> IOPS instructions completed </td><td> 3</td><td>	Group 41 pm_ic_miss</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP41</td><td> Run instructions completed </td><td> 4</td><td>	Group 41 pm_ic_miss</td>

</tr>

<tr><td>PM_RUN_CYC_GRP41</td><td> Run cycles </td><td> 5</td><td>	Group 41 pm_ic_miss</td>

</tr>

<tr><td>PM_TLB_MISS_GRP42</td><td> TLB misses </td><td> 0</td><td>	Group 42 pm_branch_miss</td>

</tr>

<tr><td>PM_SLB_MISS_GRP42</td><td> SLB misses </td><td> 1</td><td>	Group 42 pm_branch_miss</td>

</tr>

<tr><td>PM_BR_MPRED_CR_GRP42</td><td> Branch mispredictions due to CR bit setting </td><td> 2</td><td>	Group 42 pm_branch_miss</td>

</tr>

<tr><td>PM_BR_MPRED_TA_GRP42</td><td> Branch mispredictions due to target address </td><td> 3</td><td>	Group 42 pm_branch_miss</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP42</td><td> Run instructions completed </td><td> 4</td><td>	Group 42 pm_branch_miss</td>

</tr>

<tr><td>PM_RUN_CYC_GRP42</td><td> Run cycles </td><td> 5</td><td>	Group 42 pm_branch_miss</td>

</tr>

<tr><td>PM_BR_UNCOND_GRP43</td><td> Unconditional branch </td><td> 0</td><td>	Group 43 pm_branch1</td>

</tr>

<tr><td>PM_BR_PRED_TA_GRP43</td><td> A conditional branch was predicted, target prediction </td><td> 1</td><td>	Group 43 pm_branch1</td>

</tr>

<tr><td>PM_BR_PRED_CR_GRP43</td><td> A conditional branch was predicted, CR prediction </td><td> 2</td><td>	Group 43 pm_branch1</td>

</tr>

<tr><td>PM_BR_PRED_CR_TA_GRP43</td><td> A conditional branch was predicted, CR and target prediction </td><td> 3</td><td>	Group 43 pm_branch1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP43</td><td> Run instructions completed </td><td> 4</td><td>	Group 43 pm_branch1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP43</td><td> Run cycles </td><td> 5</td><td>	Group 43 pm_branch1</td>

</tr>

<tr><td>PM_GRP_BR_REDIR_NONSPEC_GRP44</td><td> Group experienced non-speculative branch redirect </td><td> 0</td><td>	Group 44 pm_branch2</td>

</tr>

<tr><td>PM_GRP_BR_REDIR_GRP44</td><td> Group experienced branch redirect </td><td> 1</td><td>	Group 44 pm_branch2</td>

</tr>

<tr><td>PM_FLUSH_BR_MPRED_GRP44</td><td> Flush caused by branch mispredict </td><td> 2</td><td>	Group 44 pm_branch2</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP44</td><td> IOPS instructions completed </td><td> 3</td><td>	Group 44 pm_branch2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP44</td><td> Run instructions completed </td><td> 4</td><td>	Group 44 pm_branch2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP44</td><td> Run cycles </td><td> 5</td><td>	Group 44 pm_branch2</td>

</tr>

<tr><td>PM_DATA_TABLEWALK_CYC_GRP45</td><td> Cycles doing data tablewalks </td><td> 0</td><td>	Group 45 pm_L1_tlbmiss</td>

</tr>

<tr><td>PM_DTLB_MISS_GRP45</td><td> Data TLB misses </td><td> 1</td><td>	Group 45 pm_L1_tlbmiss</td>

</tr>

<tr><td>PM_LD_MISS_L1_GRP45</td><td> L1 D cache load misses </td><td> 2</td><td>	Group 45 pm_L1_tlbmiss</td>

</tr>

<tr><td>PM_LD_REF_L1_GRP45</td><td> L1 D cache load references </td><td> 3</td><td>	Group 45 pm_L1_tlbmiss</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP45</td><td> Run instructions completed </td><td> 4</td><td>	Group 45 pm_L1_tlbmiss</td>

</tr>

<tr><td>PM_RUN_CYC_GRP45</td><td> Run cycles </td><td> 5</td><td>	Group 45 pm_L1_tlbmiss</td>

</tr>

<tr><td>PM_DATA_FROM_L2_GRP46</td><td> Data loaded from L2 </td><td> 0</td><td>	Group 46 pm_L1_DERAT_miss</td>

</tr>

<tr><td>PM_LSU_DERAT_MISS_GRP46</td><td> DERAT misses </td><td> 1</td><td>	Group 46 pm_L1_DERAT_miss</td>

</tr>

<tr><td>PM_ST_REF_L1_GRP46</td><td> L1 D cache store references </td><td> 2</td><td>	Group 46 pm_L1_DERAT_miss</td>

</tr>

<tr><td>PM_ST_MISS_L1_GRP46</td><td> L1 D cache store misses </td><td> 3</td><td>	Group 46 pm_L1_DERAT_miss</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP46</td><td> Run instructions completed </td><td> 4</td><td>	Group 46 pm_L1_DERAT_miss</td>

</tr>

<tr><td>PM_RUN_CYC_GRP46</td><td> Run cycles </td><td> 5</td><td>	Group 46 pm_L1_DERAT_miss</td>

</tr>

<tr><td>PM_DSLB_MISS_GRP47</td><td> Data SLB misses </td><td> 0</td><td>	Group 47 pm_L1_slbmiss</td>

</tr>

<tr><td>PM_ISLB_MISS_GRP47</td><td> Instruction SLB misses </td><td> 1</td><td>	Group 47 pm_L1_slbmiss</td>

</tr>

<tr><td>PM_LD_MISS_L1_LSU0_GRP47</td><td> LSU0 L1 D cache load misses </td><td> 2</td><td>	Group 47 pm_L1_slbmiss</td>

</tr>

<tr><td>PM_LD_MISS_L1_LSU1_GRP47</td><td> LSU1 L1 D cache load misses </td><td> 3</td><td>	Group 47 pm_L1_slbmiss</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP47</td><td> Run instructions completed </td><td> 4</td><td>	Group 47 pm_L1_slbmiss</td>

</tr>

<tr><td>PM_RUN_CYC_GRP47</td><td> Run cycles </td><td> 5</td><td>	Group 47 pm_L1_slbmiss</td>

</tr>

<tr><td>PM_DTLB_REF_4K_GRP48</td><td> Data TLB reference for 4K page </td><td> 0</td><td>	Group 48 pm_dtlbref</td>

</tr>

<tr><td>PM_DTLB_REF_64K_GRP48</td><td> Data TLB reference for 64K page </td><td> 1</td><td>	Group 48 pm_dtlbref</td>

</tr>

<tr><td>PM_DTLB_REF_16M_GRP48</td><td> Data TLB reference for 16M page </td><td> 2</td><td>	Group 48 pm_dtlbref</td>

</tr>

<tr><td>PM_DTLB_REF_16G_GRP48</td><td> Data TLB reference for 16G page </td><td> 3</td><td>	Group 48 pm_dtlbref</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP48</td><td> Run instructions completed </td><td> 4</td><td>	Group 48 pm_dtlbref</td>

</tr>

<tr><td>PM_RUN_CYC_GRP48</td><td> Run cycles </td><td> 5</td><td>	Group 48 pm_dtlbref</td>

</tr>

<tr><td>PM_DTLB_MISS_4K_GRP49</td><td> Data TLB miss for 4K page </td><td> 0</td><td>	Group 49 pm_dtlbmiss</td>

</tr>

<tr><td>PM_DTLB_MISS_64K_GRP49</td><td> Data TLB miss for 64K page </td><td> 1</td><td>	Group 49 pm_dtlbmiss</td>

</tr>

<tr><td>PM_DTLB_MISS_16M_GRP49</td><td> Data TLB miss for 16M page </td><td> 2</td><td>	Group 49 pm_dtlbmiss</td>

</tr>

<tr><td>PM_DTLB_MISS_16G_GRP49</td><td> Data TLB miss for 16G page </td><td> 3</td><td>	Group 49 pm_dtlbmiss</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP49</td><td> Run instructions completed </td><td> 4</td><td>	Group 49 pm_dtlbmiss</td>

</tr>

<tr><td>PM_RUN_CYC_GRP49</td><td> Run cycles </td><td> 5</td><td>	Group 49 pm_dtlbmiss</td>

</tr>

<tr><td>PM_DTLB_REF_GRP50</td><td> Data TLB references </td><td> 0</td><td>	Group 50 pm_dtlb</td>

</tr>

<tr><td>PM_DTLB_MISS_GRP50</td><td> Data TLB misses </td><td> 1</td><td>	Group 50 pm_dtlb</td>

</tr>

<tr><td>PM_CYC_GRP50</td><td> Processor cycles </td><td> 2</td><td>	Group 50 pm_dtlb</td>

</tr>

<tr><td>PM_CYC_GRP50</td><td> Processor cycles </td><td> 3</td><td>	Group 50 pm_dtlb</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP50</td><td> Run instructions completed </td><td> 4</td><td>	Group 50 pm_dtlb</td>

</tr>

<tr><td>PM_RUN_CYC_GRP50</td><td> Run cycles </td><td> 5</td><td>	Group 50 pm_dtlb</td>

</tr>

<tr><td>PM_LD_REF_L1_GRP51</td><td> L1 D cache load references </td><td> 0</td><td>	Group 51 pm_L1_refmiss</td>

</tr>

<tr><td>PM_ST_REF_L1_GRP51</td><td> L1 D cache store references </td><td> 1</td><td>	Group 51 pm_L1_refmiss</td>

</tr>

<tr><td>PM_LD_MISS_L1_GRP51</td><td> L1 D cache load misses </td><td> 2</td><td>	Group 51 pm_L1_refmiss</td>

</tr>

<tr><td>PM_ST_MISS_L1_GRP51</td><td> L1 D cache store misses </td><td> 3</td><td>	Group 51 pm_L1_refmiss</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP51</td><td> Run instructions completed </td><td> 4</td><td>	Group 51 pm_L1_refmiss</td>

</tr>

<tr><td>PM_RUN_CYC_GRP51</td><td> Run cycles </td><td> 5</td><td>	Group 51 pm_L1_refmiss</td>

</tr>

<tr><td>PM_DATA_FROM_L3_GRP52</td><td> Data loaded from L3 </td><td> 0</td><td>	Group 52 pm_dsource1</td>

</tr>

<tr><td>PM_DATA_FROM_LMEM_GRP52</td><td> Data loaded from local memory </td><td> 1</td><td>	Group 52 pm_dsource1</td>

</tr>

<tr><td>PM_FLUSH_GRP52</td><td> Flushes </td><td> 2</td><td>	Group 52 pm_dsource1</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP52</td><td> IOPS instructions completed </td><td> 3</td><td>	Group 52 pm_dsource1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP52</td><td> Run instructions completed </td><td> 4</td><td>	Group 52 pm_dsource1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP52</td><td> Run cycles </td><td> 5</td><td>	Group 52 pm_dsource1</td>

</tr>

<tr><td>PM_DATA_FROM_L3_GRP53</td><td> Data loaded from L3 </td><td> 0</td><td>	Group 53 pm_dsource2</td>

</tr>

<tr><td>PM_DATA_FROM_LMEM_GRP53</td><td> Data loaded from local memory </td><td> 1</td><td>	Group 53 pm_dsource2</td>

</tr>

<tr><td>PM_DATA_FROM_L2MISS_GRP53</td><td> Data loaded missed L2 </td><td> 2</td><td>	Group 53 pm_dsource2</td>

</tr>

<tr><td>PM_DATA_FROM_RMEM_GRP53</td><td> Data loaded from remote memory </td><td> 3</td><td>	Group 53 pm_dsource2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP53</td><td> Run instructions completed </td><td> 4</td><td>	Group 53 pm_dsource2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP53</td><td> Run cycles </td><td> 5</td><td>	Group 53 pm_dsource2</td>

</tr>

<tr><td>PM_DATA_FROM_L25_SHR_GRP54</td><td> Data loaded from L2.5 shared </td><td> 0</td><td>	Group 54 pm_dsource_L2</td>

</tr>

<tr><td>PM_DATA_FROM_L25_MOD_GRP54</td><td> Data loaded from L2.5 modified </td><td> 1</td><td>	Group 54 pm_dsource_L2</td>

</tr>

<tr><td>PM_DATA_FROM_L275_SHR_GRP54</td><td> Data loaded from L2.75 shared </td><td> 2</td><td>	Group 54 pm_dsource_L2</td>

</tr>

<tr><td>PM_DATA_FROM_L275_MOD_GRP54</td><td> Data loaded from L2.75 modified </td><td> 3</td><td>	Group 54 pm_dsource_L2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP54</td><td> Run instructions completed </td><td> 4</td><td>	Group 54 pm_dsource_L2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP54</td><td> Run cycles </td><td> 5</td><td>	Group 54 pm_dsource_L2</td>

</tr>

<tr><td>PM_DATA_FROM_L35_SHR_GRP55</td><td> Data loaded from L3.5 shared </td><td> 0</td><td>	Group 55 pm_dsource_L3</td>

</tr>

<tr><td>PM_DATA_FROM_L35_MOD_GRP55</td><td> Data loaded from L3.5 modified </td><td> 1</td><td>	Group 55 pm_dsource_L3</td>

</tr>

<tr><td>PM_DATA_FROM_L375_SHR_GRP55</td><td> Data loaded from L3.75 shared </td><td> 2</td><td>	Group 55 pm_dsource_L3</td>

</tr>

<tr><td>PM_DATA_FROM_L375_MOD_GRP55</td><td> Data loaded from L3.75 modified </td><td> 3</td><td>	Group 55 pm_dsource_L3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP55</td><td> Run instructions completed </td><td> 4</td><td>	Group 55 pm_dsource_L3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP55</td><td> Run cycles </td><td> 5</td><td>	Group 55 pm_dsource_L3</td>

</tr>

<tr><td>PM_INST_FROM_L3_GRP56</td><td> Instruction fetched from L3 </td><td> 0</td><td>	Group 56 pm_isource1</td>

</tr>

<tr><td>PM_INST_FROM_L1_GRP56</td><td> Instruction fetched from L1 </td><td> 1</td><td>	Group 56 pm_isource1</td>

</tr>

<tr><td>PM_INST_FROM_PREF_GRP56</td><td> Instructions fetched from prefetch </td><td> 2</td><td>	Group 56 pm_isource1</td>

</tr>

<tr><td>PM_INST_FROM_RMEM_GRP56</td><td> Instruction fetched from remote memory </td><td> 3</td><td>	Group 56 pm_isource1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP56</td><td> Run instructions completed </td><td> 4</td><td>	Group 56 pm_isource1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP56</td><td> Run cycles </td><td> 5</td><td>	Group 56 pm_isource1</td>

</tr>

<tr><td>PM_INST_FROM_L2_GRP57</td><td> Instructions fetched from L2 </td><td> 0</td><td>	Group 57 pm_isource2</td>

</tr>

<tr><td>PM_INST_FROM_LMEM_GRP57</td><td> Instruction fetched from local memory </td><td> 1</td><td>	Group 57 pm_isource2</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP57</td><td> IOPS instructions completed </td><td> 2</td><td>	Group 57 pm_isource2</td>

</tr>

<tr><td>PM_0INST_FETCH_GRP57</td><td> No instructions fetched </td><td> 3</td><td>	Group 57 pm_isource2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP57</td><td> Run instructions completed </td><td> 4</td><td>	Group 57 pm_isource2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP57</td><td> Run cycles </td><td> 5</td><td>	Group 57 pm_isource2</td>

</tr>

<tr><td>PM_INST_FROM_L25_SHR_GRP58</td><td> Instruction fetched from L2.5 shared </td><td> 0</td><td>	Group 58 pm_isource_L2</td>

</tr>

<tr><td>PM_INST_FROM_L25_MOD_GRP58</td><td> Instruction fetched from L2.5 modified </td><td> 1</td><td>	Group 58 pm_isource_L2</td>

</tr>

<tr><td>PM_INST_FROM_L275_SHR_GRP58</td><td> Instruction fetched from L2.75 shared </td><td> 2</td><td>	Group 58 pm_isource_L2</td>

</tr>

<tr><td>PM_INST_FROM_L275_MOD_GRP58</td><td> Instruction fetched from L2.75 modified </td><td> 3</td><td>	Group 58 pm_isource_L2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP58</td><td> Run instructions completed </td><td> 4</td><td>	Group 58 pm_isource_L2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP58</td><td> Run cycles </td><td> 5</td><td>	Group 58 pm_isource_L2</td>

</tr>

<tr><td>PM_INST_FROM_L2MISS_GRP59</td><td> Instructions fetched missed L2 </td><td> 0</td><td>	Group 59 pm_isource_L3</td>

</tr>

<tr><td>PM_INST_FROM_L35_MOD_GRP59</td><td> Instruction fetched from L3.5 modified </td><td> 1</td><td>	Group 59 pm_isource_L3</td>

</tr>

<tr><td>PM_INST_FROM_L375_SHR_GRP59</td><td> Instruction fetched from L3.75 shared </td><td> 2</td><td>	Group 59 pm_isource_L3</td>

</tr>

<tr><td>PM_INST_FROM_L375_MOD_GRP59</td><td> Instruction fetched from L3.75 modified </td><td> 3</td><td>	Group 59 pm_isource_L3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP59</td><td> Run instructions completed </td><td> 4</td><td>	Group 59 pm_isource_L3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP59</td><td> Run cycles </td><td> 5</td><td>	Group 59 pm_isource_L3</td>

</tr>

<tr><td>PM_PTEG_FROM_L25_SHR_GRP60</td><td> PTEG loaded from L2.5 shared </td><td> 0</td><td>	Group 60 pm_pteg_source1</td>

</tr>

<tr><td>PM_PTEG_FROM_L25_MOD_GRP60</td><td> PTEG loaded from L2.5 modified </td><td> 1</td><td>	Group 60 pm_pteg_source1</td>

</tr>

<tr><td>PM_PTEG_FROM_L275_SHR_GRP60</td><td> PTEG loaded from L2.75 shared </td><td> 2</td><td>	Group 60 pm_pteg_source1</td>

</tr>

<tr><td>PM_PTEG_FROM_L275_MOD_GRP60</td><td> PTEG loaded from L2.75 modified </td><td> 3</td><td>	Group 60 pm_pteg_source1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP60</td><td> Run instructions completed </td><td> 4</td><td>	Group 60 pm_pteg_source1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP60</td><td> Run cycles </td><td> 5</td><td>	Group 60 pm_pteg_source1</td>

</tr>

<tr><td>PM_PTEG_FROM_L35_SHR_GRP61</td><td> PTEG loaded from L3.5 shared </td><td> 0</td><td>	Group 61 pm_pteg_source2</td>

</tr>

<tr><td>PM_PTEG_FROM_L35_MOD_GRP61</td><td> PTEG loaded from L3.5 modified </td><td> 1</td><td>	Group 61 pm_pteg_source2</td>

</tr>

<tr><td>PM_PTEG_FROM_L375_SHR_GRP61</td><td> PTEG loaded from L3.75 shared </td><td> 2</td><td>	Group 61 pm_pteg_source2</td>

</tr>

<tr><td>PM_PTEG_FROM_L375_MOD_GRP61</td><td> PTEG loaded from L3.75 modified </td><td> 3</td><td>	Group 61 pm_pteg_source2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP61</td><td> Run instructions completed </td><td> 4</td><td>	Group 61 pm_pteg_source2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP61</td><td> Run cycles </td><td> 5</td><td>	Group 61 pm_pteg_source2</td>

</tr>

<tr><td>PM_PTEG_FROM_L2_GRP62</td><td> PTEG loaded from L2 </td><td> 0</td><td>	Group 62 pm_pteg_source3</td>

</tr>

<tr><td>PM_PTEG_FROM_LMEM_GRP62</td><td> PTEG loaded from local memory </td><td> 1</td><td>	Group 62 pm_pteg_source3</td>

</tr>

<tr><td>PM_PTEG_FROM_L2MISS_GRP62</td><td> PTEG loaded from L2 miss </td><td> 2</td><td>	Group 62 pm_pteg_source3</td>

</tr>

<tr><td>PM_PTEG_FROM_RMEM_GRP62</td><td> PTEG loaded from remote memory </td><td> 3</td><td>	Group 62 pm_pteg_source3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP62</td><td> Run instructions completed </td><td> 4</td><td>	Group 62 pm_pteg_source3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP62</td><td> Run cycles </td><td> 5</td><td>	Group 62 pm_pteg_source3</td>

</tr>

<tr><td>PM_PTEG_FROM_L3_GRP63</td><td> PTEG loaded from L3 </td><td> 0</td><td>	Group 63 pm_pteg_source4</td>

</tr>

<tr><td>PM_GRP_DISP_GRP63</td><td> Group dispatches </td><td> 1</td><td>	Group 63 pm_pteg_source4</td>

</tr>

<tr><td>PM_GRP_DISP_SUCCESS_GRP63</td><td> Group dispatch success </td><td> 2</td><td>	Group 63 pm_pteg_source4</td>

</tr>

<tr><td>PM_DC_INV_L2_GRP63</td><td> L1 D cache entries invalidated from L2 </td><td> 3</td><td>	Group 63 pm_pteg_source4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP63</td><td> Run instructions completed </td><td> 4</td><td>	Group 63 pm_pteg_source4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP63</td><td> Run cycles </td><td> 5</td><td>	Group 63 pm_pteg_source4</td>

</tr>

<tr><td>PM_L2SA_RCLD_DISP_GRP64</td><td> L2 Slice A RC load dispatch attempt </td><td> 0</td><td>	Group 64 pm_L2SA_ld</td>

</tr>

<tr><td>PM_L2SA_RCLD_DISP_FAIL_RC_FULL_GRP64</td><td> L2 Slice A RC load dispatch attempt failed due to all RC full </td><td> 1</td><td>	Group 64 pm_L2SA_ld</td>

</tr>

<tr><td>PM_L2SA_RCLD_DISP_FAIL_ADDR_GRP64</td><td> L2 Slice A RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ </td><td> 2</td><td>	Group 64 pm_L2SA_ld</td>

</tr>

<tr><td>PM_L2SA_RCLD_DISP_FAIL_OTHER_GRP64</td><td> L2 Slice A RC load dispatch attempt failed due to other reasons </td><td> 3</td><td>	Group 64 pm_L2SA_ld</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP64</td><td> Run instructions completed </td><td> 4</td><td>	Group 64 pm_L2SA_ld</td>

</tr>

<tr><td>PM_RUN_CYC_GRP64</td><td> Run cycles </td><td> 5</td><td>	Group 64 pm_L2SA_ld</td>

</tr>

<tr><td>PM_L2SA_RCST_DISP_GRP65</td><td> L2 Slice A RC store dispatch attempt </td><td> 0</td><td>	Group 65 pm_L2SA_st</td>

</tr>

<tr><td>PM_L2SA_RCST_DISP_FAIL_RC_FULL_GRP65</td><td> L2 Slice A RC store dispatch attempt failed due to all RC full </td><td> 1</td><td>	Group 65 pm_L2SA_st</td>

</tr>

<tr><td>PM_L2SA_RCST_DISP_FAIL_ADDR_GRP65</td><td> L2 Slice A RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ </td><td> 2</td><td>	Group 65 pm_L2SA_st</td>

</tr>

<tr><td>PM_L2SA_RCST_DISP_FAIL_OTHER_GRP65</td><td> L2 Slice A RC store dispatch attempt failed due to other reasons </td><td> 3</td><td>	Group 65 pm_L2SA_st</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP65</td><td> Run instructions completed </td><td> 4</td><td>	Group 65 pm_L2SA_st</td>

</tr>

<tr><td>PM_RUN_CYC_GRP65</td><td> Run cycles </td><td> 5</td><td>	Group 65 pm_L2SA_st</td>

</tr>

<tr><td>PM_L2SA_RC_DISP_FAIL_CO_BUSY_GRP66</td><td> L2 Slice A RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy </td><td> 0</td><td>	Group 66 pm_L2SA_st2</td>

</tr>

<tr><td>PM_L2SA_ST_REQ_GRP66</td><td> L2 slice A store requests </td><td> 1</td><td>	Group 66 pm_L2SA_st2</td>

</tr>

<tr><td>PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL_GRP66</td><td> L2 Slice A RC dispatch attempt failed due to all CO busy </td><td> 2</td><td>	Group 66 pm_L2SA_st2</td>

</tr>

<tr><td>PM_L2SA_ST_HIT_GRP66</td><td> L2 slice A store hits </td><td> 3</td><td>	Group 66 pm_L2SA_st2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP66</td><td> Run instructions completed </td><td> 4</td><td>	Group 66 pm_L2SA_st2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP66</td><td> Run cycles </td><td> 5</td><td>	Group 66 pm_L2SA_st2</td>

</tr>

<tr><td>PM_L2SB_RCLD_DISP_GRP67</td><td> L2 Slice B RC load dispatch attempt </td><td> 0</td><td>	Group 67 pm_L2SB_ld</td>

</tr>

<tr><td>PM_L2SB_RCLD_DISP_FAIL_RC_FULL_GRP67</td><td> L2 Slice B RC load dispatch attempt failed due to all RC full </td><td> 1</td><td>	Group 67 pm_L2SB_ld</td>

</tr>

<tr><td>PM_L2SB_RCLD_DISP_FAIL_ADDR_GRP67</td><td> L2 Slice B RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ </td><td> 2</td><td>	Group 67 pm_L2SB_ld</td>

</tr>

<tr><td>PM_L2SB_RCLD_DISP_FAIL_OTHER_GRP67</td><td> L2 Slice B RC load dispatch attempt failed due to other reasons </td><td> 3</td><td>	Group 67 pm_L2SB_ld</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP67</td><td> Run instructions completed </td><td> 4</td><td>	Group 67 pm_L2SB_ld</td>

</tr>

<tr><td>PM_RUN_CYC_GRP67</td><td> Run cycles </td><td> 5</td><td>	Group 67 pm_L2SB_ld</td>

</tr>

<tr><td>PM_L2SB_RCST_DISP_GRP68</td><td> L2 Slice B RC store dispatch attempt </td><td> 0</td><td>	Group 68 pm_L2SB_st</td>

</tr>

<tr><td>PM_L2SB_RCST_DISP_FAIL_RC_FULL_GRP68</td><td> L2 Slice B RC store dispatch attempt failed due to all RC full </td><td> 1</td><td>	Group 68 pm_L2SB_st</td>

</tr>

<tr><td>PM_L2SB_RCST_DISP_FAIL_ADDR_GRP68</td><td> L2 Slice B RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ </td><td> 2</td><td>	Group 68 pm_L2SB_st</td>

</tr>

<tr><td>PM_L2SB_RCST_DISP_FAIL_OTHER_GRP68</td><td> L2 Slice B RC store dispatch attempt failed due to other reasons </td><td> 3</td><td>	Group 68 pm_L2SB_st</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP68</td><td> Run instructions completed </td><td> 4</td><td>	Group 68 pm_L2SB_st</td>

</tr>

<tr><td>PM_RUN_CYC_GRP68</td><td> Run cycles </td><td> 5</td><td>	Group 68 pm_L2SB_st</td>

</tr>

<tr><td>PM_L2SB_RC_DISP_FAIL_CO_BUSY_GRP69</td><td> L2 Slice B RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy </td><td> 0</td><td>	Group 69 pm_L2SB_st2</td>

</tr>

<tr><td>PM_L2SB_ST_REQ_GRP69</td><td> L2 slice B store requests </td><td> 1</td><td>	Group 69 pm_L2SB_st2</td>

</tr>

<tr><td>PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL_GRP69</td><td> L2 Slice B RC dispatch attempt failed due to all CO busy </td><td> 2</td><td>	Group 69 pm_L2SB_st2</td>

</tr>

<tr><td>PM_L2SB_ST_HIT_GRP69</td><td> L2 slice B store hits </td><td> 3</td><td>	Group 69 pm_L2SB_st2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP69</td><td> Run instructions completed </td><td> 4</td><td>	Group 69 pm_L2SB_st2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP69</td><td> Run cycles </td><td> 5</td><td>	Group 69 pm_L2SB_st2</td>

</tr>

<tr><td>PM_L2SC_RCLD_DISP_GRP70</td><td> L2 Slice C RC load dispatch attempt </td><td> 0</td><td>	Group 70 pm_L2SB_ld</td>

</tr>

<tr><td>PM_L2SC_RCLD_DISP_FAIL_RC_FULL_GRP70</td><td> L2 Slice C RC load dispatch attempt failed due to all RC full </td><td> 1</td><td>	Group 70 pm_L2SB_ld</td>

</tr>

<tr><td>PM_L2SC_RCLD_DISP_FAIL_ADDR_GRP70</td><td> L2 Slice C RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ </td><td> 2</td><td>	Group 70 pm_L2SB_ld</td>

</tr>

<tr><td>PM_L2SC_RCLD_DISP_FAIL_OTHER_GRP70</td><td> L2 Slice C RC load dispatch attempt failed due to other reasons </td><td> 3</td><td>	Group 70 pm_L2SB_ld</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP70</td><td> Run instructions completed </td><td> 4</td><td>	Group 70 pm_L2SB_ld</td>

</tr>

<tr><td>PM_RUN_CYC_GRP70</td><td> Run cycles </td><td> 5</td><td>	Group 70 pm_L2SB_ld</td>

</tr>

<tr><td>PM_L2SC_RCST_DISP_GRP71</td><td> L2 Slice C RC store dispatch attempt </td><td> 0</td><td>	Group 71 pm_L2SB_st</td>

</tr>

<tr><td>PM_L2SC_RCST_DISP_FAIL_RC_FULL_GRP71</td><td> L2 Slice C RC store dispatch attempt failed due to all RC full </td><td> 1</td><td>	Group 71 pm_L2SB_st</td>

</tr>

<tr><td>PM_L2SC_RCST_DISP_FAIL_ADDR_GRP71</td><td> L2 Slice C RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ </td><td> 2</td><td>	Group 71 pm_L2SB_st</td>

</tr>

<tr><td>PM_L2SC_RCST_DISP_FAIL_OTHER_GRP71</td><td> L2 Slice C RC store dispatch attempt failed due to other reasons </td><td> 3</td><td>	Group 71 pm_L2SB_st</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP71</td><td> Run instructions completed </td><td> 4</td><td>	Group 71 pm_L2SB_st</td>

</tr>

<tr><td>PM_RUN_CYC_GRP71</td><td> Run cycles </td><td> 5</td><td>	Group 71 pm_L2SB_st</td>

</tr>

<tr><td>PM_L2SC_RC_DISP_FAIL_CO_BUSY_GRP72</td><td> L2 Slice C RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy </td><td> 0</td><td>	Group 72 pm_L2SB_st2</td>

</tr>

<tr><td>PM_L2SC_ST_REQ_GRP72</td><td> L2 slice C store requests </td><td> 1</td><td>	Group 72 pm_L2SB_st2</td>

</tr>

<tr><td>PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL_GRP72</td><td> L2 Slice C RC dispatch attempt failed due to all CO busy </td><td> 2</td><td>	Group 72 pm_L2SB_st2</td>

</tr>

<tr><td>PM_L2SC_ST_HIT_GRP72</td><td> L2 slice C store hits </td><td> 3</td><td>	Group 72 pm_L2SB_st2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP72</td><td> Run instructions completed </td><td> 4</td><td>	Group 72 pm_L2SB_st2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP72</td><td> Run cycles </td><td> 5</td><td>	Group 72 pm_L2SB_st2</td>

</tr>

<tr><td>PM_L3SA_MOD_TAG_GRP73</td><td> L3 slice A transition from modified to TAG </td><td> 0</td><td>	Group 73 pm_L3SA_trans</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP73</td><td> IOPS instructions completed </td><td> 1</td><td>	Group 73 pm_L3SA_trans</td>

</tr>

<tr><td>PM_L3SA_MOD_INV_GRP73</td><td> L3 slice A transition from modified to invalid </td><td> 2</td><td>	Group 73 pm_L3SA_trans</td>

</tr>

<tr><td>PM_L3SA_SHR_INV_GRP73</td><td> L3 slice A transition from shared to invalid </td><td> 3</td><td>	Group 73 pm_L3SA_trans</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP73</td><td> Run instructions completed </td><td> 4</td><td>	Group 73 pm_L3SA_trans</td>

</tr>

<tr><td>PM_RUN_CYC_GRP73</td><td> Run cycles </td><td> 5</td><td>	Group 73 pm_L3SA_trans</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP74</td><td> IOPS instructions completed </td><td> 0</td><td>	Group 74 pm_L3SB_trans</td>

</tr>

<tr><td>PM_L3SB_MOD_TAG_GRP74</td><td> L3 slice B transition from modified to TAG </td><td> 1</td><td>	Group 74 pm_L3SB_trans</td>

</tr>

<tr><td>PM_L3SB_MOD_INV_GRP74</td><td> L3 slice B transition from modified to invalid </td><td> 2</td><td>	Group 74 pm_L3SB_trans</td>

</tr>

<tr><td>PM_L3SB_SHR_INV_GRP74</td><td> L3 slice B transition from shared to invalid </td><td> 3</td><td>	Group 74 pm_L3SB_trans</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP74</td><td> Run instructions completed </td><td> 4</td><td>	Group 74 pm_L3SB_trans</td>

</tr>

<tr><td>PM_RUN_CYC_GRP74</td><td> Run cycles </td><td> 5</td><td>	Group 74 pm_L3SB_trans</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP75</td><td> IOPS instructions completed </td><td> 0</td><td>	Group 75 pm_L3SC_trans</td>

</tr>

<tr><td>PM_L3SC_MOD_TAG_GRP75</td><td> L3 slice C transition from modified to TAG </td><td> 1</td><td>	Group 75 pm_L3SC_trans</td>

</tr>

<tr><td>PM_L3SC_MOD_INV_GRP75</td><td> L3 slice C transition from modified to invalid </td><td> 2</td><td>	Group 75 pm_L3SC_trans</td>

</tr>

<tr><td>PM_L3SC_SHR_INV_GRP75</td><td> L3 slice C transition from shared to invalid </td><td> 3</td><td>	Group 75 pm_L3SC_trans</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP75</td><td> Run instructions completed </td><td> 4</td><td>	Group 75 pm_L3SC_trans</td>

</tr>

<tr><td>PM_RUN_CYC_GRP75</td><td> Run cycles </td><td> 5</td><td>	Group 75 pm_L3SC_trans</td>

</tr>

<tr><td>PM_L2SA_MOD_TAG_GRP76</td><td> L2 slice A transition from modified to tagged </td><td> 0</td><td>	Group 76 pm_L2SA_trans</td>

</tr>

<tr><td>PM_L2SA_SHR_MOD_GRP76</td><td> L2 slice A transition from shared to modified </td><td> 1</td><td>	Group 76 pm_L2SA_trans</td>

</tr>

<tr><td>PM_L2SA_MOD_INV_GRP76</td><td> L2 slice A transition from modified to invalid </td><td> 2</td><td>	Group 76 pm_L2SA_trans</td>

</tr>

<tr><td>PM_L2SA_SHR_INV_GRP76</td><td> L2 slice A transition from shared to invalid </td><td> 3</td><td>	Group 76 pm_L2SA_trans</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP76</td><td> Run instructions completed </td><td> 4</td><td>	Group 76 pm_L2SA_trans</td>

</tr>

<tr><td>PM_RUN_CYC_GRP76</td><td> Run cycles </td><td> 5</td><td>	Group 76 pm_L2SA_trans</td>

</tr>

<tr><td>PM_L2SB_MOD_TAG_GRP77</td><td> L2 slice B transition from modified to tagged </td><td> 0</td><td>	Group 77 pm_L2SB_trans</td>

</tr>

<tr><td>PM_L2SB_SHR_MOD_GRP77</td><td> L2 slice B transition from shared to modified </td><td> 1</td><td>	Group 77 pm_L2SB_trans</td>

</tr>

<tr><td>PM_L2SB_MOD_INV_GRP77</td><td> L2 slice B transition from modified to invalid </td><td> 2</td><td>	Group 77 pm_L2SB_trans</td>

</tr>

<tr><td>PM_L2SB_SHR_INV_GRP77</td><td> L2 slice B transition from shared to invalid </td><td> 3</td><td>	Group 77 pm_L2SB_trans</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP77</td><td> Run instructions completed </td><td> 4</td><td>	Group 77 pm_L2SB_trans</td>

</tr>

<tr><td>PM_RUN_CYC_GRP77</td><td> Run cycles </td><td> 5</td><td>	Group 77 pm_L2SB_trans</td>

</tr>

<tr><td>PM_L2SC_MOD_TAG_GRP78</td><td> L2 slice C transition from modified to tagged </td><td> 0</td><td>	Group 78 pm_L2SC_trans</td>

</tr>

<tr><td>PM_L2SC_SHR_MOD_GRP78</td><td> L2 slice C transition from shared to modified </td><td> 1</td><td>	Group 78 pm_L2SC_trans</td>

</tr>

<tr><td>PM_L2SC_MOD_INV_GRP78</td><td> L2 slice C transition from modified to invalid </td><td> 2</td><td>	Group 78 pm_L2SC_trans</td>

</tr>

<tr><td>PM_L2SC_SHR_INV_GRP78</td><td> L2 slice C transition from shared to invalid </td><td> 3</td><td>	Group 78 pm_L2SC_trans</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP78</td><td> Run instructions completed </td><td> 4</td><td>	Group 78 pm_L2SC_trans</td>

</tr>

<tr><td>PM_RUN_CYC_GRP78</td><td> Run cycles </td><td> 5</td><td>	Group 78 pm_L2SC_trans</td>

</tr>

<tr><td>PM_L3SA_ALL_BUSY_GRP79</td><td> L3 slice A active for every cycle all CI/CO machines busy </td><td> 0</td><td>	Group 79 pm_L3SAB_retry</td>

</tr>

<tr><td>PM_L3SB_ALL_BUSY_GRP79</td><td> L3 slice B active for every cycle all CI/CO machines busy </td><td> 1</td><td>	Group 79 pm_L3SAB_retry</td>

</tr>

<tr><td>PM_L3SA_SNOOP_RETRY_GRP79</td><td> L3 slice A snoop retries </td><td> 2</td><td>	Group 79 pm_L3SAB_retry</td>

</tr>

<tr><td>PM_L3SB_SNOOP_RETRY_GRP79</td><td> L3 slice B snoop retries </td><td> 3</td><td>	Group 79 pm_L3SAB_retry</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP79</td><td> Run instructions completed </td><td> 4</td><td>	Group 79 pm_L3SAB_retry</td>

</tr>

<tr><td>PM_RUN_CYC_GRP79</td><td> Run cycles </td><td> 5</td><td>	Group 79 pm_L3SAB_retry</td>

</tr>

<tr><td>PM_L3SA_REF_GRP80</td><td> L3 slice A references </td><td> 0</td><td>	Group 80 pm_L3SAB_hit</td>

</tr>

<tr><td>PM_L3SB_REF_GRP80</td><td> L3 slice B references </td><td> 1</td><td>	Group 80 pm_L3SAB_hit</td>

</tr>

<tr><td>PM_L3SA_HIT_GRP80</td><td> L3 slice A hits </td><td> 2</td><td>	Group 80 pm_L3SAB_hit</td>

</tr>

<tr><td>PM_L3SB_HIT_GRP80</td><td> L3 slice B hits </td><td> 3</td><td>	Group 80 pm_L3SAB_hit</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP80</td><td> Run instructions completed </td><td> 4</td><td>	Group 80 pm_L3SAB_hit</td>

</tr>

<tr><td>PM_RUN_CYC_GRP80</td><td> Run cycles </td><td> 5</td><td>	Group 80 pm_L3SAB_hit</td>

</tr>

<tr><td>PM_L3SC_ALL_BUSY_GRP81</td><td> L3 slice C active for every cycle all CI/CO machines busy </td><td> 0</td><td>	Group 81 pm_L3SC_retry_hit</td>

</tr>

<tr><td>PM_L3SC_REF_GRP81</td><td> L3 slice C references </td><td> 1</td><td>	Group 81 pm_L3SC_retry_hit</td>

</tr>

<tr><td>PM_L3SC_SNOOP_RETRY_GRP81</td><td> L3 slice C snoop retries </td><td> 2</td><td>	Group 81 pm_L3SC_retry_hit</td>

</tr>

<tr><td>PM_L3SC_HIT_GRP81</td><td> L3 Slice C hits </td><td> 3</td><td>	Group 81 pm_L3SC_retry_hit</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP81</td><td> Run instructions completed </td><td> 4</td><td>	Group 81 pm_L3SC_retry_hit</td>

</tr>

<tr><td>PM_RUN_CYC_GRP81</td><td> Run cycles </td><td> 5</td><td>	Group 81 pm_L3SC_retry_hit</td>

</tr>

<tr><td>PM_FPU_FDIV_GRP82</td><td> FPU executed FDIV instruction </td><td> 0</td><td>	Group 82 pm_fpu1</td>

</tr>

<tr><td>PM_FPU_FMA_GRP82</td><td> FPU executed multiply-add instruction </td><td> 1</td><td>	Group 82 pm_fpu1</td>

</tr>

<tr><td>PM_FPU_FMOV_FEST_GRP82</td><td> FPU executing FMOV or FEST instructions </td><td> 2</td><td>	Group 82 pm_fpu1</td>

</tr>

<tr><td>PM_FPU_FEST_GRP82</td><td> FPU executed FEST instruction </td><td> 3</td><td>	Group 82 pm_fpu1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP82</td><td> Run instructions completed </td><td> 4</td><td>	Group 82 pm_fpu1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP82</td><td> Run cycles </td><td> 5</td><td>	Group 82 pm_fpu1</td>

</tr>

<tr><td>PM_FPU_1FLOP_GRP83</td><td> FPU executed one flop instruction  </td><td> 0</td><td>	Group 83 pm_fpu2</td>

</tr>

<tr><td>PM_FPU_FSQRT_GRP83</td><td> FPU executed FSQRT instruction </td><td> 1</td><td>	Group 83 pm_fpu2</td>

</tr>

<tr><td>PM_FPU_FRSP_FCONV_GRP83</td><td> FPU executed FRSP or FCONV instructions </td><td> 2</td><td>	Group 83 pm_fpu2</td>

</tr>

<tr><td>PM_FPU_FIN_GRP83</td><td> FPU produced a result </td><td> 3</td><td>	Group 83 pm_fpu2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP83</td><td> Run instructions completed </td><td> 4</td><td>	Group 83 pm_fpu2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP83</td><td> Run cycles </td><td> 5</td><td>	Group 83 pm_fpu2</td>

</tr>

<tr><td>PM_FPU_DENORM_GRP84</td><td> FPU received denormalized data </td><td> 0</td><td>	Group 84 pm_fpu3</td>

</tr>

<tr><td>PM_FPU_STALL3_GRP84</td><td> FPU stalled in pipe3 </td><td> 1</td><td>	Group 84 pm_fpu3</td>

</tr>

<tr><td>PM_FPU0_FIN_GRP84</td><td> FPU0 produced a result </td><td> 2</td><td>	Group 84 pm_fpu3</td>

</tr>

<tr><td>PM_FPU1_FIN_GRP84</td><td> FPU1 produced a result </td><td> 3</td><td>	Group 84 pm_fpu3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP84</td><td> Run instructions completed </td><td> 4</td><td>	Group 84 pm_fpu3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP84</td><td> Run cycles </td><td> 5</td><td>	Group 84 pm_fpu3</td>

</tr>

<tr><td>PM_FPU_SINGLE_GRP85</td><td> FPU executed single precision instruction </td><td> 0</td><td>	Group 85 pm_fpu4</td>

</tr>

<tr><td>PM_FPU_STF_GRP85</td><td> FPU executed store instruction </td><td> 1</td><td>	Group 85 pm_fpu4</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP85</td><td> IOPS instructions completed </td><td> 2</td><td>	Group 85 pm_fpu4</td>

</tr>

<tr><td>PM_LSU_LDF_GRP85</td><td> LSU executed Floating Point load instruction </td><td> 3</td><td>	Group 85 pm_fpu4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP85</td><td> Run instructions completed </td><td> 4</td><td>	Group 85 pm_fpu4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP85</td><td> Run cycles </td><td> 5</td><td>	Group 85 pm_fpu4</td>

</tr>

<tr><td>PM_FPU0_FSQRT_GRP86</td><td> FPU0 executed FSQRT instruction </td><td> 0</td><td>	Group 86 pm_fpu5</td>

</tr>

<tr><td>PM_FPU1_FSQRT_GRP86</td><td> FPU1 executed FSQRT instruction </td><td> 1</td><td>	Group 86 pm_fpu5</td>

</tr>

<tr><td>PM_FPU0_FEST_GRP86</td><td> FPU0 executed FEST instruction </td><td> 2</td><td>	Group 86 pm_fpu5</td>

</tr>

<tr><td>PM_FPU1_FEST_GRP86</td><td> FPU1 executed FEST instruction </td><td> 3</td><td>	Group 86 pm_fpu5</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP86</td><td> Run instructions completed </td><td> 4</td><td>	Group 86 pm_fpu5</td>

</tr>

<tr><td>PM_RUN_CYC_GRP86</td><td> Run cycles </td><td> 5</td><td>	Group 86 pm_fpu5</td>

</tr>

<tr><td>PM_FPU0_DENORM_GRP87</td><td> FPU0 received denormalized data </td><td> 0</td><td>	Group 87 pm_fpu6</td>

</tr>

<tr><td>PM_FPU1_DENORM_GRP87</td><td> FPU1 received denormalized data </td><td> 1</td><td>	Group 87 pm_fpu6</td>

</tr>

<tr><td>PM_FPU0_FMOV_FEST_GRP87</td><td> FPU0 executed FMOV or FEST instructions </td><td> 2</td><td>	Group 87 pm_fpu6</td>

</tr>

<tr><td>PM_FPU1_FMOV_FEST_GRP87</td><td> FPU1 executing FMOV or FEST instructions </td><td> 3</td><td>	Group 87 pm_fpu6</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP87</td><td> Run instructions completed </td><td> 4</td><td>	Group 87 pm_fpu6</td>

</tr>

<tr><td>PM_RUN_CYC_GRP87</td><td> Run cycles </td><td> 5</td><td>	Group 87 pm_fpu6</td>

</tr>

<tr><td>PM_FPU0_FDIV_GRP88</td><td> FPU0 executed FDIV instruction </td><td> 0</td><td>	Group 88 pm_fpu7</td>

</tr>

<tr><td>PM_FPU1_FDIV_GRP88</td><td> FPU1 executed FDIV instruction </td><td> 1</td><td>	Group 88 pm_fpu7</td>

</tr>

<tr><td>PM_FPU0_FRSP_FCONV_GRP88</td><td> FPU0 executed FRSP or FCONV instructions </td><td> 2</td><td>	Group 88 pm_fpu7</td>

</tr>

<tr><td>PM_FPU1_FRSP_FCONV_GRP88</td><td> FPU1 executed FRSP or FCONV instructions </td><td> 3</td><td>	Group 88 pm_fpu7</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP88</td><td> Run instructions completed </td><td> 4</td><td>	Group 88 pm_fpu7</td>

</tr>

<tr><td>PM_RUN_CYC_GRP88</td><td> Run cycles </td><td> 5</td><td>	Group 88 pm_fpu7</td>

</tr>

<tr><td>PM_FPU0_STALL3_GRP89</td><td> FPU0 stalled in pipe3 </td><td> 0</td><td>	Group 89 pm_fpu8</td>

</tr>

<tr><td>PM_FPU1_STALL3_GRP89</td><td> FPU1 stalled in pipe3 </td><td> 1</td><td>	Group 89 pm_fpu8</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP89</td><td> IOPS instructions completed </td><td> 2</td><td>	Group 89 pm_fpu8</td>

</tr>

<tr><td>PM_FPU0_FPSCR_GRP89</td><td> FPU0 executed FPSCR instruction </td><td> 3</td><td>	Group 89 pm_fpu8</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP89</td><td> Run instructions completed </td><td> 4</td><td>	Group 89 pm_fpu8</td>

</tr>

<tr><td>PM_RUN_CYC_GRP89</td><td> Run cycles </td><td> 5</td><td>	Group 89 pm_fpu8</td>

</tr>

<tr><td>PM_FPU0_SINGLE_GRP90</td><td> FPU0 executed single precision instruction </td><td> 0</td><td>	Group 90 pm_fpu9</td>

</tr>

<tr><td>PM_FPU1_SINGLE_GRP90</td><td> FPU1 executed single precision instruction </td><td> 1</td><td>	Group 90 pm_fpu9</td>

</tr>

<tr><td>PM_LSU0_LDF_GRP90</td><td> LSU0 executed Floating Point load instruction </td><td> 2</td><td>	Group 90 pm_fpu9</td>

</tr>

<tr><td>PM_LSU1_LDF_GRP90</td><td> LSU1 executed Floating Point load instruction </td><td> 3</td><td>	Group 90 pm_fpu9</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP90</td><td> Run instructions completed </td><td> 4</td><td>	Group 90 pm_fpu9</td>

</tr>

<tr><td>PM_RUN_CYC_GRP90</td><td> Run cycles </td><td> 5</td><td>	Group 90 pm_fpu9</td>

</tr>

<tr><td>PM_FPU0_FMA_GRP91</td><td> FPU0 executed multiply-add instruction </td><td> 0</td><td>	Group 91 pm_fpu10</td>

</tr>

<tr><td>PM_FPU1_FMA_GRP91</td><td> FPU1 executed multiply-add instruction </td><td> 1</td><td>	Group 91 pm_fpu10</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP91</td><td> IOPS instructions completed </td><td> 2</td><td>	Group 91 pm_fpu10</td>

</tr>

<tr><td>PM_FPU1_FRSP_FCONV_GRP91</td><td> FPU1 executed FRSP or FCONV instructions </td><td> 3</td><td>	Group 91 pm_fpu10</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP91</td><td> Run instructions completed </td><td> 4</td><td>	Group 91 pm_fpu10</td>

</tr>

<tr><td>PM_RUN_CYC_GRP91</td><td> Run cycles </td><td> 5</td><td>	Group 91 pm_fpu10</td>

</tr>

<tr><td>PM_FPU0_1FLOP_GRP92</td><td> FPU0 executed add, mult, sub, cmp or sel instruction </td><td> 0</td><td>	Group 92 pm_fpu11</td>

</tr>

<tr><td>PM_FPU1_1FLOP_GRP92</td><td> FPU1 executed add, mult, sub, cmp or sel instruction </td><td> 1</td><td>	Group 92 pm_fpu11</td>

</tr>

<tr><td>PM_FPU0_FIN_GRP92</td><td> FPU0 produced a result </td><td> 2</td><td>	Group 92 pm_fpu11</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP92</td><td> IOPS instructions completed </td><td> 3</td><td>	Group 92 pm_fpu11</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP92</td><td> Run instructions completed </td><td> 4</td><td>	Group 92 pm_fpu11</td>

</tr>

<tr><td>PM_RUN_CYC_GRP92</td><td> Run cycles </td><td> 5</td><td>	Group 92 pm_fpu11</td>

</tr>

<tr><td>PM_FPU0_STF_GRP93</td><td> FPU0 executed store instruction </td><td> 0</td><td>	Group 93 pm_fpu12</td>

</tr>

<tr><td>PM_FPU1_STF_GRP93</td><td> FPU1 executed store instruction </td><td> 1</td><td>	Group 93 pm_fpu12</td>

</tr>

<tr><td>PM_LSU0_LDF_GRP93</td><td> LSU0 executed Floating Point load instruction </td><td> 2</td><td>	Group 93 pm_fpu12</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP93</td><td> IOPS instructions completed </td><td> 3</td><td>	Group 93 pm_fpu12</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP93</td><td> Run instructions completed </td><td> 4</td><td>	Group 93 pm_fpu12</td>

</tr>

<tr><td>PM_RUN_CYC_GRP93</td><td> Run cycles </td><td> 5</td><td>	Group 93 pm_fpu12</td>

</tr>

<tr><td>PM_FXU_IDLE_GRP94</td><td> FXU idle </td><td> 0</td><td>	Group 94 pm_fxu1</td>

</tr>

<tr><td>PM_FXU_BUSY_GRP94</td><td> FXU busy </td><td> 1</td><td>	Group 94 pm_fxu1</td>

</tr>

<tr><td>PM_FXU0_BUSY_FXU1_IDLE_GRP94</td><td> FXU0 busy FXU1 idle </td><td> 2</td><td>	Group 94 pm_fxu1</td>

</tr>

<tr><td>PM_FXU1_BUSY_FXU0_IDLE_GRP94</td><td> FXU1 busy FXU0 idle </td><td> 3</td><td>	Group 94 pm_fxu1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP94</td><td> Run instructions completed </td><td> 4</td><td>	Group 94 pm_fxu1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP94</td><td> Run cycles </td><td> 5</td><td>	Group 94 pm_fxu1</td>

</tr>

<tr><td>PM_MRK_GRP_DISP_GRP95</td><td> Marked group dispatched </td><td> 0</td><td>	Group 95 pm_fxu2</td>

</tr>

<tr><td>PM_MRK_GRP_BR_REDIR_GRP95</td><td> Group experienced marked branch redirect </td><td> 1</td><td>	Group 95 pm_fxu2</td>

</tr>

<tr><td>PM_FXU_FIN_GRP95</td><td> FXU produced a result </td><td> 2</td><td>	Group 95 pm_fxu2</td>

</tr>

<tr><td>PM_FXLS_FULL_CYC_GRP95</td><td> Cycles FXLS queue is full </td><td> 3</td><td>	Group 95 pm_fxu2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP95</td><td> Run instructions completed </td><td> 4</td><td>	Group 95 pm_fxu2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP95</td><td> Run cycles </td><td> 5</td><td>	Group 95 pm_fxu2</td>

</tr>

<tr><td>PM_3INST_CLB_CYC_GRP96</td><td> Cycles 3 instructions in CLB </td><td> 0</td><td>	Group 96 pm_fxu3</td>

</tr>

<tr><td>PM_4INST_CLB_CYC_GRP96</td><td> Cycles 4 instructions in CLB </td><td> 1</td><td>	Group 96 pm_fxu3</td>

</tr>

<tr><td>PM_FXU0_FIN_GRP96</td><td> FXU0 produced a result </td><td> 2</td><td>	Group 96 pm_fxu3</td>

</tr>

<tr><td>PM_FXU1_FIN_GRP96</td><td> FXU1 produced a result </td><td> 3</td><td>	Group 96 pm_fxu3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP96</td><td> Run instructions completed </td><td> 4</td><td>	Group 96 pm_fxu3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP96</td><td> Run cycles </td><td> 5</td><td>	Group 96 pm_fxu3</td>

</tr>

<tr><td>PM_THRD_PRIO_4_CYC_GRP97</td><td> Cycles thread running at priority level 4 </td><td> 0</td><td>	Group 97 pm_smt_priorities1</td>

</tr>

<tr><td>PM_THRD_PRIO_7_CYC_GRP97</td><td> Cycles thread running at priority level 7 </td><td> 1</td><td>	Group 97 pm_smt_priorities1</td>

</tr>

<tr><td>PM_THRD_PRIO_DIFF_0_CYC_GRP97</td><td> Cycles no thread priority difference </td><td> 2</td><td>	Group 97 pm_smt_priorities1</td>

</tr>

<tr><td>PM_THRD_PRIO_DIFF_1or2_CYC_GRP97</td><td> Cycles thread priority difference is 1 or 2 </td><td> 3</td><td>	Group 97 pm_smt_priorities1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP97</td><td> Run instructions completed </td><td> 4</td><td>	Group 97 pm_smt_priorities1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP97</td><td> Run cycles </td><td> 5</td><td>	Group 97 pm_smt_priorities1</td>

</tr>

<tr><td>PM_THRD_PRIO_3_CYC_GRP98</td><td> Cycles thread running at priority level 3 </td><td> 0</td><td>	Group 98 pm_smt_priorities2</td>

</tr>

<tr><td>PM_THRD_PRIO_6_CYC_GRP98</td><td> Cycles thread running at priority level 6 </td><td> 1</td><td>	Group 98 pm_smt_priorities2</td>

</tr>

<tr><td>PM_THRD_PRIO_DIFF_3or4_CYC_GRP98</td><td> Cycles thread priority difference is 3 or 4 </td><td> 2</td><td>	Group 98 pm_smt_priorities2</td>

</tr>

<tr><td>PM_THRD_PRIO_DIFF_5or6_CYC_GRP98</td><td> Cycles thread priority difference is 5 or 6 </td><td> 3</td><td>	Group 98 pm_smt_priorities2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP98</td><td> Run instructions completed </td><td> 4</td><td>	Group 98 pm_smt_priorities2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP98</td><td> Run cycles </td><td> 5</td><td>	Group 98 pm_smt_priorities2</td>

</tr>

<tr><td>PM_THRD_PRIO_2_CYC_GRP99</td><td> Cycles thread running at priority level 2 </td><td> 0</td><td>	Group 99 pm_smt_priorities3</td>

</tr>

<tr><td>PM_THRD_PRIO_5_CYC_GRP99</td><td> Cycles thread running at priority level 5 </td><td> 1</td><td>	Group 99 pm_smt_priorities3</td>

</tr>

<tr><td>PM_THRD_PRIO_DIFF_minus1or2_CYC_GRP99</td><td> Cycles thread priority difference is -1 or -2 </td><td> 2</td><td>	Group 99 pm_smt_priorities3</td>

</tr>

<tr><td>PM_THRD_PRIO_DIFF_minus3or4_CYC_GRP99</td><td> Cycles thread priority difference is -3 or -4 </td><td> 3</td><td>	Group 99 pm_smt_priorities3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP99</td><td> Run instructions completed </td><td> 4</td><td>	Group 99 pm_smt_priorities3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP99</td><td> Run cycles </td><td> 5</td><td>	Group 99 pm_smt_priorities3</td>

</tr>

<tr><td>PM_THRD_PRIO_1_CYC_GRP100</td><td> Cycles thread running at priority level 1 </td><td> 0</td><td>	Group 100 pm_smt_priorities4</td>

</tr>

<tr><td>PM_HV_CYC_GRP100</td><td> Hypervisor Cycles </td><td> 1</td><td>	Group 100 pm_smt_priorities4</td>

</tr>

<tr><td>PM_THRD_PRIO_DIFF_minus5or6_CYC_GRP100</td><td> Cycles thread priority difference is -5 or -6 </td><td> 2</td><td>	Group 100 pm_smt_priorities4</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP100</td><td> IOPS instructions completed </td><td> 3</td><td>	Group 100 pm_smt_priorities4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP100</td><td> Run instructions completed </td><td> 4</td><td>	Group 100 pm_smt_priorities4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP100</td><td> Run cycles </td><td> 5</td><td>	Group 100 pm_smt_priorities4</td>

</tr>

<tr><td>PM_THRD_ONE_RUN_CYC_GRP101</td><td> One of the threads in run cycles </td><td> 0</td><td>	Group 101 pm_smt_both</td>

</tr>

<tr><td>PM_THRD_GRP_CMPL_BOTH_CYC_GRP101</td><td> Cycles group completed by both threads </td><td> 1</td><td>	Group 101 pm_smt_both</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP101</td><td> IOPS instructions completed </td><td> 2</td><td>	Group 101 pm_smt_both</td>

</tr>

<tr><td>PM_THRD_L2MISS_BOTH_CYC_GRP101</td><td> Cycles both threads in L2 misses </td><td> 3</td><td>	Group 101 pm_smt_both</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP101</td><td> Run instructions completed </td><td> 4</td><td>	Group 101 pm_smt_both</td>

</tr>

<tr><td>PM_RUN_CYC_GRP101</td><td> Run cycles </td><td> 5</td><td>	Group 101 pm_smt_both</td>

</tr>

<tr><td>PM_SNOOP_TLBIE_GRP102</td><td> Snoop TLBIE </td><td> 0</td><td>	Group 102 pm_smt_selection</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP102</td><td> IOPS instructions completed </td><td> 1</td><td>	Group 102 pm_smt_selection</td>

</tr>

<tr><td>PM_THRD_SEL_T0_GRP102</td><td> Decode selected thread 0 </td><td> 2</td><td>	Group 102 pm_smt_selection</td>

</tr>

<tr><td>PM_THRD_SEL_T1_GRP102</td><td> Decode selected thread 1 </td><td> 3</td><td>	Group 102 pm_smt_selection</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP102</td><td> Run instructions completed </td><td> 4</td><td>	Group 102 pm_smt_selection</td>

</tr>

<tr><td>PM_RUN_CYC_GRP102</td><td> Run cycles </td><td> 5</td><td>	Group 102 pm_smt_selection</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP103</td><td> IOPS instructions completed </td><td> 0</td><td>	Group 103 pm_smt_selectover1</td>

</tr>

<tr><td>PM_0INST_CLB_CYC_GRP103</td><td> Cycles no instructions in CLB </td><td> 1</td><td>	Group 103 pm_smt_selectover1</td>

</tr>

<tr><td>PM_THRD_SEL_OVER_CLB_EMPTY_GRP103</td><td> Thread selection overides caused by CLB empty </td><td> 2</td><td>	Group 103 pm_smt_selectover1</td>

</tr>

<tr><td>PM_THRD_SEL_OVER_GCT_IMBAL_GRP103</td><td> Thread selection overides caused by GCT imbalance </td><td> 3</td><td>	Group 103 pm_smt_selectover1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP103</td><td> Run instructions completed </td><td> 4</td><td>	Group 103 pm_smt_selectover1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP103</td><td> Run cycles </td><td> 5</td><td>	Group 103 pm_smt_selectover1</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP104</td><td> IOPS instructions completed </td><td> 0</td><td>	Group 104 pm_smt_selectover2</td>

</tr>

<tr><td>PM_CYC_GRP104</td><td> Processor cycles </td><td> 1</td><td>	Group 104 pm_smt_selectover2</td>

</tr>

<tr><td>PM_THRD_SEL_OVER_ISU_HOLD_GRP104</td><td> Thread selection overides caused by ISU holds </td><td> 2</td><td>	Group 104 pm_smt_selectover2</td>

</tr>

<tr><td>PM_THRD_SEL_OVER_L2MISS_GRP104</td><td> Thread selection overides caused by L2 misses </td><td> 3</td><td>	Group 104 pm_smt_selectover2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP104</td><td> Run instructions completed </td><td> 4</td><td>	Group 104 pm_smt_selectover2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP104</td><td> Run cycles </td><td> 5</td><td>	Group 104 pm_smt_selectover2</td>

</tr>

<tr><td>PM_FAB_CMD_ISSUED_GRP105</td><td> Fabric command issued </td><td> 0</td><td>	Group 105 pm_fabric1</td>

</tr>

<tr><td>PM_FAB_DCLAIM_ISSUED_GRP105</td><td> dclaim issued </td><td> 1</td><td>	Group 105 pm_fabric1</td>

</tr>

<tr><td>PM_FAB_CMD_RETRIED_GRP105</td><td> Fabric command retried </td><td> 2</td><td>	Group 105 pm_fabric1</td>

</tr>

<tr><td>PM_FAB_DCLAIM_RETRIED_GRP105</td><td> dclaim retried </td><td> 3</td><td>	Group 105 pm_fabric1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP105</td><td> Run instructions completed </td><td> 4</td><td>	Group 105 pm_fabric1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP105</td><td> Run cycles </td><td> 5</td><td>	Group 105 pm_fabric1</td>

</tr>

<tr><td>PM_FAB_P1toM1_SIDECAR_EMPTY_GRP106</td><td> P1 to M1 sidecar empty </td><td> 0</td><td>	Group 106 pm_fabric2</td>

</tr>

<tr><td>PM_FAB_HOLDtoVN_EMPTY_GRP106</td><td> Hold buffer to VN empty </td><td> 1</td><td>	Group 106 pm_fabric2</td>

</tr>

<tr><td>PM_FAB_P1toVNorNN_SIDECAR_EMPTY_GRP106</td><td> P1 to VN/NN sidecar empty </td><td> 2</td><td>	Group 106 pm_fabric2</td>

</tr>

<tr><td>PM_FAB_VBYPASS_EMPTY_GRP106</td><td> Vertical bypass buffer empty </td><td> 3</td><td>	Group 106 pm_fabric2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP106</td><td> Run instructions completed </td><td> 4</td><td>	Group 106 pm_fabric2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP106</td><td> Run cycles </td><td> 5</td><td>	Group 106 pm_fabric2</td>

</tr>

<tr><td>PM_FAB_PNtoNN_DIRECT_GRP107</td><td> PN to NN beat went straight to its destination </td><td> 0</td><td>	Group 107 pm_fabric3</td>

</tr>

<tr><td>PM_FAB_PNtoVN_DIRECT_GRP107</td><td> PN to VN beat went straight to its destination </td><td> 1</td><td>	Group 107 pm_fabric3</td>

</tr>

<tr><td>PM_FAB_PNtoNN_SIDECAR_GRP107</td><td> PN to NN beat went to sidecar first </td><td> 2</td><td>	Group 107 pm_fabric3</td>

</tr>

<tr><td>PM_FAB_PNtoVN_SIDECAR_GRP107</td><td> PN to VN beat went to sidecar first </td><td> 3</td><td>	Group 107 pm_fabric3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP107</td><td> Run instructions completed </td><td> 4</td><td>	Group 107 pm_fabric3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP107</td><td> Run cycles </td><td> 5</td><td>	Group 107 pm_fabric3</td>

</tr>

<tr><td>PM_FAB_M1toP1_SIDECAR_EMPTY_GRP108</td><td> M1 to P1 sidecar empty </td><td> 0</td><td>	Group 108 pm_fabric4</td>

</tr>

<tr><td>PM_FAB_HOLDtoNN_EMPTY_GRP108</td><td> Hold buffer to NN empty </td><td> 1</td><td>	Group 108 pm_fabric4</td>

</tr>

<tr><td>PM_EE_OFF_GRP108</td><td> Cycles MSR(EE) bit off </td><td> 2</td><td>	Group 108 pm_fabric4</td>

</tr>

<tr><td>PM_FAB_M1toVNorNN_SIDECAR_EMPTY_GRP108</td><td> M1 to VN/NN sidecar empty </td><td> 3</td><td>	Group 108 pm_fabric4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP108</td><td> Run instructions completed </td><td> 4</td><td>	Group 108 pm_fabric4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP108</td><td> Run cycles </td><td> 5</td><td>	Group 108 pm_fabric4</td>

</tr>

<tr><td>PM_SNOOP_RD_RETRY_QFULL_GRP109</td><td> Snoop read retry due to read queue full </td><td> 0</td><td>	Group 109 pm_snoop1</td>

</tr>

<tr><td>PM_SNOOP_DCLAIM_RETRY_QFULL_GRP109</td><td> Snoop dclaim/flush retry due to write/dclaim queues full </td><td> 1</td><td>	Group 109 pm_snoop1</td>

</tr>

<tr><td>PM_SNOOP_WR_RETRY_QFULL_GRP109</td><td> Snoop read retry due to read queue full </td><td> 2</td><td>	Group 109 pm_snoop1</td>

</tr>

<tr><td>PM_SNOOP_PARTIAL_RTRY_QFULL_GRP109</td><td> Snoop partial write retry due to partial-write queues full </td><td> 3</td><td>	Group 109 pm_snoop1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP109</td><td> Run instructions completed </td><td> 4</td><td>	Group 109 pm_snoop1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP109</td><td> Run cycles </td><td> 5</td><td>	Group 109 pm_snoop1</td>

</tr>

<tr><td>PM_SNOOP_RD_RETRY_RQ_GRP110</td><td> Snoop read retry due to collision with active read queue </td><td> 0</td><td>	Group 110 pm_snoop2</td>

</tr>

<tr><td>PM_SNOOP_RETRY_1AHEAD_GRP110</td><td> Snoop retry due to one ahead collision </td><td> 1</td><td>	Group 110 pm_snoop2</td>

</tr>

<tr><td>PM_SNOOP_RD_RETRY_WQ_GRP110</td><td> Snoop read retry due to collision with active write queue </td><td> 2</td><td>	Group 110 pm_snoop2</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP110</td><td> IOPS instructions completed </td><td> 3</td><td>	Group 110 pm_snoop2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP110</td><td> Run instructions completed </td><td> 4</td><td>	Group 110 pm_snoop2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP110</td><td> Run cycles </td><td> 5</td><td>	Group 110 pm_snoop2</td>

</tr>

<tr><td>PM_SNOOP_WR_RETRY_RQ_GRP111</td><td> Snoop write/dclaim retry due to collision with active read queue </td><td> 0</td><td>	Group 111 pm_snoop3</td>

</tr>

<tr><td>PM_MEM_HI_PRIO_WR_CMPL_GRP111</td><td> High priority write completed </td><td> 1</td><td>	Group 111 pm_snoop3</td>

</tr>

<tr><td>PM_SNOOP_WR_RETRY_WQ_GRP111</td><td> Snoop write/dclaim retry due to collision with active write queue </td><td> 2</td><td>	Group 111 pm_snoop3</td>

</tr>

<tr><td>PM_MEM_LO_PRIO_WR_CMPL_GRP111</td><td> Low priority write completed </td><td> 3</td><td>	Group 111 pm_snoop3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP111</td><td> Run instructions completed </td><td> 4</td><td>	Group 111 pm_snoop3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP111</td><td> Run cycles </td><td> 5</td><td>	Group 111 pm_snoop3</td>

</tr>

<tr><td>PM_SNOOP_PW_RETRY_RQ_GRP112</td><td> Snoop partial-write retry due to collision with active read queue </td><td> 0</td><td>	Group 112 pm_snoop4</td>

</tr>

<tr><td>PM_MEM_HI_PRIO_PW_CMPL_GRP112</td><td> High priority partial-write completed </td><td> 1</td><td>	Group 112 pm_snoop4</td>

</tr>

<tr><td>PM_SNOOP_PW_RETRY_WQ_PWQ_GRP112</td><td> Snoop partial-write retry due to collision with active write or partial-write queue </td><td> 2</td><td>	Group 112 pm_snoop4</td>

</tr>

<tr><td>PM_MEM_LO_PRIO_PW_CMPL_GRP112</td><td> Low priority partial-write completed </td><td> 3</td><td>	Group 112 pm_snoop4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP112</td><td> Run instructions completed </td><td> 4</td><td>	Group 112 pm_snoop4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP112</td><td> Run cycles </td><td> 5</td><td>	Group 112 pm_snoop4</td>

</tr>

<tr><td>PM_MEM_RQ_DISP_GRP113</td><td> Memory read queue dispatched </td><td> 0</td><td>	Group 113 pm_mem_rq</td>

</tr>

<tr><td>PM_MEM_RQ_DISP_BUSY8to15_GRP113</td><td> Memory read queue dispatched with 8-15 queues busy </td><td> 1</td><td>	Group 113 pm_mem_rq</td>

</tr>

<tr><td>PM_MEM_RQ_DISP_BUSY1to7_GRP113</td><td> Memory read queue dispatched with 1-7 queues busy </td><td> 2</td><td>	Group 113 pm_mem_rq</td>

</tr>

<tr><td>PM_EE_OFF_EXT_INT_GRP113</td><td> Cycles MSR(EE) bit off and external interrupt pending </td><td> 3</td><td>	Group 113 pm_mem_rq</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP113</td><td> Run instructions completed </td><td> 4</td><td>	Group 113 pm_mem_rq</td>

</tr>

<tr><td>PM_RUN_CYC_GRP113</td><td> Run cycles </td><td> 5</td><td>	Group 113 pm_mem_rq</td>

</tr>

<tr><td>PM_MEM_READ_CMPL_GRP114</td><td> Memory read completed or canceled </td><td> 0</td><td>	Group 114 pm_mem_read</td>

</tr>

<tr><td>PM_MEM_FAST_PATH_RD_CMPL_GRP114</td><td> Fast path memory read completed </td><td> 1</td><td>	Group 114 pm_mem_read</td>

</tr>

<tr><td>PM_MEM_SPEC_RD_CANCEL_GRP114</td><td> Speculative memory read canceled </td><td> 2</td><td>	Group 114 pm_mem_read</td>

</tr>

<tr><td>PM_EXT_INT_GRP114</td><td> External interrupts </td><td> 3</td><td>	Group 114 pm_mem_read</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP114</td><td> Run instructions completed </td><td> 4</td><td>	Group 114 pm_mem_read</td>

</tr>

<tr><td>PM_RUN_CYC_GRP114</td><td> Run cycles </td><td> 5</td><td>	Group 114 pm_mem_read</td>

</tr>

<tr><td>PM_MEM_WQ_DISP_WRITE_GRP115</td><td> Memory write queue dispatched due to write </td><td> 0</td><td>	Group 115 pm_mem_wq</td>

</tr>

<tr><td>PM_MEM_WQ_DISP_BUSY1to7_GRP115</td><td> Memory write queue dispatched with 1-7 queues busy </td><td> 1</td><td>	Group 115 pm_mem_wq</td>

</tr>

<tr><td>PM_MEM_WQ_DISP_DCLAIM_GRP115</td><td> Memory write queue dispatched due to dclaim/flush </td><td> 2</td><td>	Group 115 pm_mem_wq</td>

</tr>

<tr><td>PM_MEM_WQ_DISP_BUSY8to15_GRP115</td><td> Memory write queue dispatched with 8-15 queues busy </td><td> 3</td><td>	Group 115 pm_mem_wq</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP115</td><td> Run instructions completed </td><td> 4</td><td>	Group 115 pm_mem_wq</td>

</tr>

<tr><td>PM_RUN_CYC_GRP115</td><td> Run cycles </td><td> 5</td><td>	Group 115 pm_mem_wq</td>

</tr>

<tr><td>PM_MEM_PWQ_DISP_GRP116</td><td> Memory partial-write queue dispatched </td><td> 0</td><td>	Group 116 pm_mem_pwq</td>

</tr>

<tr><td>PM_MEM_PWQ_DISP_BUSY2or3_GRP116</td><td> Memory partial-write queue dispatched with 2-3 queues busy </td><td> 1</td><td>	Group 116 pm_mem_pwq</td>

</tr>

<tr><td>PM_MEM_PW_GATH_GRP116</td><td> Memory partial-write gathered </td><td> 2</td><td>	Group 116 pm_mem_pwq</td>

</tr>

<tr><td>PM_MEM_PW_CMPL_GRP116</td><td> Memory partial-write completed </td><td> 3</td><td>	Group 116 pm_mem_pwq</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP116</td><td> Run instructions completed </td><td> 4</td><td>	Group 116 pm_mem_pwq</td>

</tr>

<tr><td>PM_RUN_CYC_GRP116</td><td> Run cycles </td><td> 5</td><td>	Group 116 pm_mem_pwq</td>

</tr>

<tr><td>PM_MRK_GRP_DISP_GRP117</td><td> Marked group dispatched </td><td> 0</td><td>	Group 117 pm_threshold</td>

</tr>

<tr><td>PM_MRK_IMR_RELOAD_GRP117</td><td> Marked IMR reloaded </td><td> 1</td><td>	Group 117 pm_threshold</td>

</tr>

<tr><td>PM_THRESH_TIMEO_GRP117</td><td> Threshold timeout </td><td> 2</td><td>	Group 117 pm_threshold</td>

</tr>

<tr><td>PM_MRK_LSU_FIN_GRP117</td><td> Marked instruction LSU processing finished </td><td> 3</td><td>	Group 117 pm_threshold</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP117</td><td> Run instructions completed </td><td> 4</td><td>	Group 117 pm_threshold</td>

</tr>

<tr><td>PM_RUN_CYC_GRP117</td><td> Run cycles </td><td> 5</td><td>	Group 117 pm_threshold</td>

</tr>

<tr><td>PM_MRK_GRP_DISP_GRP118</td><td> Marked group dispatched </td><td> 0</td><td>	Group 118 pm_mrk_grp1</td>

</tr>

<tr><td>PM_MRK_ST_MISS_L1_GRP118</td><td> Marked L1 D cache store misses </td><td> 1</td><td>	Group 118 pm_mrk_grp1</td>

</tr>

<tr><td>PM_MRK_INST_FIN_GRP118</td><td> Marked instruction finished </td><td> 2</td><td>	Group 118 pm_mrk_grp1</td>

</tr>

<tr><td>PM_MRK_GRP_CMPL_GRP118</td><td> Marked group completed </td><td> 3</td><td>	Group 118 pm_mrk_grp1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP118</td><td> Run instructions completed </td><td> 4</td><td>	Group 118 pm_mrk_grp1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP118</td><td> Run cycles </td><td> 5</td><td>	Group 118 pm_mrk_grp1</td>

</tr>

<tr><td>PM_MRK_GRP_ISSUED_GRP119</td><td> Marked group issued </td><td> 0</td><td>	Group 119 pm_mrk_grp2</td>

</tr>

<tr><td>PM_MRK_BRU_FIN_GRP119</td><td> Marked instruction BRU processing finished </td><td> 1</td><td>	Group 119 pm_mrk_grp2</td>

</tr>

<tr><td>PM_MRK_L1_RELOAD_VALID_GRP119</td><td> Marked L1 reload data source valid </td><td> 2</td><td>	Group 119 pm_mrk_grp2</td>

</tr>

<tr><td>PM_MRK_GRP_IC_MISS_GRP119</td><td> Group experienced marked I cache miss </td><td> 3</td><td>	Group 119 pm_mrk_grp2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP119</td><td> Run instructions completed </td><td> 4</td><td>	Group 119 pm_mrk_grp2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP119</td><td> Run cycles </td><td> 5</td><td>	Group 119 pm_mrk_grp2</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L2_GRP120</td><td> Marked data loaded from L2 </td><td> 0</td><td>	Group 120 pm_mrk_dsource1</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L2_CYC_GRP120</td><td> Marked load latency from L2 </td><td> 1</td><td>	Group 120 pm_mrk_dsource1</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L25_MOD_GRP120</td><td> Marked data loaded from L2.5 modified </td><td> 2</td><td>	Group 120 pm_mrk_dsource1</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L25_MOD_CYC_GRP120</td><td> Marked load latency from L2.5 modified </td><td> 3</td><td>	Group 120 pm_mrk_dsource1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP120</td><td> Run instructions completed </td><td> 4</td><td>	Group 120 pm_mrk_dsource1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP120</td><td> Run cycles </td><td> 5</td><td>	Group 120 pm_mrk_dsource1</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L25_SHR_GRP121</td><td> Marked data loaded from L2.5 shared </td><td> 0</td><td>	Group 121 pm_mrk_dsource2</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L25_SHR_CYC_GRP121</td><td> Marked load latency from L2.5 shared </td><td> 1</td><td>	Group 121 pm_mrk_dsource2</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP121</td><td> IOPS instructions completed </td><td> 2</td><td>	Group 121 pm_mrk_dsource2</td>

</tr>

<tr><td>PM_FPU_FIN_GRP121</td><td> FPU produced a result </td><td> 3</td><td>	Group 121 pm_mrk_dsource2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP121</td><td> Run instructions completed </td><td> 4</td><td>	Group 121 pm_mrk_dsource2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP121</td><td> Run cycles </td><td> 5</td><td>	Group 121 pm_mrk_dsource2</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L3_GRP122</td><td> Marked data loaded from L3 </td><td> 0</td><td>	Group 122 pm_mrk_dsource3</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L3_CYC_GRP122</td><td> Marked load latency from L3 </td><td> 1</td><td>	Group 122 pm_mrk_dsource3</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L35_MOD_GRP122</td><td> Marked data loaded from L3.5 modified </td><td> 2</td><td>	Group 122 pm_mrk_dsource3</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L35_MOD_CYC_GRP122</td><td> Marked load latency from L3.5 modified </td><td> 3</td><td>	Group 122 pm_mrk_dsource3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP122</td><td> Run instructions completed </td><td> 4</td><td>	Group 122 pm_mrk_dsource3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP122</td><td> Run cycles </td><td> 5</td><td>	Group 122 pm_mrk_dsource3</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_RMEM_GRP123</td><td> Marked data loaded from remote memory </td><td> 0</td><td>	Group 123 pm_mrk_dsource4</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L275_SHR_CYC_GRP123</td><td> Marked load latency from L2.75 shared </td><td> 1</td><td>	Group 123 pm_mrk_dsource4</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L275_SHR_GRP123</td><td> Marked data loaded from L2.75 shared </td><td> 2</td><td>	Group 123 pm_mrk_dsource4</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_RMEM_CYC_GRP123</td><td> Marked load latency from remote memory </td><td> 3</td><td>	Group 123 pm_mrk_dsource4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP123</td><td> Run instructions completed </td><td> 4</td><td>	Group 123 pm_mrk_dsource4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP123</td><td> Run cycles </td><td> 5</td><td>	Group 123 pm_mrk_dsource4</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L35_SHR_GRP124</td><td> Marked data loaded from L3.5 shared </td><td> 0</td><td>	Group 124 pm_mrk_dsource5</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L35_SHR_CYC_GRP124</td><td> Marked load latency from L3.5 shared </td><td> 1</td><td>	Group 124 pm_mrk_dsource5</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_LMEM_GRP124</td><td> Marked data loaded from local memory </td><td> 2</td><td>	Group 124 pm_mrk_dsource5</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_LMEM_CYC_GRP124</td><td> Marked load latency from local memory </td><td> 3</td><td>	Group 124 pm_mrk_dsource5</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP124</td><td> Run instructions completed </td><td> 4</td><td>	Group 124 pm_mrk_dsource5</td>

</tr>

<tr><td>PM_RUN_CYC_GRP124</td><td> Run cycles </td><td> 5</td><td>	Group 124 pm_mrk_dsource5</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L275_MOD_GRP125</td><td> Marked data loaded from L2.75 modified </td><td> 0</td><td>	Group 125 pm_mrk_dsource6</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L275_SHR_CYC_GRP125</td><td> Marked load latency from L2.75 shared </td><td> 1</td><td>	Group 125 pm_mrk_dsource6</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP125</td><td> IOPS instructions completed </td><td> 2</td><td>	Group 125 pm_mrk_dsource6</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L275_MOD_CYC_GRP125</td><td> Marked load latency from L2.75 modified </td><td> 3</td><td>	Group 125 pm_mrk_dsource6</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP125</td><td> Run instructions completed </td><td> 4</td><td>	Group 125 pm_mrk_dsource6</td>

</tr>

<tr><td>PM_RUN_CYC_GRP125</td><td> Run cycles </td><td> 5</td><td>	Group 125 pm_mrk_dsource6</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L375_MOD_GRP126</td><td> Marked data loaded from L3.75 modified </td><td> 0</td><td>	Group 126 pm_mrk_dsource7</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L375_SHR_CYC_GRP126</td><td> Marked load latency from L3.75 shared </td><td> 1</td><td>	Group 126 pm_mrk_dsource7</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L375_SHR_GRP126</td><td> Marked data loaded from L3.75 shared </td><td> 2</td><td>	Group 126 pm_mrk_dsource7</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L375_MOD_CYC_GRP126</td><td> Marked load latency from L3.75 modified </td><td> 3</td><td>	Group 126 pm_mrk_dsource7</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP126</td><td> Run instructions completed </td><td> 4</td><td>	Group 126 pm_mrk_dsource7</td>

</tr>

<tr><td>PM_RUN_CYC_GRP126</td><td> Run cycles </td><td> 5</td><td>	Group 126 pm_mrk_dsource7</td>

</tr>

<tr><td>PM_MRK_DTLB_REF_4K_GRP127</td><td> Marked Data TLB reference for 4K page </td><td> 0</td><td>	Group 127 pm_mrk_dtlbref</td>

</tr>

<tr><td>PM_MRK_DTLB_REF_64K_GRP127</td><td> Marked Data TLB reference for 64K page </td><td> 1</td><td>	Group 127 pm_mrk_dtlbref</td>

</tr>

<tr><td>PM_MRK_DTLB_REF_16M_GRP127</td><td> Marked Data TLB reference for 16M page </td><td> 2</td><td>	Group 127 pm_mrk_dtlbref</td>

</tr>

<tr><td>PM_MRK_DTLB_REF_16G_GRP127</td><td> Marked Data TLB reference for 16G page </td><td> 3</td><td>	Group 127 pm_mrk_dtlbref</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP127</td><td> Run instructions completed </td><td> 4</td><td>	Group 127 pm_mrk_dtlbref</td>

</tr>

<tr><td>PM_RUN_CYC_GRP127</td><td> Run cycles </td><td> 5</td><td>	Group 127 pm_mrk_dtlbref</td>

</tr>

<tr><td>PM_MRK_DTLB_MISS_4K_GRP128</td><td> Marked Data TLB misses for 4K page </td><td> 0</td><td>	Group 128 pm_mrk_dtlbmiss</td>

</tr>

<tr><td>PM_MRK_DTLB_MISS_64K_GRP128</td><td> Marked Data TLB misses for 64K page </td><td> 1</td><td>	Group 128 pm_mrk_dtlbmiss</td>

</tr>

<tr><td>PM_MRK_DTLB_MISS_16M_GRP128</td><td> Marked Data TLB misses for 16M page </td><td> 2</td><td>	Group 128 pm_mrk_dtlbmiss</td>

</tr>

<tr><td>PM_MRK_DTLB_MISS_16G_GRP128</td><td> Marked Data TLB misses for 16G page </td><td> 3</td><td>	Group 128 pm_mrk_dtlbmiss</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP128</td><td> Run instructions completed </td><td> 4</td><td>	Group 128 pm_mrk_dtlbmiss</td>

</tr>

<tr><td>PM_RUN_CYC_GRP128</td><td> Run cycles </td><td> 5</td><td>	Group 128 pm_mrk_dtlbmiss</td>

</tr>

<tr><td>PM_MRK_DTLB_REF_GRP129</td><td> Marked Data TLB reference </td><td> 0</td><td>	Group 129 pm_mrk_dtlb_dslb</td>

</tr>

<tr><td>PM_MRK_DTLB_MISS_GRP129</td><td> Marked Data TLB misses </td><td> 1</td><td>	Group 129 pm_mrk_dtlb_dslb</td>

</tr>

<tr><td>PM_MRK_DSLB_MISS_GRP129</td><td> Marked Data SLB misses </td><td> 2</td><td>	Group 129 pm_mrk_dtlb_dslb</td>

</tr>

<tr><td>PM_CYC_GRP129</td><td> Processor cycles </td><td> 3</td><td>	Group 129 pm_mrk_dtlb_dslb</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP129</td><td> Run instructions completed </td><td> 4</td><td>	Group 129 pm_mrk_dtlb_dslb</td>

</tr>

<tr><td>PM_RUN_CYC_GRP129</td><td> Run cycles </td><td> 5</td><td>	Group 129 pm_mrk_dtlb_dslb</td>

</tr>

<tr><td>PM_MRK_DTLB_REF_4K_GRP130</td><td> Marked Data TLB reference for 4K page </td><td> 0</td><td>	Group 130 pm_mrk_lbref</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP130</td><td> IOPS instructions completed </td><td> 1</td><td>	Group 130 pm_mrk_lbref</td>

</tr>

<tr><td>PM_MRK_DTLB_REF_16M_GRP130</td><td> Marked Data TLB reference for 16M page </td><td> 2</td><td>	Group 130 pm_mrk_lbref</td>

</tr>

<tr><td>PM_MRK_DSLB_MISS_GRP130</td><td> Marked Data SLB misses </td><td> 3</td><td>	Group 130 pm_mrk_lbref</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP130</td><td> Run instructions completed </td><td> 4</td><td>	Group 130 pm_mrk_lbref</td>

</tr>

<tr><td>PM_RUN_CYC_GRP130</td><td> Run cycles </td><td> 5</td><td>	Group 130 pm_mrk_lbref</td>

</tr>

<tr><td>PM_MRK_LD_MISS_L1_GRP131</td><td> Marked L1 D cache load misses </td><td> 0</td><td>	Group 131 pm_mrk_lsmiss</td>

</tr>

<tr><td>PM_IOPS_CMPL_GRP131</td><td> IOPS instructions completed </td><td> 1</td><td>	Group 131 pm_mrk_lsmiss</td>

</tr>

<tr><td>PM_MRK_ST_CMPL_INT_GRP131</td><td> Marked store completed with intervention </td><td> 2</td><td>	Group 131 pm_mrk_lsmiss</td>

</tr>

<tr><td>PM_MRK_CRU_FIN_GRP131</td><td> Marked instruction CRU processing finished </td><td> 3</td><td>	Group 131 pm_mrk_lsmiss</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP131</td><td> Run instructions completed </td><td> 4</td><td>	Group 131 pm_mrk_lsmiss</td>

</tr>

<tr><td>PM_RUN_CYC_GRP131</td><td> Run cycles </td><td> 5</td><td>	Group 131 pm_mrk_lsmiss</td>

</tr>

<tr><td>PM_MRK_ST_CMPL_GRP132</td><td> Marked store instruction completed </td><td> 0</td><td>	Group 132 pm_mrk_ulsflush</td>

</tr>

<tr><td>PM_MRK_ST_MISS_L1_GRP132</td><td> Marked L1 D cache store misses </td><td> 1</td><td>	Group 132 pm_mrk_ulsflush</td>

</tr>

<tr><td>PM_MRK_LSU_FLUSH_UST_GRP132</td><td> Marked unaligned store flushes </td><td> 2</td><td>	Group 132 pm_mrk_ulsflush</td>

</tr>

<tr><td>PM_MRK_LSU_FLUSH_ULD_GRP132</td><td> Marked unaligned load flushes </td><td> 3</td><td>	Group 132 pm_mrk_ulsflush</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP132</td><td> Run instructions completed </td><td> 4</td><td>	Group 132 pm_mrk_ulsflush</td>

</tr>

<tr><td>PM_RUN_CYC_GRP132</td><td> Run cycles </td><td> 5</td><td>	Group 132 pm_mrk_ulsflush</td>

</tr>

<tr><td>PM_MRK_STCX_FAIL_GRP133</td><td> Marked STCX failed </td><td> 0</td><td>	Group 133 pm_mrk_misc</td>

</tr>

<tr><td>PM_MRK_ST_GPS_GRP133</td><td> Marked store sent to GPS </td><td> 1</td><td>	Group 133 pm_mrk_misc</td>

</tr>

<tr><td>PM_MRK_FPU_FIN_GRP133</td><td> Marked instruction FPU processing finished </td><td> 2</td><td>	Group 133 pm_mrk_misc</td>

</tr>

<tr><td>PM_MRK_GRP_TIMEO_GRP133</td><td> Marked group completion timeout </td><td> 3</td><td>	Group 133 pm_mrk_misc</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP133</td><td> Run instructions completed </td><td> 4</td><td>	Group 133 pm_mrk_misc</td>

</tr>

<tr><td>PM_RUN_CYC_GRP133</td><td> Run cycles </td><td> 5</td><td>	Group 133 pm_mrk_misc</td>

</tr>

<tr><td>PM_DATA_FROM_L2_GRP134</td><td> Data loaded from L2 </td><td> 0</td><td>	Group 134 pm_lsref_L1</td>

</tr>

<tr><td>PM_INST_FROM_L1_GRP134</td><td> Instruction fetched from L1 </td><td> 1</td><td>	Group 134 pm_lsref_L1</td>

</tr>

<tr><td>PM_ST_REF_L1_GRP134</td><td> L1 D cache store references </td><td> 2</td><td>	Group 134 pm_lsref_L1</td>

</tr>

<tr><td>PM_LD_REF_L1_GRP134</td><td> L1 D cache load references </td><td> 3</td><td>	Group 134 pm_lsref_L1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP134</td><td> Run instructions completed </td><td> 4</td><td>	Group 134 pm_lsref_L1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP134</td><td> Run cycles </td><td> 5</td><td>	Group 134 pm_lsref_L1</td>

</tr>

<tr><td>PM_DATA_FROM_L3_GRP135</td><td> Data loaded from L3 </td><td> 0</td><td>	Group 135 pm_lsref_L2L3</td>

</tr>

<tr><td>PM_DATA_FROM_LMEM_GRP135</td><td> Data loaded from local memory </td><td> 1</td><td>	Group 135 pm_lsref_L2L3</td>

</tr>

<tr><td>PM_ST_REF_L1_GRP135</td><td> L1 D cache store references </td><td> 2</td><td>	Group 135 pm_lsref_L2L3</td>

</tr>

<tr><td>PM_LD_REF_L1_GRP135</td><td> L1 D cache load references </td><td> 3</td><td>	Group 135 pm_lsref_L2L3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP135</td><td> Run instructions completed </td><td> 4</td><td>	Group 135 pm_lsref_L2L3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP135</td><td> Run cycles </td><td> 5</td><td>	Group 135 pm_lsref_L2L3</td>

</tr>

<tr><td>PM_ITLB_MISS_GRP136</td><td> Instruction TLB misses </td><td> 0</td><td>	Group 136 pm_lsref_tlbmiss</td>

</tr>

<tr><td>PM_DTLB_MISS_GRP136</td><td> Data TLB misses </td><td> 1</td><td>	Group 136 pm_lsref_tlbmiss</td>

</tr>

<tr><td>PM_ST_REF_L1_GRP136</td><td> L1 D cache store references </td><td> 2</td><td>	Group 136 pm_lsref_tlbmiss</td>

</tr>

<tr><td>PM_LD_REF_L1_GRP136</td><td> L1 D cache load references </td><td> 3</td><td>	Group 136 pm_lsref_tlbmiss</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP136</td><td> Run instructions completed </td><td> 4</td><td>	Group 136 pm_lsref_tlbmiss</td>

</tr>

<tr><td>PM_RUN_CYC_GRP136</td><td> Run cycles </td><td> 5</td><td>	Group 136 pm_lsref_tlbmiss</td>

</tr>

<tr><td>PM_DATA_FROM_L3_GRP137</td><td> Data loaded from L3 </td><td> 0</td><td>	Group 137 pm_Dmiss</td>

</tr>

<tr><td>PM_DATA_FROM_LMEM_GRP137</td><td> Data loaded from local memory </td><td> 1</td><td>	Group 137 pm_Dmiss</td>

</tr>

<tr><td>PM_LD_MISS_L1_GRP137</td><td> L1 D cache load misses </td><td> 2</td><td>	Group 137 pm_Dmiss</td>

</tr>

<tr><td>PM_ST_MISS_L1_GRP137</td><td> L1 D cache store misses </td><td> 3</td><td>	Group 137 pm_Dmiss</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP137</td><td> Run instructions completed </td><td> 4</td><td>	Group 137 pm_Dmiss</td>

</tr>

<tr><td>PM_RUN_CYC_GRP137</td><td> Run cycles </td><td> 5</td><td>	Group 137 pm_Dmiss</td>

</tr>

<tr><td>PM_CYC_GRP138</td><td> Processor cycles </td><td> 0</td><td>	Group 138 pm_prefetchX</td>

</tr>

<tr><td>PM_IC_PREF_REQ_GRP138</td><td> Instruction prefetch requests </td><td> 1</td><td>	Group 138 pm_prefetchX</td>

</tr>

<tr><td>PM_L1_PREF_GRP138</td><td> L1 cache data prefetches </td><td> 2</td><td>	Group 138 pm_prefetchX</td>

</tr>

<tr><td>PM_L2_PREF_GRP138</td><td> L2 cache prefetches </td><td> 3</td><td>	Group 138 pm_prefetchX</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP138</td><td> Run instructions completed </td><td> 4</td><td>	Group 138 pm_prefetchX</td>

</tr>

<tr><td>PM_RUN_CYC_GRP138</td><td> Run cycles </td><td> 5</td><td>	Group 138 pm_prefetchX</td>

</tr>

<tr><td>PM_BR_UNCOND_GRP139</td><td> Unconditional branch </td><td> 0</td><td>	Group 139 pm_branchX</td>

</tr>

<tr><td>PM_BR_PRED_TA_GRP139</td><td> A conditional branch was predicted, target prediction </td><td> 1</td><td>	Group 139 pm_branchX</td>

</tr>

<tr><td>PM_BR_PRED_CR_GRP139</td><td> A conditional branch was predicted, CR prediction </td><td> 2</td><td>	Group 139 pm_branchX</td>

</tr>

<tr><td>PM_BR_ISSUED_GRP139</td><td> Branches issued </td><td> 3</td><td>	Group 139 pm_branchX</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP139</td><td> Run instructions completed </td><td> 4</td><td>	Group 139 pm_branchX</td>

</tr>

<tr><td>PM_RUN_CYC_GRP139</td><td> Run cycles </td><td> 5</td><td>	Group 139 pm_branchX</td>

</tr>

<tr><td>PM_FPU0_STALL3_GRP140</td><td> FPU0 stalled in pipe3 </td><td> 0</td><td>	Group 140 pm_fpuX1</td>

</tr>

<tr><td>PM_FPU1_STALL3_GRP140</td><td> FPU1 stalled in pipe3 </td><td> 1</td><td>	Group 140 pm_fpuX1</td>

</tr>

<tr><td>PM_FPU0_FIN_GRP140</td><td> FPU0 produced a result </td><td> 2</td><td>	Group 140 pm_fpuX1</td>

</tr>

<tr><td>PM_FPU0_FPSCR_GRP140</td><td> FPU0 executed FPSCR instruction </td><td> 3</td><td>	Group 140 pm_fpuX1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP140</td><td> Run instructions completed </td><td> 4</td><td>	Group 140 pm_fpuX1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP140</td><td> Run cycles </td><td> 5</td><td>	Group 140 pm_fpuX1</td>

</tr>

<tr><td>PM_FPU0_FMA_GRP141</td><td> FPU0 executed multiply-add instruction </td><td> 0</td><td>	Group 141 pm_fpuX2</td>

</tr>

<tr><td>PM_FPU1_FMA_GRP141</td><td> FPU1 executed multiply-add instruction </td><td> 1</td><td>	Group 141 pm_fpuX2</td>

</tr>

<tr><td>PM_FPU0_FRSP_FCONV_GRP141</td><td> FPU0 executed FRSP or FCONV instructions </td><td> 2</td><td>	Group 141 pm_fpuX2</td>

</tr>

<tr><td>PM_FPU1_FRSP_FCONV_GRP141</td><td> FPU1 executed FRSP or FCONV instructions </td><td> 3</td><td>	Group 141 pm_fpuX2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP141</td><td> Run instructions completed </td><td> 4</td><td>	Group 141 pm_fpuX2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP141</td><td> Run cycles </td><td> 5</td><td>	Group 141 pm_fpuX2</td>

</tr>

<tr><td>PM_FPU0_1FLOP_GRP142</td><td> FPU0 executed add, mult, sub, cmp or sel instruction </td><td> 0</td><td>	Group 142 pm_fpuX3</td>

</tr>

<tr><td>PM_FPU1_1FLOP_GRP142</td><td> FPU1 executed add, mult, sub, cmp or sel instruction </td><td> 1</td><td>	Group 142 pm_fpuX3</td>

</tr>

<tr><td>PM_FPU0_FIN_GRP142</td><td> FPU0 produced a result </td><td> 2</td><td>	Group 142 pm_fpuX3</td>

</tr>

<tr><td>PM_FPU1_FIN_GRP142</td><td> FPU1 produced a result </td><td> 3</td><td>	Group 142 pm_fpuX3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP142</td><td> Run instructions completed </td><td> 4</td><td>	Group 142 pm_fpuX3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP142</td><td> Run cycles </td><td> 5</td><td>	Group 142 pm_fpuX3</td>

</tr>

<tr><td>PM_FPU_1FLOP_GRP143</td><td> FPU executed one flop instruction  </td><td> 0</td><td>	Group 143 pm_fpuX4</td>

</tr>

<tr><td>PM_FPU_FMA_GRP143</td><td> FPU executed multiply-add instruction </td><td> 1</td><td>	Group 143 pm_fpuX4</td>

</tr>

<tr><td>PM_ST_REF_L1_GRP143</td><td> L1 D cache store references </td><td> 2</td><td>	Group 143 pm_fpuX4</td>

</tr>

<tr><td>PM_LD_REF_L1_GRP143</td><td> L1 D cache load references </td><td> 3</td><td>	Group 143 pm_fpuX4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP143</td><td> Run instructions completed </td><td> 4</td><td>	Group 143 pm_fpuX4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP143</td><td> Run cycles </td><td> 5</td><td>	Group 143 pm_fpuX4</td>

</tr>

<tr><td>PM_FPU_SINGLE_GRP144</td><td> FPU executed single precision instruction </td><td> 0</td><td>	Group 144 pm_fpuX5</td>

</tr>

<tr><td>PM_FPU_STF_GRP144</td><td> FPU executed store instruction </td><td> 1</td><td>	Group 144 pm_fpuX5</td>

</tr>

<tr><td>PM_FPU0_FIN_GRP144</td><td> FPU0 produced a result </td><td> 2</td><td>	Group 144 pm_fpuX5</td>

</tr>

<tr><td>PM_FPU1_FIN_GRP144</td><td> FPU1 produced a result </td><td> 3</td><td>	Group 144 pm_fpuX5</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP144</td><td> Run instructions completed </td><td> 4</td><td>	Group 144 pm_fpuX5</td>

</tr>

<tr><td>PM_RUN_CYC_GRP144</td><td> Run cycles </td><td> 5</td><td>	Group 144 pm_fpuX5</td>

</tr>

<tr><td>PM_FPU_FDIV_GRP145</td><td> FPU executed FDIV instruction </td><td> 0</td><td>	Group 145 pm_fpuX6</td>

</tr>

<tr><td>PM_FPU_FSQRT_GRP145</td><td> FPU executed FSQRT instruction </td><td> 1</td><td>	Group 145 pm_fpuX6</td>

</tr>

<tr><td>PM_FPU_FRSP_FCONV_GRP145</td><td> FPU executed FRSP or FCONV instructions </td><td> 2</td><td>	Group 145 pm_fpuX6</td>

</tr>

<tr><td>PM_FPU_FIN_GRP145</td><td> FPU produced a result </td><td> 3</td><td>	Group 145 pm_fpuX6</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP145</td><td> Run instructions completed </td><td> 4</td><td>	Group 145 pm_fpuX6</td>

</tr>

<tr><td>PM_RUN_CYC_GRP145</td><td> Run cycles </td><td> 5</td><td>	Group 145 pm_fpuX6</td>

</tr>

<tr><td>PM_FPU_1FLOP_GRP146</td><td> FPU executed one flop instruction  </td><td> 0</td><td>	Group 146 pm_fpuX7</td>

</tr>

<tr><td>PM_FPU_FMA_GRP146</td><td> FPU executed multiply-add instruction </td><td> 1</td><td>	Group 146 pm_fpuX7</td>

</tr>

<tr><td>PM_FPU_STF_GRP146</td><td> FPU executed store instruction </td><td> 2</td><td>	Group 146 pm_fpuX7</td>

</tr>

<tr><td>PM_FPU_FIN_GRP146</td><td> FPU produced a result </td><td> 3</td><td>	Group 146 pm_fpuX7</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP146</td><td> Run instructions completed </td><td> 4</td><td>	Group 146 pm_fpuX7</td>

</tr>

<tr><td>PM_RUN_CYC_GRP146</td><td> Run cycles </td><td> 5</td><td>	Group 146 pm_fpuX7</td>

</tr>

<tr><td>PM_CYC_GRP147</td><td> Processor cycles </td><td> 0</td><td>	Group 147 pm_hpmcount1</td>

</tr>

<tr><td>PM_FXU_FIN_GRP147</td><td> FXU produced a result </td><td> 1</td><td>	Group 147 pm_hpmcount1</td>

</tr>

<tr><td>PM_CYC_GRP147</td><td> Processor cycles </td><td> 2</td><td>	Group 147 pm_hpmcount1</td>

</tr>

<tr><td>PM_FPU_FIN_GRP147</td><td> FPU produced a result </td><td> 3</td><td>	Group 147 pm_hpmcount1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP147</td><td> Run instructions completed </td><td> 4</td><td>	Group 147 pm_hpmcount1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP147</td><td> Run cycles </td><td> 5</td><td>	Group 147 pm_hpmcount1</td>

</tr>

<tr><td>PM_CYC_GRP148</td><td> Processor cycles </td><td> 0</td><td>	Group 148 pm_hpmcount2</td>

</tr>

<tr><td>PM_FPU_STF_GRP148</td><td> FPU executed store instruction </td><td> 1</td><td>	Group 148 pm_hpmcount2</td>

</tr>

<tr><td>PM_INST_DISP_GRP148</td><td> Instructions dispatched </td><td> 2</td><td>	Group 148 pm_hpmcount2</td>

</tr>

<tr><td>PM_LSU_LDF_GRP148</td><td> LSU executed Floating Point load instruction </td><td> 3</td><td>	Group 148 pm_hpmcount2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP148</td><td> Run instructions completed </td><td> 4</td><td>	Group 148 pm_hpmcount2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP148</td><td> Run cycles </td><td> 5</td><td>	Group 148 pm_hpmcount2</td>

</tr>

<tr><td>PM_CYC_GRP149</td><td> Processor cycles </td><td> 0</td><td>	Group 149 pm_hpmcount3</td>

</tr>

<tr><td>PM_INST_DISP_GRP149</td><td> Instructions dispatched </td><td> 1</td><td>	Group 149 pm_hpmcount3</td>

</tr>

<tr><td>PM_LD_MISS_L1_GRP149</td><td> L1 D cache load misses </td><td> 2</td><td>	Group 149 pm_hpmcount3</td>

</tr>

<tr><td>PM_ST_MISS_L1_GRP149</td><td> L1 D cache store misses </td><td> 3</td><td>	Group 149 pm_hpmcount3</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP149</td><td> Run instructions completed </td><td> 4</td><td>	Group 149 pm_hpmcount3</td>

</tr>

<tr><td>PM_RUN_CYC_GRP149</td><td> Run cycles </td><td> 5</td><td>	Group 149 pm_hpmcount3</td>

</tr>

<tr><td>PM_TLB_MISS_GRP150</td><td> TLB misses </td><td> 0</td><td>	Group 150 pm_hpmcount4</td>

</tr>

<tr><td>PM_CYC_GRP150</td><td> Processor cycles </td><td> 1</td><td>	Group 150 pm_hpmcount4</td>

</tr>

<tr><td>PM_ST_REF_L1_GRP150</td><td> L1 D cache store references </td><td> 2</td><td>	Group 150 pm_hpmcount4</td>

</tr>

<tr><td>PM_LD_REF_L1_GRP150</td><td> L1 D cache load references </td><td> 3</td><td>	Group 150 pm_hpmcount4</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP150</td><td> Run instructions completed </td><td> 4</td><td>	Group 150 pm_hpmcount4</td>

</tr>

<tr><td>PM_RUN_CYC_GRP150</td><td> Run cycles </td><td> 5</td><td>	Group 150 pm_hpmcount4</td>

</tr>

<tr><td>PM_FPU_FDIV_GRP151</td><td> FPU executed FDIV instruction </td><td> 0</td><td>	Group 151 pm_flop</td>

</tr>

<tr><td>PM_FPU_FMA_GRP151</td><td> FPU executed multiply-add instruction </td><td> 1</td><td>	Group 151 pm_flop</td>

</tr>

<tr><td>PM_FPU_FSQRT_GRP151</td><td> FPU executed FSQRT instruction </td><td> 2</td><td>	Group 151 pm_flop</td>

</tr>

<tr><td>PM_FPU_1FLOP_GRP151</td><td> FPU executed one flop instruction  </td><td> 3</td><td>	Group 151 pm_flop</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP151</td><td> Run instructions completed </td><td> 4</td><td>	Group 151 pm_flop</td>

</tr>

<tr><td>PM_RUN_CYC_GRP151</td><td> Run cycles </td><td> 5</td><td>	Group 151 pm_flop</td>

</tr>

<tr><td>PM_INST_CMPL_GRP152</td><td> Instructions completed </td><td> 0</td><td>	Group 152 pm_eprof1</td>

</tr>

<tr><td>PM_CYC_GRP152</td><td> Processor cycles </td><td> 1</td><td>	Group 152 pm_eprof1</td>

</tr>

<tr><td>PM_LD_MISS_L1_GRP152</td><td> L1 D cache load misses </td><td> 2</td><td>	Group 152 pm_eprof1</td>

</tr>

<tr><td>PM_DC_INV_L2_GRP152</td><td> L1 D cache entries invalidated from L2 </td><td> 3</td><td>	Group 152 pm_eprof1</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP152</td><td> Run instructions completed </td><td> 4</td><td>	Group 152 pm_eprof1</td>

</tr>

<tr><td>PM_RUN_CYC_GRP152</td><td> Run cycles </td><td> 5</td><td>	Group 152 pm_eprof1</td>

</tr>

<tr><td>PM_INST_CMPL_GRP153</td><td> Instructions completed </td><td> 0</td><td>	Group 153 pm_eprof2</td>

</tr>

<tr><td>PM_ST_REF_L1_GRP153</td><td> L1 D cache store references </td><td> 1</td><td>	Group 153 pm_eprof2</td>

</tr>

<tr><td>PM_INST_DISP_GRP153</td><td> Instructions dispatched </td><td> 2</td><td>	Group 153 pm_eprof2</td>

</tr>

<tr><td>PM_LD_REF_L1_GRP153</td><td> L1 D cache load references </td><td> 3</td><td>	Group 153 pm_eprof2</td>

</tr>

<tr><td>PM_RUN_INST_CMPL_GRP153</td><td> Run instructions completed </td><td> 4</td><td>	Group 153 pm_eprof2</td>

</tr>

<tr><td>PM_RUN_CYC_GRP153</td><td> Run cycles </td><td> 5</td><td>	Group 153 pm_eprof2</td>

</tr>

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