Diff of /docs/ppc64-cellBE-events [9766c7] .. [28a31d]  Maximize  Restore

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--- a/docs/ppc64-cellBE-events
+++ b/docs/ppc64-cellBE-events
@@ -8,7 +8,7 @@
 
 </tr>
 
-<tr><td>Group 21 </td><td>	Branch instruction committed. </td><td> (counter</td><td>
+<tr><td>Group 21 </td><td>	Branch instruction committed.  </td><td> (counter</td><td>
 	0x00: Count edges				[mandatory]
  <br />
 	0x00: Negative polarity				[optional ]
@@ -23,7 +23,7 @@
 
 </tr>
 
-<tr><td>Group 21 </td><td>	Branch instruction that caused a misprediction flush is committed. Branch misprediction includes: (1) misprediction of taken or not-taken on conditional branch, (2) misprediction of branch target address on bclr[1] and bcctr[1]. </td><td> (counter</td><td>
+<tr><td>Group 21 </td><td>	Branch instruction that caused a misprediction flush is committed. Branch misprediction includes: (1) misprediction of taken or not-taken on conditional branch, (2) misprediction of branch target address on bclr[1] and bcctr[1].  </td><td> (counter</td><td>
 	0x00: Count edges				[mandatory]
  <br />
 	0x00: Negative polarity				[optional ]
@@ -38,7 +38,7 @@
 
 </tr>
 
-<tr><td>Group 21 </td><td>	Instruction buffer empty. </td><td> (counter</td><td>
+<tr><td>Group 21 </td><td>	Instruction buffer empty.  </td><td> (counter</td><td>
 	0x01: Count cycles				[mandatory]
  <br />
 	0x00: Negative polarity				[optional ]
@@ -53,7 +53,7 @@
 
 </tr>
 
-<tr><td>Group 21 </td><td>	Instruction effective-address-to-real-address translation (I-ERAT) miss. </td><td> (counter</td><td>
+<tr><td>Group 21 </td><td>	Instruction effective-address-to-real-address translation (I-ERAT) miss.  </td><td> (counter</td><td>
 	0x00: Count edges				[mandatory]
  <br />
 	0x00: Negative polarity				[optional ]
@@ -68,7 +68,7 @@
 
 </tr>
 
-<tr><td>Group 21 </td><td>	L1 Instruction cache miss cycles. Counts the cycles from the miss event until the returned instruction is dispatched or cancelled due to branch misprediction, completion restart, or exceptions (see Note 1). </td><td> (counter</td><td>
+<tr><td>Group 21 </td><td>	L1 Instruction cache miss cycles. Counts the cycles from the miss event until the returned instruction is dispatched or cancelled due to branch misprediction, completion restart, or exceptions (see Note 1).  </td><td> (counter</td><td>
 	0x00: Count edges				[optional ]
  <br />
 	0x01: Count cycles				[default ]
@@ -100,7 +100,7 @@
 
 </tr>
 
-<tr><td>Group 21 </td><td>	Instruction in pipeline stage EX7 causes a flush. </td><td> (counter</td><td>
+<tr><td>Group 21 </td><td>	Instruction in pipeline stage EX7 causes a flush.  </td><td> (counter</td><td>
 	0x00: Count edges				[mandatory]
  <br />
 	0x00: Negative polarity				[optional ]
@@ -115,7 +115,7 @@
 
 </tr>
 
-<tr><td>Group 21 </td><td>	Two PowerPC instructions committed. For microcode sequences, only the last microcode operation is counted. Committed instructions are counted two at a time. If only one instruction has committed for a given cycle, this event will not be raised until another instruction has been committed in a future cycle. </td><td> (counter</td><td>
+<tr><td>Group 21 </td><td>	Two PowerPC instructions committed. For microcode sequences, only the last microcode operation is counted. Committed instructions are counted two at a time. If only one instruction has committed for a given cycle, this event will not be raised until another instruction has been committed in a future cycle.  </td><td> (counter</td><td>
 	0x00: Count edges				[mandatory]
  <br />
 	0x00: Negative polarity				[optional ]
@@ -130,7 +130,7 @@
 
 </tr>
 
-<tr><td>Group 22 </td><td>	Data effective-address-to-real-address translation (D-ERAT) miss. Not speculative. </td><td> (counter</td><td>
+<tr><td>Group 22 </td><td>	Data effective-address-to-real-address translation (D-ERAT) miss. Not speculative.  </td><td> (counter</td><td>
 	0x01: Count cycles				[mandatory]
  <br />
 	0x00: Negative polarity				[optional ]
@@ -160,7 +160,7 @@
 
 </tr>
 
-<tr><td>Group 22 </td><td>	Load valid at a particular pipe stage. Speculative, since flushed operations are counted as well. Counts microcoded PPE sequences more than once. Misaligned flushes might be counted the first time as well. Load operations include all loads that read data from the cache, dcbt and dcbtst. Does not include load Vector/SIMD multimedia extension pattern instructions. </td><td> (counter</td><td>
+<tr><td>Group 22 </td><td>	Load valid at a particular pipe stage. Speculative, since flushed operations are counted as well. Counts microcoded PPE sequences more than once. Misaligned flushes might be counted the first time as well. Load operations include all loads that read data from the cache, dcbt and dcbtst. Does not include load Vector/SIMD multimedia extension pattern instructions.  </td><td> (counter</td><td>
 	0x01: Count cycles				[mandatory]
  <br />
 	0x00: Negative polarity				[optional ]
@@ -175,7 +175,7 @@
 
 </tr>
 
-<tr><td>Group 22 </td><td>	L1 D-cache load miss. Pulsed when there is a miss request that has a tag miss but not an ERAT miss. Speculative, since flushed operations are counted as well. </td><td> (counter</td><td>
+<tr><td>Group 22 </td><td>	L1 D-cache load miss. Pulsed when there is a miss request that has a tag miss but not an ERAT miss. Speculative, since flushed operations are counted as well.  </td><td> (counter</td><td>
 	0x01: Count cycles				[mandatory]
  <br />
 	0x00: Negative polarity				[optional ]

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