Diff of /docs/ppc-e300-events [9766c7] .. [28a31d]  Maximize  Restore

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--- a/docs/ppc-e300-events
+++ b/docs/ppc-e300-events
@@ -58,62 +58,62 @@
 
 </tr>
 
-<tr><td>ISSUE_STALLED</td><td>	Cycles the issue buffer is not empty but 0 instructions issued </td><td> all</td><td>
+<tr><td>ISSUE_STALLED</td><td>	Cycles the issue buffer is not empty but 0 instructions issued  </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>CACHEINHIBITED_ACCESSES_TRANSLATED</td><td>	Number of cache inhibited accesses translated </td><td> all</td><td>
+<tr><td>CACHEINHIBITED_ACCESSES_TRANSLATED</td><td>	Number of cache inhibited accesses translated  </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>FETCHES</td><td>	Counts the number of fetches that write at least one instruction to the instruction buffer. (With instruction fetched, can used to compute instructions-per-fetch) </td><td> all</td><td>
+<tr><td>FETCHES</td><td>	Counts the number of fetches that write at least one instruction to the instruction buffer. (With instruction fetched, can used to compute instructions-per-fetch)  </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>MMU_MISSES</td><td>	Counts instruction TLB miss exceptions </td><td> all</td><td>
+<tr><td>MMU_MISSES</td><td>	Counts instruction TLB miss exceptions  </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>BIU_MASTER_REQUESTS</td><td>	Number of master transactions. (Number of master TSs.) </td><td> all</td><td>
+<tr><td>BIU_MASTER_REQUESTS</td><td>	Number of master transactions. (Number of master TSs.)  </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>BIU_MASTER_I_REQUESTS</td><td>	Number of master I-Side transactions. (Number of master I-Side TSs.) </td><td> all</td><td>
+<tr><td>BIU_MASTER_I_REQUESTS</td><td>	Number of master I-Side transactions. (Number of master I-Side TSs.)  </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>BIU_MASTER_D_REQUESTS</td><td>	Number of master D-Side transactions. (Number of master D-Side TSs.) </td><td> all</td><td>
+<tr><td>BIU_MASTER_D_REQUESTS</td><td>	Number of master D-Side transactions. (Number of master D-Side TSs.)  </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>BIU_MASTER_RETRIES</td><td>	Number of transactions which were initiated by this processor which were retried on the BIU interface. (Number of master ARTRYs.) </td><td> all</td><td>
+<tr><td>BIU_MASTER_RETRIES</td><td>	Number of transactions which were initiated by this processor which were retried on the BIU interface. (Number of master ARTRYs.)  </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>SNOOP_PUSHES</td><td>	Number of snoop pushes from all D-side resources. (Counts snoop ARTRY/WOPs.) </td><td> all</td><td>
+<tr><td>SNOOP_PUSHES</td><td>	Number of snoop pushes from all D-side resources. (Counts snoop ARTRY/WOPs.)  </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>PMC0_OVERFLOW</td><td>	Counts the number of times PMC0[32] transitioned from 1 to 0. </td><td> all</td><td>
+<tr><td>PMC0_OVERFLOW</td><td>	Counts the number of times PMC0[32] transitioned from 1 to 0.  </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>PMC1_OVERFLOW</td><td>	Counts the number of times PMC1[32] transitioned from 1 to 0. </td><td> all</td><td>
+<tr><td>PMC1_OVERFLOW</td><td>	Counts the number of times PMC1[32] transitioned from 1 to 0.  </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>PMC2_OVERFLOW</td><td>	Counts the number of times PMC2[32] transitioned from 1 to 0. </td><td> all</td><td>
+<tr><td>PMC2_OVERFLOW</td><td>	Counts the number of times PMC2[32] transitioned from 1 to 0.  </td><td> all</td><td>
 </td>
 
 </tr>
@@ -148,7 +148,7 @@
 
 </tr>
 
-<tr><td>I_CACHE_HIT</td><td>	Number if fetches that hit in i-cache </td><td> all</td><td>
+<tr><td>I_CACHE_HIT</td><td>	Number if fetches that hit in i-cache  </td><td> all</td><td>
 </td>
 
 </tr>

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