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<tr><td>CYCLES</td><td>	0-0 Cycles </td><td> all</td><td>
</td>

</tr>

<tr><td>INSTRUCTIONS</td><td>	1-0 Instructions completed </td><td> all</td><td>
</td>

</tr>

<tr><td>DCACHE_MISSES</td><td>	11-0 Data cache misses </td><td> all</td><td>
</td>

</tr>

<tr><td>BRANCH_INSNS</td><td>	2-0 Branch instructions (whether completed or mispredicted) </td><td> 0</td><td>
</td>

</tr>

<tr><td>JR_31_INSNS</td><td>	3-0 JR $31 (return) instructions executed </td><td> 0</td><td>
</td>

</tr>

<tr><td>JR_NON_31_INSNS</td><td>	4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict) </td><td> 0</td><td>
</td>

</tr>

<tr><td>ITLB_ACCESSES</td><td>	5-0 Instruction micro-TLB accesses </td><td> 0</td><td>
</td>

</tr>

<tr><td>DTLB_ACCESSES</td><td>	6-0 Data micro-TLB accesses </td><td> 0</td><td>
</td>

</tr>

<tr><td>JTLB_INSN_ACCESSES</td><td>	7-0 Joint TLB instruction accesses </td><td> 0</td><td>
</td>

</tr>

<tr><td>JTLB_DATA_ACCESSES</td><td>	8-0 Joint TLB data (non-instruction) accesses </td><td> 0</td><td>
</td>

</tr>

<tr><td>ICACHE_ACCESSES</td><td>	9-0 Instruction cache accesses </td><td> 0</td><td>
</td>

</tr>

<tr><td>DCACHE_ACCESSES</td><td>	10-0 Data cache accesses </td><td> 0</td><td>
</td>

</tr>

<tr><td>STORE_MISS_INSNS</td><td>	13-0 Cacheable stores that miss in the cache </td><td> 0</td><td>
</td>

</tr>

<tr><td>INTEGER_INSNS</td><td>	14-0 Integer instructions completed </td><td> 0</td><td>
</td>

</tr>

<tr><td>LOAD_INSNS</td><td>	15-0 Load instructions completed (including FP) </td><td> 0</td><td>
</td>

</tr>

<tr><td>J_JAL_INSNS</td><td>	16-0 J/JAL instructions completed </td><td> 0</td><td>
</td>

</tr>

<tr><td>NO_OPS_INSNS</td><td>	17-0 no-ops completed, ie instructions writing $0 </td><td> 0</td><td>
</td>

</tr>

<tr><td>ALL_STALLS</td><td>	18-0 Stall cycles, including ALU and IFU </td><td> 0</td><td>
</td>

</tr>

<tr><td>SC_INSNS</td><td>	19-0 SC instructions completed </td><td> 0</td><td>
</td>

</tr>

<tr><td>PREFETCH_INSNS</td><td>	20-0 PREFETCH instructions completed </td><td> 0</td><td>
</td>

</tr>

<tr><td>L2_CACHE_WRITEBACKS</td><td>	21-0 L2 cache lines written back to memory </td><td> 0</td><td>
</td>

</tr>

<tr><td>L2_CACHE_MISSES</td><td>	22-0 L2 cache accesses that missed in the cache </td><td> 0</td><td>
</td>

</tr>

<tr><td>EXCEPTIONS_TAKEN</td><td>	23-0 Exceptions taken </td><td> 0</td><td>
</td>

</tr>

<tr><td>CACHE_FIXUP_CYCLES</td><td>	24-0 Cache fixup cycles (specific to the 34K family microarchitecture) </td><td> 0</td><td>
</td>

</tr>

<tr><td>IFU_STALLS</td><td>	25-0 IFU stall cycles </td><td> 0</td><td>
</td>

</tr>

<tr><td>DSP_INSNS</td><td>	26-0 DSP instructions completed </td><td> 0</td><td>
</td>

</tr>

<tr><td>POLICY_EVENTS</td><td>	28-0 Implementation specific policy manager events </td><td> 0</td><td>
</td>

</tr>

<tr><td>ISPRAM_EVENTS</td><td>	29-0 Implementation specific ISPRAM events </td><td> 0</td><td>
</td>

</tr>

<tr><td>COREEXTEND_EVENTS</td><td>	30-0 Implementation specific CorExtend events </td><td> 0</td><td>
</td>

</tr>

<tr><td>YIELD_EVENTS</td><td>	31-0 Implementation specific yield events </td><td> 0</td><td>
</td>

</tr>

<tr><td>ITC_LOADS</td><td>	32-0 ITC Loads </td><td> 0</td><td>
</td>

</tr>

<tr><td>UNCACHED_LOAD_INSNS</td><td>	33-0 Uncached load instructions </td><td> 0</td><td>
</td>

</tr>

<tr><td>FORK_INSNS</td><td>	34-0 Fork instructions completed </td><td> 0</td><td>
</td>

</tr>

<tr><td>CP2_ARITH_INSNS</td><td>	35-0 CP2 arithmetic instructions completed </td><td> 0</td><td>
</td>

</tr>

<tr><td>INTERVENTION_STALLS</td><td>	36-0 Cache coherence intervention processing stall cycles </td><td> 0</td><td>
</td>

</tr>

<tr><td>ICACHE_MISS_STALLS</td><td>	37-0 Stall cycles due to an instruction cache miss </td><td> 0</td><td>
</td>

</tr>

<tr><td>DCACHE_MISS_CYCLES</td><td>	39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline </td><td> 0</td><td>
</td>

</tr>

<tr><td>UNCACHED_STALLS</td><td>	40-0 Uncached stall cycles </td><td> 0</td><td>
</td>

</tr>

<tr><td>MDU_STALLS</td><td>	41-0 MDU stall cycles </td><td> 0</td><td>
</td>

</tr>

<tr><td>CP2_STALLS</td><td>	42-0 CP2 stall cycles </td><td> 0</td><td>
</td>

</tr>

<tr><td>ISPRAM_STALLS</td><td>	43-0 ISPRAM stall cycles </td><td> 0</td><td>
</td>

</tr>

<tr><td>CACHE_INSN_STALLS</td><td>	44-0 Stall cycless due to CACHE instructions </td><td> 0</td><td>
</td>

</tr>

<tr><td>LOAD_USE_STALLS</td><td>	45-0 Load to use stall cycles </td><td> 0</td><td>
</td>

</tr>

<tr><td>INTERLOCK_STALLS</td><td>	46-0 Stall cycles due to return data from MFC0, RDHWR, and MFTR instructions </td><td> 0</td><td>
</td>

</tr>

<tr><td>RELAX_STALLS</td><td>	47-0 Low power stall cycles (operations) as requested by the policy manager </td><td> 0</td><td>
</td>

</tr>

<tr><td>IFU_FB_FULL_REFETCHES</td><td>	48-0 Refetches due to cache misses while both fill buffers already allocated </td><td> 0</td><td>
</td>

</tr>

<tr><td>EJTAG_INSN_TRIGGERS</td><td>	49-0 EJTAG instruction triggerpoints </td><td> 0</td><td>
</td>

</tr>

<tr><td>FSB_LESS_25_FULL</td><td>	50-0 FSB < 25% full </td><td> 0</td><td>
</td>

</tr>

<tr><td>FSB_OVER_50_FULL</td><td>	51-0 FSB > 50% full </td><td> 0</td><td>
</td>

</tr>

<tr><td>LDQ_LESS_25_FULL</td><td>	52-0 LDQ < 25% full </td><td> 0</td><td>
</td>

</tr>

<tr><td>LDQ_OVER_50_FULL</td><td>	53-0 LDQ > 50% full </td><td> 0</td><td>
</td>

</tr>

<tr><td>WBB_LESS_25_FULL</td><td>	54-0 WBB < 25% full </td><td> 0</td><td>
</td>

</tr>

<tr><td>WBB_OVER_50_FULL</td><td>	55-0 WBB > 50% full </td><td> 0</td><td>
</td>

</tr>

<tr><td>INTERVENTION_HIT_COUNT</td><td>	56-0 External interventions that hit in the cache  </td><td> 0</td><td>
</td>

</tr>

<tr><td>INVALIDATE_INTERVENTION_COUNT</td><td>	57-0 External invalidate (i.e. leaving a cache line in the invalid state) interventions </td><td> 0</td><td>
</td>

</tr>

<tr><td>EVICTION_COUNT</td><td>	58-0 Cache lines written back due to cache replacement or non-coherent cache operation </td><td> 0</td><td>
</td>

</tr>

<tr><td>MESI_INVAL_COUNT</td><td>	59-0 MESI protocol transitions into invalid state </td><td> 0</td><td>
</td>

</tr>

<tr><td>MESI_MODIFIED_COUNT</td><td>	60-0 MESI protocol transitions into modified state </td><td> 0</td><td>
</td>

</tr>

<tr><td>SELF_INTERVENTION_LATENCY</td><td>	61-0 Latency from miss detection to self intervention </td><td> 0</td><td>
</td>

</tr>

<tr><td>READ_RESPONSE_LATENCY</td><td>	62-0 Read latency from miss detection until critical dword of response is returned </td><td> 0</td><td>
</td>

</tr>

<tr><td>MISPREDICTED_BRANCH_INSNS</td><td>	2-1 Branch mispredictions </td><td> 1</td><td>
</td>

</tr>

<tr><td>JR_31_MISPREDICTIONS</td><td>	3-1 JR $31 mispredictions </td><td> 1</td><td>
</td>

</tr>

<tr><td>JR_31_NO_PREDICTIONS</td><td>	4-1 JR $31 not predicted (stack mismatch). </td><td> 1</td><td>
</td>

</tr>

<tr><td>ITLB_MISSES</td><td>	5-1 Instruction micro-TLB misses </td><td> 1</td><td>
</td>

</tr>

<tr><td>DTLB_MISSES</td><td>	6-1 Data micro-TLB misses </td><td> 1</td><td>
</td>

</tr>

<tr><td>JTLB_INSN_MISSES</td><td>	7-1 Joint TLB instruction misses </td><td> 1</td><td>
</td>

</tr>

<tr><td>JTLB_DATA_MISSES</td><td>	8-1 Joint TLB data (non-instruction) misses </td><td> 1</td><td>
</td>

</tr>

<tr><td>ICACHE_MISSES</td><td>	9-1 Instruction cache misses </td><td> 1</td><td>
</td>

</tr>

<tr><td>DCACHE_WRITEBACKS</td><td>	10-1 Data cache lines written back to memory </td><td> 1</td><td>
</td>

</tr>

<tr><td>LOAD_MISS_INSNS</td><td>	13-1 Cacheable load instructions that miss in the cache </td><td> 1</td><td>
</td>

</tr>

<tr><td>FPU_INSNS</td><td>	14-1 FPU instructions completed (not including loads/stores) </td><td> 1</td><td>
</td>

</tr>

<tr><td>STORE_INSNS</td><td>	15-1 Stores completed (including FP) </td><td> 1</td><td>
</td>

</tr>

<tr><td>MIPS16_INSNS</td><td>	16-1 MIPS16 instructions completed </td><td> 1</td><td>
</td>

</tr>

<tr><td>INT_MUL_DIV_INSNS</td><td>	17-1 Integer multiply/divide instructions completed </td><td> 1</td><td>
</td>

</tr>

<tr><td>REPLAYED_INSNS</td><td>	18-1 Replayed instructions </td><td> 1</td><td>
</td>

</tr>

<tr><td>SC_INSNS_FAILED</td><td>	19-1 SC instructions completed, but store failed (because the link bit had been cleared) </td><td> 1</td><td>
</td>

</tr>

<tr><td>CACHE_HIT_PREFETCH_INSNS</td><td>	20-1 PREFETCH instructions completed with cache hit </td><td> 1</td><td>
</td>

</tr>

<tr><td>L2_CACHE_ACCESSES</td><td>	21-1 Accesses to the L2 cache </td><td> 1</td><td>
</td>

</tr>

<tr><td>L2_CACHE_SINGLE_BIT_ERRORS</td><td>	22-1 Single bit errors corrected in L2 </td><td> 1</td><td>
</td>

</tr>

<tr><td>SINGLE_THREADED_CYCLES</td><td>	23-1 Cycles while one and only one TC is eligible for scheduling </td><td> 1</td><td>
</td>

</tr>

<tr><td>REFETCHED_INSNS</td><td>	24-1 Replayed instructions sent back to IFU to be refetched </td><td> 1</td><td>
</td>

</tr>

<tr><td>ALU_STALLS</td><td>	25-1 ALU stall cycles </td><td> 1</td><td>
</td>

</tr>

<tr><td>ALU_DSP_SATURATION_INSNS</td><td>	26-1 ALU-DSP saturation instructions </td><td> 1</td><td>
</td>

</tr>

<tr><td>MDU_DSP_SATURATION_INSNS</td><td>	27-1 MDU-DSP saturation instructions </td><td> 1</td><td>
</td>

</tr>

<tr><td>CP2_EVENTS</td><td>	28-1 Implementation specific CP2 events </td><td> 1</td><td>
</td>

</tr>

<tr><td>DSPRAM_EVENTS</td><td>	29-1 Implementation specific DSPRAM events </td><td> 1</td><td>
</td>

</tr>

<tr><td>ITC_EVENT</td><td>	31-1 Implementation specific yield event </td><td> 1</td><td>
</td>

</tr>

<tr><td>UNCACHED_STORE_INSNS</td><td>	33-1 Uncached store instructions </td><td> 1</td><td>
</td>

</tr>

<tr><td>CP2_TO_FROM_INSNS</td><td>	35-1 CP2 to/from instructions (moves, control, loads, stores) </td><td> 1</td><td>
</td>

</tr>

<tr><td>INTERVENTION_MISS_STALLS</td><td>	36-1 Cache coherence intervention processing stall cycles due to an earlier miss </td><td> 1</td><td>
</td>

</tr>

<tr><td>DCACHE_MISS_STALLS</td><td>	37-1 Stall cycles due to a data cache miss </td><td> 1</td><td>
</td>

</tr>

<tr><td>FSB_INDEX_CONFLICT_STALLS</td><td>	38-1 FSB (fill/store buffer) index conflict stall cycles </td><td> 1</td><td>
</td>

</tr>

<tr><td>L2_CACHE_MISS_CYCLES</td><td>	39-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline </td><td> 1</td><td>
</td>

</tr>

<tr><td>ITC_STALLS</td><td>	40-1 ITC stall cycles </td><td> 1</td><td>
</td>

</tr>

<tr><td>FPU_STALLS</td><td>	41-1 FPU stall cycles </td><td> 1</td><td>
</td>

</tr>

<tr><td>COREEXTEND_STALLS</td><td>	42-1 CorExtend stall cycles </td><td> 1</td><td>
</td>

</tr>

<tr><td>DSPRAM_STALLS</td><td>	43-1 DSPRAM stall cycles </td><td> 1</td><td>
</td>

</tr>

<tr><td>ALU_TO_AGEN_STALLS</td><td>	45-1 ALU to AGEN stall cycles </td><td> 1</td><td>
</td>

</tr>

<tr><td>MISPREDICTION_STALLS</td><td>	46-1 Branch mispredict stall cycles </td><td> 1</td><td>
</td>

</tr>

<tr><td>FB_ENTRY_ALLOCATED_CYCLES</td><td>	48-1 Cycles while at least one IFU fill buffer is allocated </td><td> 1</td><td>
</td>

</tr>

<tr><td>EJTAG_DATA_TRIGGERS</td><td>	49-1 EJTAG Data triggerpoints </td><td> 1</td><td>
</td>

</tr>

<tr><td>FSB_25_50_FULL</td><td>	50-1 FSB 25-50% full </td><td> 1</td><td>
</td>

</tr>

<tr><td>FSB_FULL_STALLS</td><td>	51-1 FSB full pipeline stall cycles </td><td> 1</td><td>
</td>

</tr>

<tr><td>LDQ_25_50_FULL</td><td>	52-1 LDQ 25-50% full </td><td> 1</td><td>
</td>

</tr>

<tr><td>LDQ_FULL_STALLS</td><td>	53-1 LDQ full pipeline stall cycles </td><td> 1</td><td>
</td>

</tr>

<tr><td>WBB_25_50_FULL</td><td>	54-1 WBB 25-50% full </td><td> 1</td><td>
</td>

</tr>

<tr><td>WBB_FULL_STALLS</td><td>	55-1 WBB full pipeline stall cycles </td><td> 1</td><td>
</td>

</tr>

<tr><td>INTERVENTION_COUNT</td><td>	56-1 External interventions </td><td> 1</td><td>
</td>

</tr>

<tr><td>INVALIDATE_INTERVENTION_HIT_COUNT</td><td>	57-1 External invalidate interventions that hit in the cache </td><td> 1</td><td>
</td>

</tr>

<tr><td>WRITEBACK_COUNT</td><td>	58-1 Cache lines written back due to cache replacement or any cache operation (non-coherent, self, or external coherent) </td><td> 1</td><td>
</td>

</tr>

<tr><td>MESI_EXCLUSIVE_COUNT</td><td>	59-1 MESI protocol transitions into exclusive state </td><td> 1</td><td>
</td>

</tr>

<tr><td>MESI_SHARED_COUNT</td><td>	60-1 MESI protocol transitions into shared state </td><td> 1</td><td>
</td>

</tr>

<tr><td>SELF_INTERVENTION_COUNT</td><td>	61-1 Self intervention requests on miss detection </td><td> 1</td><td>
</td>

</tr>

<tr><td>READ_RESPONSE_COUNT</td><td>	62-1 Read requests on miss detection </td><td> 1</td><td>
</td>

</tr>

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