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37
<tr><td>BR_MISS_PRED_RETIRED</td><td>   number of mispredicted branches retired (precise) </td><td> all</td><td>
37
<tr><td>BR_MISS_PRED_RETIRED</td><td>   number of mispredicted branches retired (precise) </td><td> all</td><td>
38
</td>
38
</td>
39
39
40
</tr>
40
</tr>
41
41
42
<tr><td>LOAD_BLOCK</td><td> Loads that partially overlap an earlier store </td><td> 0, 1, 2, 3</td><td>
42
<tr><td>LOAD_BLOCK</td><td> Loads that partially overlap an earlier store </td><td> all</td><td>
43
    0x02: No unit mask
43
    0x02: No unit mask
44
 <br />
44
 <br />
45
</td>
45
</td>
46
46
47
</tr>
47
</tr>
48
48
49
<tr><td>SB_DRAIN</td><td>   All Store buffer stall cycles </td><td> 0, 1, 2, 3</td><td>
49
<tr><td>SB_DRAIN</td><td>   All Store buffer stall cycles </td><td> all</td><td>
50
    0x07: No unit mask
50
    0x07: No unit mask
51
 <br />
51
 <br />
52
</td>
52
</td>
53
53
54
</tr>
54
</tr>
55
55
56
<tr><td>MISALIGN_MEM_REF</td><td>   Misaligned store references </td><td> 0, 1, 2, 3</td><td>
56
<tr><td>MISALIGN_MEM_REF</td><td>   Misaligned store references </td><td> all</td><td>
57
    0x02: No unit mask
57
    0x02: No unit mask
58
 <br />
58
 <br />
59
</td>
59
</td>
60
60
61
</tr>
61
</tr>
62
62
63
<tr><td>STORE_BLOCKS</td><td>   Loads delayed with at-Retirement block code </td><td> 0, 1, 2, 3</td><td>
63
<tr><td>STORE_BLOCKS</td><td>   Loads delayed with at-Retirement block code </td><td> all</td><td>
64
    0x04: at_ret Loads delayed with at-Retirement block code
64
    0x04: (name=at_ret) Loads delayed with at-Retirement block code
65
 <br />
65
 <br />
66
    0x08: l1d_block Cacheable loads delayed with L1D block code
66
    0x08: (name=l1d_block) Cacheable loads delayed with L1D block code
67
 <br />
67
 <br />
68
</td>
69
70
</tr>
68
</td>
71
69
70
</tr>
71
72
<tr><td>PARTIAL_ADDRESS_ALIAS</td><td>  False dependencies due to partial address aliasing </td><td> 0, 1, 2, 3</td><td>
72
<tr><td>PARTIAL_ADDRESS_ALIAS</td><td>  False dependencies due to partial address aliasing </td><td> all</td><td>
73
    0x01: No unit mask
73
    0x01: No unit mask
74
 <br />
74
 <br />
75
</td>
76
77
</tr>
75
</td>
78
76
77
</tr>
78
79
<tr><td>DTLB_LOAD_MISSES</td><td>   DTLB load misses </td><td> 0, 1, 2, 3</td><td>
79
<tr><td>DTLB_LOAD_MISSES</td><td>   DTLB load misses </td><td> all</td><td>
80
    0x01: any DTLB load misses
80
    0x01: (name=any) DTLB load misses
81
 <br />
81
 <br />
82
    0x02: walk_completed DTLB load miss page walks complete
82
    0x02: (name=walk_completed) DTLB load miss page walks complete
83
 <br />
83
 <br />
84
    0x04: walk_cycles DTLB load miss page walk cycles
84
    0x04: (name=walk_cycles) DTLB load miss page walk cycles
85
 <br />
85
 <br />
86
    0x10: stlb_hit DTLB second level hit
86
    0x10: (name=stlb_hit) DTLB second level hit
87
 <br />
87
 <br />
88
    0x20: pde_miss DTLB load miss caused by low part of address
88
    0x20: (name=pde_miss) DTLB load miss caused by low part of address
89
 <br />
89
 <br />
90
    0x80: large_walk_completed DTLB load miss large page walks
90
    0x80: (name=large_walk_completed) DTLB load miss large page walks
91
 <br />
91
 <br />
92
</td>
93
94
</tr>
92
</td>
95
93
94
</tr>
95
96
<tr><td>MEM_INST_RETIRED</td><td>   Memory instructions retired above 0 clocks (Precise Event) </td><td> 0, 1, 2, 3</td><td>
96
<tr><td>MEM_INST_RETIRED</td><td>   Memory instructions retired above 0 clocks (Precise Event) </td><td> all</td><td>
97
    0x01: loads Instructions retired which contains a load (Precise Event)
97
    0x01: (name=loads) Instructions retired which contains a load (Precise Event)
98
 <br />
98
 <br />
99
    0x02: stores Instructions retired which contains a store (Precise Event)
99
    0x02: (name=stores) Instructions retired which contains a store (Precise Event)
100
 <br />
100
 <br />
101
</td>
102
103
</tr>
101
</td>
104
102
103
</tr>
104
105
<tr><td>MEM_STORE_RETIRED</td><td>  Retired stores that miss the DTLB (Precise Event) </td><td> 0, 1, 2, 3</td><td>
105
<tr><td>MEM_STORE_RETIRED</td><td>  Retired stores that miss the DTLB (Precise Event) </td><td> all</td><td>
106
    0x01: No unit mask
106
    0x01: No unit mask
107
 <br />
107
 <br />
108
</td>
109
110
</tr>
108
</td>
111
109
110
</tr>
111
112
<tr><td>UOPS_ISSUED</td><td>    Uops issued </td><td> 0, 1, 2, 3</td><td>
112
<tr><td>UOPS_ISSUED</td><td>    Uops issued </td><td> all</td><td>
113
    0x01: any Uops issued
113
    0x01: (name=any) Uops issued
114
 <br />
114
 <br />
115
    0x02: fused Fused Uops issued
115
    0x02: (name=fused) Fused Uops issued
116
 <br />
116
 <br />
117
</td>
118
119
</tr>
117
</td>
120
118
119
</tr>
120
121
<tr><td>MEM_UNCORE_RETIRED</td><td> Load instructions retired that HIT modified data in sibling core (Precise Event) </td><td> 0, 1, 2, 3</td><td>
121
<tr><td>MEM_UNCORE_RETIRED</td><td> Load instructions retired that HIT modified data in sibling core (Precise Event) </td><td> all</td><td>
122
    0x02: local_hitm Load instructions retired that HIT modified data in sibling core (Precise Event)
122
    0x02: (name=local_hitm) Load instructions retired that HIT modified data in sibling core (Precise Event)
123
 <br />
123
 <br />
124
    0x04: remote_hitm Retired loads that hit remote socket in modified state (Precise Event)
124
    0x04: (name=remote_hitm) Retired loads that hit remote socket in modified state (Precise Event)
125
 <br />
125
 <br />
126
    0x08: local_dram_and_remote_cache_hit Load instructions retired local dram and remote cache HIT data sources (Precise Event)
126
    0x08: (name=local_dram_and_remote_cache_hit) Load instructions retired local dram and remote cache HIT data sources (Precise Event)
127
 <br />
127
 <br />
128
    0x10: remote_dram Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)
128
    0x10: (name=remote_dram) Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)
129
 <br />
129
 <br />
130
    0x80: uncacheable Load instructions retired IO (Precise Event)
130
    0x80: (name=uncacheable) Load instructions retired IO (Precise Event)
131
 <br />
131
 <br />
132
</td>
133
134
</tr>
132
</td>
135
133
134
</tr>
135
136
<tr><td>FP_COMP_OPS_EXE</td><td>    MMX Uops </td><td> 0, 1, 2, 3</td><td>
136
<tr><td>FP_COMP_OPS_EXE</td><td>    MMX Uops </td><td> all</td><td>
137
    0x01: x87 Computational floating-point operations executed
137
    0x01: (name=x87) Computational floating-point operations executed
138
 <br />
138
 <br />
139
    0x02: mmx MMX Uops
139
    0x02: (name=mmx) MMX Uops
140
 <br />
140
 <br />
141
    0x04: sse_fp SSE and SSE2 FP Uops
141
    0x04: (name=sse_fp) SSE and SSE2 FP Uops
142
 <br />
142
 <br />
143
    0x08: sse2_integer SSE2 integer Uops
143
    0x08: (name=sse2_integer) SSE2 integer Uops
144
 <br />
144
 <br />
145
    0x10: sse_fp_packed SSE FP packed Uops
145
    0x10: (name=sse_fp_packed) SSE FP packed Uops
146
 <br />
146
 <br />
147
    0x20: sse_fp_scalar SSE FP scalar Uops
147
    0x20: (name=sse_fp_scalar) SSE FP scalar Uops
148
 <br />
148
 <br />
149
    0x40: sse_single_precision SSE* FP single precision Uops
149
    0x40: (name=sse_single_precision) SSE* FP single precision Uops
150
 <br />
150
 <br />
151
    0x80: sse_double_precision SSE* FP double precision Uops
151
    0x80: (name=sse_double_precision) SSE* FP double precision Uops
152
 <br />
152
 <br />
153
</td>
154
155
</tr>
153
</td>
156
154
155
</tr>
156
157
<tr><td>SIMD_INT_128</td><td>   128 bit SIMD integer pack operations </td><td> 0, 1, 2, 3</td><td>
157
<tr><td>SIMD_INT_128</td><td>   128 bit SIMD integer pack operations </td><td> all</td><td>
158
    0x01: packed_mpy 128 bit SIMD integer multiply operations
158
    0x01: (name=packed_mpy) 128 bit SIMD integer multiply operations
159
 <br />
159
 <br />
160
    0x02: packed_shift 128 bit SIMD integer shift operations
160
    0x02: (name=packed_shift) 128 bit SIMD integer shift operations
161
 <br />
161
 <br />
162
    0x04: pack 128 bit SIMD integer pack operations
162
    0x04: (name=pack) 128 bit SIMD integer pack operations
163
 <br />
163
 <br />
164
    0x08: unpack 128 bit SIMD integer unpack operations
164
    0x08: (name=unpack) 128 bit SIMD integer unpack operations
165
 <br />
165
 <br />
166
    0x10: packed_logical 128 bit SIMD integer logical operations
166
    0x10: (name=packed_logical) 128 bit SIMD integer logical operations
167
 <br />
167
 <br />
168
    0x20: packed_arith 128 bit SIMD integer arithmetic operations
168
    0x20: (name=packed_arith) 128 bit SIMD integer arithmetic operations
169
 <br />
169
 <br />
170
    0x40: shuffle_move 128 bit SIMD integer shuffle/move operations
170
    0x40: (name=shuffle_move) 128 bit SIMD integer shuffle/move operations
171
 <br />
171
 <br />
172
</td>
173
174
</tr>
172
</td>
175
173
174
</tr>
175
176
<tr><td>LOAD_DISPATCH</td><td>  All loads dispatched </td><td> 0, 1, 2, 3</td><td>
176
<tr><td>LOAD_DISPATCH</td><td>  All loads dispatched </td><td> all</td><td>
177
    0x01: rs Loads dispatched that bypass the MOB
177
    0x01: (name=rs) Loads dispatched that bypass the MOB
178
 <br />
178
 <br />
179
    0x02: rs_delayed Loads dispatched from stage 305
179
    0x02: (name=rs_delayed) Loads dispatched from stage 305
180
 <br />
180
 <br />
181
    0x04: mob Loads dispatched from the MOB
181
    0x04: (name=mob) Loads dispatched from the MOB
182
 <br />
182
 <br />
183
    0x07: any All loads dispatched
183
    0x07: (name=any) All loads dispatched
184
 <br />
184
 <br />
185
</td>
186
187
</tr>
185
</td>
188
186
187
</tr>
188
189
<tr><td>ARITH</td><td>  Cycles the divider is busy </td><td> 0, 1, 2, 3</td><td>
189
<tr><td>ARITH</td><td>  Cycles the divider is busy </td><td> all</td><td>
190
    0x01: cycles_div_busy Cycles the divider is busy
190
    0x01: (name=cycles_div_busy) Cycles the divider is busy
191
 <br />
191
 <br />
192
    0x02: mul Multiply operations executed
192
    0x02: (name=mul) Multiply operations executed
193
 <br />
193
 <br />
194
</td>
195
196
</tr>
194
</td>
197
195
196
</tr>
197
198
<tr><td>INST_QUEUE_WRITES</td><td>  Instructions written to instruction queue. </td><td> 0, 1, 2, 3</td><td>
198
<tr><td>INST_QUEUE_WRITES</td><td>  Instructions written to instruction queue. </td><td> all</td><td>
199
    0x01: No unit mask
199
    0x01: No unit mask
200
 <br />
200
 <br />
201
</td>
202
203
</tr>
201
</td>
204
202
203
</tr>
204
205
<tr><td>INST_DECODED</td><td>   Instructions that must be decoded by decoder 0 </td><td> 0, 1, 2, 3</td><td>
205
<tr><td>INST_DECODED</td><td>   Instructions that must be decoded by decoder 0 </td><td> all</td><td>
206
    0x01: No unit mask
206
    0x01: No unit mask
207
 <br />
207
 <br />
208
</td>
209
210
</tr>
208
</td>
211
209
210
</tr>
211
212
<tr><td>TWO_UOP_INSTS_DECODED</td><td>  Two Uop instructions decoded </td><td> 0, 1, 2, 3</td><td>
212
<tr><td>TWO_UOP_INSTS_DECODED</td><td>  Two Uop instructions decoded </td><td> all</td><td>
213
    0x01: No unit mask
213
    0x01: No unit mask
214
 <br />
214
 <br />
215
</td>
216
217
</tr>
215
</td>
218
216
217
</tr>
218
219
<tr><td>INST_QUEUE_WRITE_CYCLES</td><td>    Cycles instructions are written to the instruction queue </td><td> 0, 1, 2, 3</td><td>
219
<tr><td>INST_QUEUE_WRITE_CYCLES</td><td>    Cycles instructions are written to the instruction queue </td><td> all</td><td>
220
    0x01: No unit mask
220
    0x01: No unit mask
221
 <br />
221
 <br />
222
</td>
223
224
</tr>
222
</td>
225
223
224
</tr>
225
226
<tr><td>LSD_OVERFLOW</td><td>   Loops that can't stream from the instruction queue </td><td> 0, 1, 2, 3</td><td>
226
<tr><td>LSD_OVERFLOW</td><td>   Loops that can't stream from the instruction queue </td><td> all</td><td>
227
    0x01: No unit mask
227
    0x01: No unit mask
228
 <br />
228
 <br />
229
</td>
230
231
</tr>
229
</td>
232
230
231
</tr>
232
233
<tr><td>L2_RQSTS</td><td>   L2 instruction fetch hits </td><td> 0, 1, 2, 3</td><td>
233
<tr><td>L2_RQSTS</td><td>   L2 instruction fetch hits </td><td> all</td><td>
234
    0x01: ld_hit L2 load hits
234
    0x01: (name=ld_hit) L2 load hits
235
 <br />
235
 <br />
236
    0x02: ld_miss L2 load misses
236
    0x02: (name=ld_miss) L2 load misses
237
 <br />
237
 <br />
238
    0x03: loads L2 requests
238
    0x03: (name=loads) L2 requests
239
 <br />
239
 <br />
240
    0x04: rfo_hit L2 RFO hits
240
    0x04: (name=rfo_hit) L2 RFO hits
241
 <br />
241
 <br />
242
    0x08: rfo_miss L2 RFO misses
242
    0x08: (name=rfo_miss) L2 RFO misses
243
 <br />
243
 <br />
244
    0x0c: rfos L2 RFO requests
244
    0x0c: (name=rfos) L2 RFO requests
245
 <br />
245
 <br />
246
    0x10: ifetch_hit L2 instruction fetch hits
246
    0x10: (name=ifetch_hit) L2 instruction fetch hits
247
 <br />
247
 <br />
248
    0x20: ifetch_miss L2 instruction fetch misses
248
    0x20: (name=ifetch_miss) L2 instruction fetch misses
249
 <br />
249
 <br />
250
    0x30: ifetches L2 instruction fetches
250
    0x30: (name=ifetches) L2 instruction fetches
251
 <br />
251
 <br />
252
    0x40: prefetch_hit L2 prefetch hits
252
    0x40: (name=prefetch_hit) L2 prefetch hits
253
 <br />
253
 <br />
254
    0x80: prefetch_miss L2 prefetch misses
254
    0x80: (name=prefetch_miss) L2 prefetch misses
255
 <br />
255
 <br />
256
    0xaa: miss All L2 misses
256
    0xaa: (name=miss) All L2 misses
257
 <br />
257
 <br />
258
    0xc0: prefetches All L2 prefetches
258
    0xc0: (name=prefetches) All L2 prefetches
259
 <br />
259
 <br />
260
    0xff: references All L2 requests
260
    0xff: (name=references) All L2 requests
261
 <br />
261
 <br />
262
</td>
263
264
</tr>
262
</td>
265
263
264
</tr>
265
266
<tr><td>L2_DATA_RQSTS</td><td>  All L2 data requests </td><td> 0, 1, 2, 3</td><td>
266
<tr><td>L2_DATA_RQSTS</td><td>  All L2 data requests </td><td> all</td><td>
267
    0x01: demand_i_state L2 data demand loads in I state (misses)
267
    0x01: (name=demand_i_state) L2 data demand loads in I state (misses)
268
 <br />
268
 <br />
269
    0x02: demand_s_state L2 data demand loads in S state
269
    0x02: (name=demand_s_state) L2 data demand loads in S state
270
 <br />
270
 <br />
271
    0x04: demand_e_state L2 data demand loads in E state
271
    0x04: (name=demand_e_state) L2 data demand loads in E state
272
 <br />
272
 <br />
273
    0x08: demand_m_state L2 data demand loads in M state
273
    0x08: (name=demand_m_state) L2 data demand loads in M state
274
 <br />
274
 <br />
275
    0x0f: demand_mesi L2 data demand requests
275
    0x0f: (name=demand_mesi) L2 data demand requests
276
 <br />
276
 <br />
277
    0x10: prefetch_i_state L2 data prefetches in the I state (misses)
277
    0x10: (name=prefetch_i_state) L2 data prefetches in the I state (misses)
278
 <br />
278
 <br />
279
    0x20: prefetch_s_state L2 data prefetches in the S state
279
    0x20: (name=prefetch_s_state) L2 data prefetches in the S state
280
 <br />
280
 <br />
281
    0x40: prefetch_e_state L2 data prefetches in E state
281
    0x40: (name=prefetch_e_state) L2 data prefetches in E state
282
 <br />
282
 <br />
283
    0x80: prefetch_m_state L2 data prefetches in M state
283
    0x80: (name=prefetch_m_state) L2 data prefetches in M state
284
 <br />
284
 <br />
285
    0xf0: prefetch_mesi All L2 data prefetches
285
    0xf0: (name=prefetch_mesi) All L2 data prefetches
286
 <br />
286
 <br />
287
    0xff: any All L2 data requests
287
    0xff: (name=any) All L2 data requests
288
 <br />
288
 <br />
289
</td>
290
291
</tr>
289
</td>
292
290
291
</tr>
292
293
<tr><td>L2_WRITE</td><td>   L2 demand lock RFOs in E state </td><td> 0, 1, 2, 3</td><td>
293
<tr><td>L2_WRITE</td><td>   L2 demand lock RFOs in E state </td><td> all</td><td>
294
    0x01: rfo_i_state L2 demand store RFOs in I state (misses)
294
    0x01: (name=rfo_i_state) L2 demand store RFOs in I state (misses)
295
 <br />
295
 <br />
296
    0x02: rfo_s_state L2 demand store RFOs in S state
296
    0x02: (name=rfo_s_state) L2 demand store RFOs in S state
297
 <br />
297
 <br />
298
    0x08: rfo_m_state L2 demand store RFOs in M state
298
    0x08: (name=rfo_m_state) L2 demand store RFOs in M state
299
 <br />
299
 <br />
300
    0x0e: rfo_hit All L2 demand store RFOs that hit the cache
300
    0x0e: (name=rfo_hit) All L2 demand store RFOs that hit the cache
301
 <br />
301
 <br />
302
    0x0f: rfo_mesi All L2 demand store RFOs
302
    0x0f: (name=rfo_mesi) All L2 demand store RFOs
303
 <br />
303
 <br />
304
    0x10: lock_i_state L2 demand lock RFOs in I state (misses)
304
    0x10: (name=lock_i_state) L2 demand lock RFOs in I state (misses)
305
 <br />
305
 <br />
306
    0x20: lock_s_state L2 demand lock RFOs in S state
306
    0x20: (name=lock_s_state) L2 demand lock RFOs in S state
307
 <br />
307
 <br />
308
    0x40: lock_e_state L2 demand lock RFOs in E state
308
    0x40: (name=lock_e_state) L2 demand lock RFOs in E state
309
 <br />
309
 <br />
310
    0x80: lock_m_state L2 demand lock RFOs in M state
310
    0x80: (name=lock_m_state) L2 demand lock RFOs in M state
311
 <br />
311
 <br />
312
    0xe0: lock_hit All demand L2 lock RFOs that hit the cache
312
    0xe0: (name=lock_hit) All demand L2 lock RFOs that hit the cache
313
 <br />
313
 <br />
314
    0xf0: lock_mesi All demand L2 lock RFOs
314
    0xf0: (name=lock_mesi) All demand L2 lock RFOs
315
 <br />
315
 <br />
316
</td>
317
318
</tr>
316
</td>
319
317
318
</tr>
319
320
<tr><td>L1D_WB_L2</td><td>  L1 writebacks to L2 in E state </td><td> 0, 1, 2, 3</td><td>
320
<tr><td>L1D_WB_L2</td><td>  L1 writebacks to L2 in E state </td><td> all</td><td>
321
    0x01: i_state L1 writebacks to L2 in I state (misses)
321
    0x01: (name=i_state) L1 writebacks to L2 in I state (misses)
322
 <br />
322
 <br />
323
    0x02: s_state L1 writebacks to L2 in S state
323
    0x02: (name=s_state) L1 writebacks to L2 in S state
324
 <br />
324
 <br />
325
    0x04: e_state L1 writebacks to L2 in E state
325
    0x04: (name=e_state) L1 writebacks to L2 in E state
326
 <br />
326
 <br />
327
    0x08: m_state L1 writebacks to L2 in M state
327
    0x08: (name=m_state) L1 writebacks to L2 in M state
328
 <br />
328
 <br />
329
    0x0f: mesi All L1 writebacks to L2
329
    0x0f: (name=mesi) All L1 writebacks to L2
330
 <br />
330
 <br />
331
</td>
332
333
</tr>
331
</td>
334
332
333
</tr>
334
335
<tr><td>LONGEST_LAT_CACHE</td><td>  Longest latency cache miss </td><td> 0, 1, 2, 3</td><td>
335
<tr><td>LONGEST_LAT_CACHE</td><td>  Longest latency cache miss </td><td> all</td><td>
336
    0x01: miss Longest latency cache miss
336
    0x01: (name=miss) Longest latency cache miss
337
 <br />
337
 <br />
338
    0x02: reference Longest latency cache reference
338
    0x02: (name=reference) Longest latency cache reference
339
 <br />
339
 <br />
340
</td>
341
342
</tr>
340
</td>
343
341
342
</tr>
343
344
<tr><td>CPU_CLK_UNHALTED</td><td>   Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter) </td><td> 0, 1, 2, 3</td><td>
344
<tr><td>CPU_CLK_UNHALTED</td><td>   Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter) </td><td> all</td><td>
345
    0x00: thread_p Cycles when thread is not halted (programmable counter)
345
    0x00: (name=thread_p) Cycles when thread is not halted (programmable counter)
346
 <br />
346
 <br />
347
    0x01: ref_p Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)
347
    0x01: (name=ref_p) Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)
348
 <br />
348
 <br />
349
</td>
350
351
</tr>
349
</td>
352
350
351
</tr>
352
353
<tr><td>DTLB_MISSES</td><td>    DTLB misses </td><td> 0, 1, 2, 3</td><td>
353
<tr><td>DTLB_MISSES</td><td>    DTLB misses </td><td> all</td><td>
354
    0x01: any DTLB misses
354
    0x01: (name=any) DTLB misses
355
 <br />
355
 <br />
356
    0x02: walk_completed DTLB miss page walks
356
    0x02: (name=walk_completed) DTLB miss page walks
357
 <br />
357
 <br />
358
    0x04: walk_cycles DTLB miss page walk cycles
358
    0x04: (name=walk_cycles) DTLB miss page walk cycles
359
 <br />
359
 <br />
360
    0x10: stlb_hit DTLB first level misses but second level hit
360
    0x10: (name=stlb_hit) DTLB first level misses but second level hit
361
 <br />
361
 <br />
362
    0x20: pde_miss DTLB misses casued by low part of address
362
    0x20: (name=pde_miss) DTLB misses casued by low part of address
363
 <br />
363
 <br />
364
    0x80: large_walk_completed DTLB miss large page walks
364
    0x80: (name=large_walk_completed) DTLB miss large page walks
365
 <br />
365
 <br />
366
</td>
367
368
</tr>
366
</td>
369
367
368
</tr>
369
370
<tr><td>LOAD_HIT_PRE</td><td>   Load operations conflicting with software prefetches </td><td> all</td><td>
370
<tr><td>LOAD_HIT_PRE</td><td>   Load operations conflicting with software prefetches </td><td> 0, 1</td><td>
371
    0x01: No unit mask
371
    0x01: No unit mask
372
 <br />
372
 <br />
373
</td>
374
375
</tr>
373
</td>
376
374
375
</tr>
376
377
<tr><td>L1D_PREFETCH</td><td>   L1D hardware prefetch misses </td><td> all</td><td>
377
<tr><td>L1D_PREFETCH</td><td>   L1D hardware prefetch misses </td><td> 0, 1</td><td>
378
    0x01: requests L1D hardware prefetch requests
378
    0x01: (name=requests) L1D hardware prefetch requests
379
 <br />
379
 <br />
380
    0x02: miss L1D hardware prefetch misses
380
    0x02: (name=miss) L1D hardware prefetch misses
381
 <br />
381
 <br />
382
    0x04: triggers L1D hardware prefetch requests triggered
382
    0x04: (name=triggers) L1D hardware prefetch requests triggered
383
 <br />
383
 <br />
384
</td>
385
386
</tr>
384
</td>
387
385
386
</tr>
387
388
<tr><td>EPT</td><td>    Extended Page Table walk cycles </td><td> 0, 1, 2, 3</td><td>
388
<tr><td>EPT</td><td>    Extended Page Table walk cycles </td><td> all</td><td>
389
    0x10: No unit mask
389
    0x10: No unit mask
390
 <br />
390
 <br />
391
</td>
391
</td>
392
392
393
</tr>
393
</tr>
394
394
395
<tr><td>L1D</td><td>    L1D cache lines replaced in M state </td><td> all</td><td>
395
<tr><td>L1D</td><td>    L1D cache lines replaced in M state  </td><td> 0, 1</td><td>
396
    0x01: repl L1 data cache lines allocated
396
    0x01: (name=repl) L1 data cache lines allocated
397
 <br />
397
 <br />
398
    0x02: m_repl L1D cache lines allocated in the M state
398
    0x02: (name=m_repl) L1D cache lines allocated in the M state
399
 <br />
399
 <br />
400
    0x04: m_evict L1D cache lines replaced in M state
400
    0x04: (name=m_evict) L1D cache lines replaced in M state
401
 <br />
401
 <br />
402
    0x08: m_snoop_evict L1D snoop eviction of cache lines in M state
402
    0x08: (name=m_snoop_evict) L1D snoop eviction of cache lines in M state
403
 <br />
403
 <br />
404
</td>
405
406
</tr>
404
</td>
407
405
406
</tr>
407
408
<tr><td>L1D_CACHE_PREFETCH_LOCK_FB_HIT</td><td> L1D prefetch load lock accepted in fill buffer </td><td> all</td><td>
408
<tr><td>L1D_CACHE_PREFETCH_LOCK_FB_HIT</td><td> L1D prefetch load lock accepted in fill buffer </td><td> 0, 1</td><td>
409
    0x01: No unit mask
409
    0x01: No unit mask
410
 <br />
410
 <br />
411
</td>
411
</td>
412
412
413
</tr>
413
</tr>
414
414
415
<tr><td>OFFCORE_REQUESTS_OUTSTANDING</td><td>   Outstanding offcore reads </td><td> 0</td><td>
415
<tr><td>OFFCORE_REQUESTS_OUTSTANDING</td><td>   Outstanding offcore reads </td><td> 0</td><td>
416
    0x01: demand_read_data Outstanding offcore demand data reads
416
    0x01: (name=demand_read_data) Outstanding offcore demand data reads
417
 <br />
417
 <br />
418
    0x02: demand_read_code Outstanding offcore demand code reads
418
    0x02: (name=demand_read_code) Outstanding offcore demand code reads
419
 <br />
419
 <br />
420
    0x04: demand_rfo Outstanding offcore demand RFOs
420
    0x04: (name=demand_rfo) Outstanding offcore demand RFOs
421
 <br />
421
 <br />
422
    0x08: any_read Outstanding offcore reads
422
    0x08: (name=any_read) Outstanding offcore reads
423
 <br />
423
 <br />
424
</td>
425
426
</tr>
424
</td>
427
425
426
</tr>
427
428
<tr><td>CACHE_LOCK_CYCLES</td><td>  Cycles L1D locked </td><td> all</td><td>
428
<tr><td>CACHE_LOCK_CYCLES</td><td>  Cycles L1D locked </td><td> 0, 1</td><td>
429
    0x01: l1d_l2 Cycles L1D and L2 locked
429
    0x01: (name=l1d_l2) Cycles L1D and L2 locked
430
 <br />
430
 <br />
431
    0x02: l1d Cycles L1D locked
431
    0x02: (name=l1d) Cycles L1D locked
432
 <br />
432
 <br />
433
</td>
434
435
</tr>
433
</td>
436
434
435
</tr>
436
437
<tr><td>IO_TRANSACTIONS</td><td>    I/O transactions </td><td> 0, 1, 2, 3</td><td>
437
<tr><td>IO_TRANSACTIONS</td><td>    I/O transactions </td><td> all</td><td>
438
    0x01: No unit mask
438
    0x01: No unit mask
439
 <br />
439
 <br />
440
</td>
441
442
</tr>
440
</td>
443
441
442
</tr>
443
444
<tr><td>L1I</td><td>    L1I instruction fetch stall cycles </td><td> 0, 1, 2, 3</td><td>
444
<tr><td>L1I</td><td>    L1I instruction fetch stall cycles </td><td> all</td><td>
445
    0x01: hits L1I instruction fetch hits
445
    0x01: (name=hits) L1I instruction fetch hits
446
 <br />
446
 <br />
447
    0x02: misses L1I instruction fetch misses
447
    0x02: (name=misses) L1I instruction fetch misses
448
 <br />
448
 <br />
449
    0x03: reads L1I Instruction fetches
449
    0x03: (name=reads) L1I Instruction fetches
450
 <br />
450
 <br />
451
    0x04: cycles_stalled L1I instruction fetch stall cycles
451
    0x04: (name=cycles_stalled) L1I instruction fetch stall cycles
452
 <br />
452
 <br />
453
</td>
454
455
</tr>
453
</td>
456
454
455
</tr>
456
457
<tr><td>LARGE_ITLB</td><td> Large ITLB hit </td><td> 0, 1, 2, 3</td><td>
457
<tr><td>LARGE_ITLB</td><td> Large ITLB hit </td><td> all</td><td>
458
    0x01: No unit mask
458
    0x01: No unit mask
459
 <br />
459
 <br />
460
</td>
461
462
</tr>
460
</td>
463
461
462
</tr>
463
464
<tr><td>ITLB_MISSES</td><td>    ITLB miss </td><td> 0, 1, 2, 3</td><td>
464
<tr><td>ITLB_MISSES</td><td>    ITLB miss </td><td> all</td><td>
465
    0x01: any ITLB miss
465
    0x01: (name=any) ITLB miss
466
 <br />
466
 <br />
467
    0x02: walk_completed ITLB miss page walks
467
    0x02: (name=walk_completed) ITLB miss page walks
468
 <br />
468
 <br />
469
    0x04: walk_cycles ITLB miss page walk cycles
469
    0x04: (name=walk_cycles) ITLB miss page walk cycles
470
 <br />
470
 <br />
471
    0x80: large_walk_completed ITLB miss large page walks
471
    0x80: (name=large_walk_completed) ITLB miss large page walks
472
 <br />
472
 <br />
473
</td>
474
475
</tr>
473
</td>
476
474
475
</tr>
476
477
<tr><td>ILD_STALL</td><td>  Any Instruction Length Decoder stall cycles </td><td> 0, 1, 2, 3</td><td>
477
<tr><td>ILD_STALL</td><td>  Any Instruction Length Decoder stall cycles </td><td> all</td><td>
478
    0x01: lcp Length Change Prefix stall cycles
478
    0x01: (name=lcp) Length Change Prefix stall cycles
479
 <br />
479
 <br />
480
    0x02: mru Stall cycles due to BPU MRU bypass
480
    0x02: (name=mru) Stall cycles due to BPU MRU bypass
481
 <br />
481
 <br />
482
    0x04: iq_full Instruction Queue full stall cycles
482
    0x04: (name=iq_full) Instruction Queue full stall cycles
483
 <br />
483
 <br />
484
    0x08: regen Regen stall cycles
484
    0x08: (name=regen) Regen stall cycles
485
 <br />
485
 <br />
486
    0x0f: any Any Instruction Length Decoder stall cycles
486
    0x0f: (name=any) Any Instruction Length Decoder stall cycles
487
 <br />
487
 <br />
488
</td>
489
490
</tr>
488
</td>
491
489
490
</tr>
491
492
<tr><td>BR_INST_EXEC</td><td>   Branch instructions executed </td><td> 0, 1, 2, 3</td><td>
492
<tr><td>BR_INST_EXEC</td><td>   Branch instructions executed </td><td> all</td><td>
493
    0x01: cond Conditional branch instructions executed
493
    0x01: (name=cond) Conditional branch instructions executed
494
 <br />
494
 <br />
495
    0x02: direct Unconditional branches executed
495
    0x02: (name=direct) Unconditional branches executed
496
 <br />
496
 <br />
497
    0x04: indirect_non_call Indirect non call branches executed
497
    0x04: (name=indirect_non_call) Indirect non call branches executed
498
 <br />
498
 <br />
499
    0x07: non_calls All non call branches executed
499
    0x07: (name=non_calls) All non call branches executed
500
 <br />
500
 <br />
501
    0x08: return_near Indirect return branches executed
501
    0x08: (name=return_near) Indirect return branches executed
502
 <br />
502
 <br />
503
    0x10: direct_near_call Unconditional call branches executed
503
    0x10: (name=direct_near_call) Unconditional call branches executed
504
 <br />
504
 <br />
505
    0x20: indirect_near_call Indirect call branches executed
505
    0x20: (name=indirect_near_call) Indirect call branches executed
506
 <br />
506
 <br />
507
    0x30: near_calls Call branches executed
507
    0x30: (name=near_calls) Call branches executed
508
 <br />
508
 <br />
509
    0x40: taken Taken branches executed
509
    0x40: (name=taken) Taken branches executed
510
 <br />
510
 <br />
511
    0x7f: any Branch instructions executed
511
    0x7f: (name=any) Branch instructions executed
512
 <br />
512
 <br />
513
</td>
514
515
</tr>
513
</td>
516
514
515
</tr>
516
517
<tr><td>BR_MISP_EXEC</td><td>   Mispredicted branches executed </td><td> 0, 1, 2, 3</td><td>
517
<tr><td>BR_MISP_EXEC</td><td>   Mispredicted branches executed </td><td> all</td><td>
518
    0x01: cond Mispredicted conditional branches executed
518
    0x01: (name=cond) Mispredicted conditional branches executed
519
 <br />
519
 <br />
520
    0x02: direct Mispredicted unconditional branches executed
520
    0x02: (name=direct) Mispredicted unconditional branches executed
521
 <br />
521
 <br />
522
    0x04: indirect_non_call Mispredicted indirect non call branches executed
522
    0x04: (name=indirect_non_call) Mispredicted indirect non call branches executed
523
 <br />
523
 <br />
524
    0x07: non_calls Mispredicted non call branches executed
524
    0x07: (name=non_calls) Mispredicted non call branches executed
525
 <br />
525
 <br />
526
    0x08: return_near Mispredicted return branches executed
526
    0x08: (name=return_near) Mispredicted return branches executed
527
 <br />
527
 <br />
528
    0x10: direct_near_call Mispredicted non call branches executed
528
    0x10: (name=direct_near_call) Mispredicted non call branches executed
529
 <br />
529
 <br />
530
    0x20: indirect_near_call Mispredicted indirect call branches executed
530
    0x20: (name=indirect_near_call) Mispredicted indirect call branches executed
531
 <br />
531
 <br />
532
    0x30: near_calls Mispredicted call branches executed
532
    0x30: (name=near_calls) Mispredicted call branches executed
533
 <br />
533
 <br />
534
    0x40: taken Mispredicted taken branches executed
534
    0x40: (name=taken) Mispredicted taken branches executed
535
 <br />
535
 <br />
536
    0x7f: any Mispredicted branches executed
536
    0x7f: (name=any) Mispredicted branches executed
537
 <br />
537
 <br />
538
</td>
539
540
</tr>
538
</td>
541
539
540
</tr>
541
542
<tr><td>RESOURCE_STALLS</td><td>    Resource related stall cycles </td><td> 0, 1, 2, 3</td><td>
542
<tr><td>RESOURCE_STALLS</td><td>    Resource related stall cycles </td><td> all</td><td>
543
    0x01: any Resource related stall cycles
543
    0x01: (name=any) Resource related stall cycles
544
 <br />
544
 <br />
545
    0x02: load Load buffer stall cycles
545
    0x02: (name=load) Load buffer stall cycles
546
 <br />
546
 <br />
547
    0x04: rs_full Reservation Station full stall cycles
547
    0x04: (name=rs_full) Reservation Station full stall cycles
548
 <br />
548
 <br />
549
    0x08: store Store buffer stall cycles
549
    0x08: (name=store) Store buffer stall cycles
550
 <br />
550
 <br />
551
    0x10: rob_full ROB full stall cycles
551
    0x10: (name=rob_full) ROB full stall cycles
552
 <br />
552
 <br />
553
    0x20: fpcw FPU control word write stall cycles
553
    0x20: (name=fpcw) FPU control word write stall cycles
554
 <br />
554
 <br />
555
    0x40: mxcsr MXCSR rename stall cycles
555
    0x40: (name=mxcsr) MXCSR rename stall cycles
556
 <br />
556
 <br />
557
    0x80: other Other Resource related stall cycles
557
    0x80: (name=other) Other Resource related stall cycles
558
 <br />
558
 <br />
559
</td>
560
561
</tr>
559
</td>
562
560
561
</tr>
562
563
<tr><td>MACRO_INSTS</td><td>    Macro-fused instructions decoded </td><td> 0, 1, 2, 3</td><td>
563
<tr><td>MACRO_INSTS</td><td>    Macro-fused instructions decoded </td><td> all</td><td>
564
    0x01: No unit mask
564
    0x01: No unit mask
565
 <br />
565
 <br />
566
</td>
567
568
</tr>
566
</td>
569
567
568
</tr>
569
570
<tr><td>BACLEAR_FORCE_IQ</td><td>   Instruction queue forced BACLEAR </td><td> 0, 1, 2, 3</td><td>
570
<tr><td>BACLEAR_FORCE_IQ</td><td>   Instruction queue forced BACLEAR </td><td> all</td><td>
571
    0x01: No unit mask
571
    0x01: No unit mask
572
 <br />
572
 <br />
573
</td>
574
575
</tr>
573
</td>
576
574
575
</tr>
576
577
<tr><td>LSD</td><td>    Cycles when uops were delivered by the LSD </td><td> 0, 1, 2, 3</td><td>
577
<tr><td>LSD</td><td>    Cycles when uops were delivered by the LSD </td><td> all</td><td>
578
    0x01: No unit mask
578
    0x01: No unit mask
579
 <br />
579
 <br />
580
</td>
581
582
</tr>
580
</td>
583
581
582
</tr>
583
584
<tr><td>ITLB_FLUSH</td><td> ITLB flushes </td><td> 0, 1, 2, 3</td><td>
584
<tr><td>ITLB_FLUSH</td><td> ITLB flushes </td><td> all</td><td>
585
    0x01: No unit mask
585
    0x01: No unit mask
586
 <br />
586
 <br />
587
</td>
588
589
</tr>
587
</td>
590
588
589
</tr>
590
591
<tr><td>OFFCORE_REQUESTS</td><td>   All offcore requests </td><td> 0, 1, 2, 3</td><td>
591
<tr><td>OFFCORE_REQUESTS</td><td>   All offcore requests </td><td> all</td><td>
592
    0x01: demand_read_data Offcore demand data read requests
592
    0x01: (name=demand_read_data) Offcore demand data read requests
593
 <br />
593
 <br />
594
    0x02: demand_read_code Offcore demand code read requests
594
    0x02: (name=demand_read_code) Offcore demand code read requests
595
 <br />
595
 <br />
596
    0x04: demand_rfo Offcore demand RFO requests
596
    0x04: (name=demand_rfo) Offcore demand RFO requests
597
 <br />
597
 <br />
598
    0x08: any_read Offcore read requests
598
    0x08: (name=any_read) Offcore read requests
599
 <br />
599
 <br />
600
    0x10: any_rfo Offcore RFO requests
600
    0x10: (name=any_rfo) Offcore RFO requests
601
 <br />
601
 <br />
602
    0x40: l1d_writeback Offcore L1 data cache writebacks
602
    0x40: (name=l1d_writeback) Offcore L1 data cache writebacks
603
 <br />
603
 <br />
604
    0x80: any All offcore requests
604
    0x80: (name=any) All offcore requests
605
 <br />
605
 <br />
606
</td>
607
608
</tr>
606
</td>
609
607
608
</tr>
609
610
<tr><td>UOPS_EXECUTED</td><td>  Cycles Uops executed on any port (core count) </td><td> 0, 1, 2, 3</td><td>
610
<tr><td>UOPS_EXECUTED</td><td>  Cycles Uops executed on any port (core count) </td><td> all</td><td>
611
    0x01: port0 Uops executed on port 0
611
    0x01: (name=port0) Uops executed on port 0
612
 <br />
612
 <br />
613
    0x02: port1 Uops executed on port 1
613
    0x02: (name=port1) Uops executed on port 1
614
 <br />
614
 <br />
615
    0x04: port2_core Uops executed on port 2 (core count)
615
    0x04: (name=port2_core) Uops executed on port 2 (core count)
616
 <br />
616
 <br />
617
    0x08: port3_core Uops executed on port 3 (core count)
617
    0x08: (name=port3_core) Uops executed on port 3 (core count)
618
 <br />
618
 <br />
619
    0x10: port4_core Uops executed on port 4 (core count)
619
    0x10: (name=port4_core) Uops executed on port 4 (core count)
620
 <br />
620
 <br />
621
    0x1f: core_active_cycles_no_port5 Cycles Uops executed on ports 0-4 (core count)
621
    0x1f: (name=core_active_cycles_no_port5) Cycles Uops executed on ports 0-4 (core count)
622
 <br />
622
 <br />
623
    0x20: port5 Uops executed on port 5
623
    0x20: (name=port5) Uops executed on port 5
624
 <br />
624
 <br />
625
    0x3f: core_active_cycles Cycles Uops executed on any port (core count)
625
    0x3f: (name=core_active_cycles) Cycles Uops executed on any port (core count)
626
 <br />
626
 <br />
627
    0x40: port015 Uops issued on ports 0, 1 or 5
627
    0x40: (name=port015) Uops issued on ports 0, 1 or 5
628
 <br />
628
 <br />
629
    0x80: port234_core Uops issued on ports 2, 3 or 4
629
    0x80: (name=port234_core) Uops issued on ports 2, 3 or 4
630
 <br />
630
 <br />
631
</td>
632
633
</tr>
631
</td>
634
632
633
</tr>
634
635
<tr><td>OFFCORE_REQUESTS_SQ_FULL</td><td>   Offcore requests blocked due to Super Queue full </td><td> 0, 1, 2, 3</td><td>
635
<tr><td>OFFCORE_REQUESTS_SQ_FULL</td><td>   Offcore requests blocked due to Super Queue full </td><td> all</td><td>
636
    0x01: No unit mask
636
    0x01: No unit mask
637
 <br />
637
 <br />
638
</td>
638
</td>
639
639
640
</tr>
640
</tr>
641
641
642
<tr><td>SNOOPQ_REQUESTS_OUTSTANDING</td><td>    Outstanding snoop code requests </td><td> 0</td><td>
642
<tr><td>SNOOPQ_REQUESTS_OUTSTANDING</td><td>    Outstanding snoop code requests </td><td> 0</td><td>
643
    0x01: data Outstanding snoop data requests
643
    0x01: (name=data) Outstanding snoop data requests
644
 <br />
644
 <br />
645
    0x02: invalidate Outstanding snoop invalidate requests
645
    0x02: (name=invalidate) Outstanding snoop invalidate requests
646
 <br />
646
 <br />
647
    0x04: code Outstanding snoop code requests
647
    0x04: (name=code) Outstanding snoop code requests
648
 <br />
648
 <br />
649
</td>
650
651
</tr>
649
</td>
652
650
651
</tr>
652
653
<tr><td>SNOOPQ_REQUESTS</td><td>    Snoop code requests </td><td> 0, 1, 2, 3</td><td>
653
<tr><td>SNOOPQ_REQUESTS</td><td>    Snoop code requests </td><td> all</td><td>
654
    0x01: data Snoop data requests
654
    0x01: (name=data) Snoop data requests
655
 <br />
655
 <br />
656
    0x02: invalidate Snoop invalidate requests
656
    0x02: (name=invalidate) Snoop invalidate requests
657
 <br />
657
 <br />
658
    0x04: code Snoop code requests
658
    0x04: (name=code) Snoop code requests
659
 <br />
659
 <br />
660
</td>
660
</td>
661
661
662
</tr>
662
</tr>
663
663
...
...
666
 <br />
666
 <br />
667
</td>
667
</td>
668
668
669
</tr>
669
</tr>
670
670
671
<tr><td>SNOOP_RESPONSE</td><td> Thread responded HIT to snoop </td><td> 0, 1, 2, 3</td><td>
671
<tr><td>SNOOP_RESPONSE</td><td> Thread responded HIT to snoop </td><td> all</td><td>
672
    0x01: hit Thread responded HIT to snoop
672
    0x01: (name=hit) Thread responded HIT to snoop
673
 <br />
673
 <br />
674
    0x02: hite Thread responded HITE to snoop
674
    0x02: (name=hite) Thread responded HITE to snoop
675
 <br />
675
 <br />
676
    0x04: hitm Thread responded HITM to snoop
676
    0x04: (name=hitm) Thread responded HITM to snoop
677
 <br />
677
 <br />
678
</td>
678
</td>
679
679
680
</tr>
680
</tr>
681
681
...
...
684
 <br />
684
 <br />
685
</td>
685
</td>
686
686
687
</tr>
687
</tr>
688
688
689
<tr><td>INST_RETIRED</td><td>   Instructions retired (Programmable counter and Precise Event) </td><td> 0, 1, 2, 3</td><td>
689
<tr><td>INST_RETIRED</td><td>   Instructions retired (Programmable counter and Precise Event) </td><td> all</td><td>
690
    0x01: any_p Instructions retired (Programmable counter and Precise Event)
690
    0x01: (name=any_p) Instructions retired (Programmable counter and Precise Event)
691
 <br />
691
 <br />
692
    0x02: x87 Retired floating-point operations (Precise Event)
692
    0x02: (name=x87) Retired floating-point operations (Precise Event)
693
 <br />
693
 <br />
694
    0x04: mmx Retired MMX instructions (Precise Event)
694
    0x04: (name=mmx) Retired MMX instructions (Precise Event)
695
 <br />
695
 <br />
696
</td>
697
698
</tr>
696
</td>
699
697
698
</tr>
699
700
<tr><td>UOPS_RETIRED</td><td>   Cycles Uops are being retired </td><td> 0, 1, 2, 3</td><td>
700
<tr><td>UOPS_RETIRED</td><td>   Cycles Uops are being retired </td><td> all</td><td>
701
    0x01: active_cycles Cycles Uops are being retired
701
    0x01: (name=active_cycles) Cycles Uops are being retired
702
 <br />
702
 <br />
703
    0x02: retire_slots Retirement slots used (Precise Event)
703
    0x02: (name=retire_slots) Retirement slots used (Precise Event)
704
 <br />
704
 <br />
705
    0x04: macro_fused Macro-fused Uops retired (Precise Event)
705
    0x04: (name=macro_fused) Macro-fused Uops retired (Precise Event)
706
 <br />
706
 <br />
707
</td>
708
709
</tr>
707
</td>
710
708
709
</tr>
710
711
<tr><td>MACHINE_CLEARS</td><td> Cycles machine clear asserted </td><td> 0, 1, 2, 3</td><td>
711
<tr><td>MACHINE_CLEARS</td><td> Cycles machine clear asserted </td><td> all</td><td>
712
    0x01: cycles Cycles machine clear asserted
712
    0x01: (name=cycles) Cycles machine clear asserted
713
 <br />
713
 <br />
714
    0x02: mem_order Execution pipeline restart due to Memory ordering conflicts
714
    0x02: (name=mem_order) Execution pipeline restart due to Memory ordering conflicts
715
 <br />
715
 <br />
716
    0x04: smc Self-Modifying Code detected
716
    0x04: (name=smc) Self-Modifying Code detected
717
 <br />
717
 <br />
718
</td>
719
720
</tr>
718
</td>
721
719
720
</tr>
721
722
<tr><td>BR_INST_RETIRED</td><td>    Retired branch instructions (Precise Event) </td><td> 0, 1, 2, 3</td><td>
722
<tr><td>BR_INST_RETIRED</td><td>    Retired branch instructions (Precise Event) </td><td> all</td><td>
723
    0x01: conditional Retired conditional branch instructions (Precise Event)
723
    0x01: (name=conditional) Retired conditional branch instructions (Precise Event)
724
 <br />
724
 <br />
725
    0x02: near_call Retired near call instructions (Precise Event)
725
    0x02: (name=near_call) Retired near call instructions (Precise Event)
726
 <br />
726
 <br />
727
    0x04: all_branches Retired branch instructions (Precise Event)
727
    0x04: (name=all_branches) Retired branch instructions (Precise Event)
728
 <br />
728
 <br />
729
</td>
730
731
</tr>
729
</td>
732
730
731
</tr>
732
733
<tr><td>BR_MISP_RETIRED</td><td>    Mispredicted retired branch instructions (Precise Event) </td><td> 0, 1, 2, 3</td><td>
733
<tr><td>BR_MISP_RETIRED</td><td>    Mispredicted retired branch instructions (Precise Event) </td><td> all</td><td>
734
    0x01: conditional Mispredicted conditional retired branches (Precise Event)
734
    0x01: (name=conditional) Mispredicted conditional retired branches (Precise Event)
735
 <br />
735
 <br />
736
    0x02: near_call Mispredicted near retired calls (Precise Event)
736
    0x02: (name=near_call) Mispredicted near retired calls (Precise Event)
737
 <br />
737
 <br />
738
    0x04: all_branches Mispredicted retired branch instructions (Precise Event)
738
    0x04: (name=all_branches) Mispredicted retired branch instructions (Precise Event)
739
 <br />
739
 <br />
740
</td>
741
742
</tr>
740
</td>
743
741
742
</tr>
743
744
<tr><td>SSEX_UOPS_RETIRED</td><td>  SIMD Packed-Double Uops retired (Precise Event) </td><td> 0, 1, 2, 3</td><td>
744
<tr><td>SSEX_UOPS_RETIRED</td><td>  SIMD Packed-Double Uops retired (Precise Event) </td><td> all</td><td>
745
    0x01: packed_single SIMD Packed-Single Uops retired (Precise Event)
745
    0x01: (name=packed_single) SIMD Packed-Single Uops retired (Precise Event)
746
 <br />
746
 <br />
747
    0x02: scalar_single SIMD Scalar-Single Uops retired (Precise Event)
747
    0x02: (name=scalar_single) SIMD Scalar-Single Uops retired (Precise Event)
748
 <br />
748
 <br />
749
    0x04: packed_double SIMD Packed-Double Uops retired (Precise Event)
749
    0x04: (name=packed_double) SIMD Packed-Double Uops retired (Precise Event)
750
 <br />
750
 <br />
751
    0x08: scalar_double SIMD Scalar-Double Uops retired (Precise Event)
751
    0x08: (name=scalar_double) SIMD Scalar-Double Uops retired (Precise Event)
752
 <br />
752
 <br />
753
    0x10: vector_integer SIMD Vector Integer Uops retired (Precise Event)
753
    0x10: (name=vector_integer) SIMD Vector Integer Uops retired (Precise Event)
754
 <br />
754
 <br />
755
</td>
756
757
</tr>
755
</td>
758
756
757
</tr>
758
759
<tr><td>ITLB_MISS_RETIRED</td><td>  Retired instructions that missed the ITLB (Precise Event) </td><td> 0, 1, 2, 3</td><td>
759
<tr><td>ITLB_MISS_RETIRED</td><td>  Retired instructions that missed the ITLB (Precise Event) </td><td> all</td><td>
760
    0x20: No unit mask
760
    0x20: No unit mask
761
 <br />
761
 <br />
762
</td>
762
</td>
763
763
764
</tr>
764
</tr>
765
765
766
<tr><td>MEM_LOAD_RETIRED</td><td>   Retired loads that miss the DTLB (Precise Event) </td><td> 0, 1, 2, 3</td><td>
766
<tr><td>MEM_LOAD_RETIRED</td><td>   Retired loads that miss the DTLB (Precise Event) </td><td> all</td><td>
767
    0x01: l1d_hit Retired loads that hit the L1 data cache (Precise Event)
767
    0x01: (name=l1d_hit) Retired loads that hit the L1 data cache (Precise Event)
768
 <br />
768
 <br />
769
    0x02: l2_hit Retired loads that hit the L2 cache (Precise Event)
769
    0x02: (name=l2_hit) Retired loads that hit the L2 cache (Precise Event)
770
 <br />
770
 <br />
771
    0x04: llc_unshared_hit Retired loads that hit valid versions in the LLC cache (Precise Event)
771
    0x04: (name=llc_unshared_hit) Retired loads that hit valid versions in the LLC cache (Precise Event)
772
 <br />
772
 <br />
773
    0x08: other_core_l2_hit_hitm Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)
773
    0x08: (name=other_core_l2_hit_hitm) Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)
774
 <br />
774
 <br />
775
    0x10: llc_miss Retired loads that miss the LLC cache (Precise Event)
775
    0x10: (name=llc_miss) Retired loads that miss the LLC cache (Precise Event)
776
 <br />
776
 <br />
777
    0x40: hit_lfb Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)
777
    0x40: (name=hit_lfb) Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)
778
 <br />
778
 <br />
779
    0x80: dtlb_miss Retired loads that miss the DTLB (Precise Event)
779
    0x80: (name=dtlb_miss) Retired loads that miss the DTLB (Precise Event)
780
 <br />
780
 <br />
781
</td>
782
783
</tr>
781
</td>
784
782
783
</tr>
784
785
<tr><td>FP_MMX_TRANS</td><td>   All Floating Point to and from MMX transitions </td><td> 0, 1, 2, 3</td><td>
785
<tr><td>FP_MMX_TRANS</td><td>   All Floating Point to and from MMX transitions </td><td> all</td><td>
786
    0x01: to_fp Transitions from MMX to Floating Point instructions
786
    0x01: (name=to_fp) Transitions from MMX to Floating Point instructions
787
 <br />
787
 <br />
788
    0x02: to_mmx Transitions from Floating Point to MMX instructions
788
    0x02: (name=to_mmx) Transitions from Floating Point to MMX instructions
789
 <br />
789
 <br />
790
    0x03: any All Floating Point to and from MMX transitions
790
    0x03: (name=any) All Floating Point to and from MMX transitions
791
 <br />
791
 <br />
792
</td>
793
794
</tr>
792
</td>
795
793
794
</tr>
795
796
<tr><td>MACRO_INSTS</td><td>    Instructions decoded </td><td> 0, 1, 2, 3</td><td>
796
<tr><td>MACRO_INSTS</td><td>    Instructions decoded </td><td> all</td><td>
797
    0x01: No unit mask
797
    0x01: No unit mask
798
 <br />
798
 <br />
799
</td>
800
801
</tr>
799
</td>
802
800
801
</tr>
802
803
<tr><td>UOPS_DECODED</td><td>   Stack pointer instructions decoded </td><td> 0, 1, 2, 3</td><td>
803
<tr><td>UOPS_DECODED</td><td>   Stack pointer instructions decoded </td><td> all</td><td>
804
    0x01: stall_cycles Cycles no Uops are decoded
804
    0x01: (name=stall_cycles) Cycles no Uops are decoded
805
 <br />
805
 <br />
806
    0x02: ms_cycles_active Uops decoded by Microcode Sequencer
806
    0x02: (name=ms_cycles_active) Uops decoded by Microcode Sequencer
807
 <br />
807
 <br />
808
    0x04: esp_folding Stack pointer instructions decoded
808
    0x04: (name=esp_folding) Stack pointer instructions decoded
809
 <br />
809
 <br />
810
    0x08: esp_sync Stack pointer sync operations
810
    0x08: (name=esp_sync) Stack pointer sync operations
811
 <br />
811
 <br />
812
</td>
813
814
</tr>
812
</td>
815
813
814
</tr>
815
816
<tr><td>RAT_STALLS</td><td> All RAT stall cycles </td><td> 0, 1, 2, 3</td><td>
816
<tr><td>RAT_STALLS</td><td> All RAT stall cycles </td><td> all</td><td>
817
    0x01: flags Flag stall cycles
817
    0x01: (name=flags) Flag stall cycles
818
 <br />
818
 <br />
819
    0x02: registers Partial register stall cycles
819
    0x02: (name=registers) Partial register stall cycles
820
 <br />
820
 <br />
821
    0x04: rob_read_port ROB read port stalls cycles
821
    0x04: (name=rob_read_port) ROB read port stalls cycles
822
 <br />
822
 <br />
823
    0x08: scoreboard Scoreboard stall cycles
823
    0x08: (name=scoreboard) Scoreboard stall cycles
824
 <br />
824
 <br />
825
    0x0f: any All RAT stall cycles
825
    0x0f: (name=any) All RAT stall cycles
826
 <br />
826
 <br />
827
</td>
828
829
</tr>
827
</td>
830
828
829
</tr>
830
831
<tr><td>SEG_RENAME_STALLS</td><td>  Segment rename stall cycles </td><td> 0, 1, 2, 3</td><td>
831
<tr><td>SEG_RENAME_STALLS</td><td>  Segment rename stall cycles </td><td> all</td><td>
832
    0x01: No unit mask
832
    0x01: No unit mask
833
 <br />
833
 <br />
834
</td>
835
836
</tr>
834
</td>
837
835
836
</tr>
837
838
<tr><td>ES_REG_RENAMES</td><td> ES segment renames </td><td> 0, 1, 2, 3</td><td>
838
<tr><td>ES_REG_RENAMES</td><td> ES segment renames </td><td> all</td><td>
839
    0x01: No unit mask
839
    0x01: No unit mask
840
 <br />
840
 <br />
841
</td>
842
843
</tr>
841
</td>
844
842
843
</tr>
844
845
<tr><td>UOP_UNFUSION</td><td>   Uop unfusions due to FP exceptions </td><td> 0, 1, 2, 3</td><td>
845
<tr><td>UOP_UNFUSION</td><td>   Uop unfusions due to FP exceptions </td><td> all</td><td>
846
    0x01: No unit mask
846
    0x01: No unit mask
847
 <br />
847
 <br />
848
</td>
849
850
</tr>
848
</td>
851
849
850
</tr>
851
852
<tr><td>BR_INST_DECODED</td><td>    Branch instructions decoded </td><td> 0, 1, 2, 3</td><td>
852
<tr><td>BR_INST_DECODED</td><td>    Branch instructions decoded </td><td> all</td><td>
853
    0x01: No unit mask
853
    0x01: No unit mask
854
 <br />
854
 <br />
855
</td>
856
857
</tr>
855
</td>
858
856
857
</tr>
858
859
<tr><td>BPU_MISSED_CALL_RET</td><td>    Branch prediction unit missed call or return </td><td> 0, 1, 2, 3</td><td>
859
<tr><td>BPU_MISSED_CALL_RET</td><td>    Branch prediction unit missed call or return </td><td> all</td><td>
860
    0x01: No unit mask
860
    0x01: No unit mask
861
 <br />
861
 <br />
862
</td>
863
864
</tr>
862
</td>
865
863
864
</tr>
865
866
<tr><td>BACLEAR</td><td>    BACLEAR asserted with bad target address </td><td> 0, 1, 2, 3</td><td>
866
<tr><td>BACLEAR</td><td>    BACLEAR asserted with bad target address </td><td> all</td><td>
867
    0x01: clear BACLEAR asserted, regardless of cause
867
    0x01: (name=clear) BACLEAR asserted, regardless of cause
868
 <br />
868
 <br />
869
    0x02: bad_target BACLEAR asserted with bad target address
869
    0x02: (name=bad_target) BACLEAR asserted with bad target address
870
 <br />
870
 <br />
871
</td>
872
873
</tr>
871
</td>
874
872
873
</tr>
874
875
<tr><td>BPU_CLEARS</td><td> Early Branch Prediction Unit clears </td><td> 0, 1, 2, 3</td><td>
875
<tr><td>BPU_CLEARS</td><td> Early Branch Prediction Unit clears </td><td> all</td><td>
876
    0x01: early Early Branch Prediction Unit clears
876
    0x01: (name=early) Early Branch Prediction Unit clears
877
 <br />
877
 <br />
878
    0x02: late Late Branch Prediction Unit clears
878
    0x02: (name=late) Late Branch Prediction Unit clears
879
 <br />
879
 <br />
880
</td>
881
882
</tr>
880
</td>
883
881
882
</tr>
883
884
<tr><td>L2_TRANSACTIONS</td><td>    All L2 transactions </td><td> 0, 1, 2, 3</td><td>
884
<tr><td>L2_TRANSACTIONS</td><td>    All L2 transactions </td><td> all</td><td>
885
    0x01: load L2 Load transactions
885
    0x01: (name=load) L2 Load transactions
886
 <br />
886
 <br />
887
    0x02: rfo L2 RFO transactions
887
    0x02: (name=rfo) L2 RFO transactions
888
 <br />
888
 <br />
889
    0x04: ifetch L2 instruction fetch transactions
889
    0x04: (name=ifetch) L2 instruction fetch transactions
890
 <br />
890
 <br />
891
    0x08: prefetch L2 prefetch transactions
891
    0x08: (name=prefetch) L2 prefetch transactions
892
 <br />
892
 <br />
893
    0x10: l1d_wb L1D writeback to L2 transactions
893
    0x10: (name=l1d_wb) L1D writeback to L2 transactions
894
 <br />
894
 <br />
895
    0x20: fill L2 fill transactions
895
    0x20: (name=fill) L2 fill transactions
896
 <br />
896
 <br />
897
    0x40: wb L2 writeback to LLC transactions
897
    0x40: (name=wb) L2 writeback to LLC transactions
898
 <br />
898
 <br />
899
    0x80: any All L2 transactions
899
    0x80: (name=any) All L2 transactions
900
 <br />
900
 <br />
901
</td>
902
903
</tr>
901
</td>
904
902
903
</tr>
904
905
<tr><td>L2_LINES_IN</td><td>    L2 lines alloacated </td><td> 0, 1, 2, 3</td><td>
905
<tr><td>L2_LINES_IN</td><td>    L2 lines alloacated </td><td> all</td><td>
906
    0x02: s_state L2 lines allocated in the S state
906
    0x02: (name=s_state) L2 lines allocated in the S state
907
 <br />
907
 <br />
908
    0x04: e_state L2 lines allocated in the E state
908
    0x04: (name=e_state) L2 lines allocated in the E state
909
 <br />
909
 <br />
910
    0x07: any L2 lines alloacated
910
    0x07: (name=any) L2 lines alloacated
911
 <br />
911
 <br />
912
</td>
913
914
</tr>
912
</td>
915
913
914
</tr>
915
916
<tr><td>L2_LINES_OUT</td><td>   L2 lines evicted </td><td> 0, 1, 2, 3</td><td>
916
<tr><td>L2_LINES_OUT</td><td>   L2 lines evicted </td><td> all</td><td>
917
    0x01: demand_clean L2 lines evicted by a demand request
917
    0x01: (name=demand_clean) L2 lines evicted by a demand request
918
 <br />
918
 <br />
919
    0x02: demand_dirty L2 modified lines evicted by a demand request
919
    0x02: (name=demand_dirty) L2 modified lines evicted by a demand request
920
 <br />
920
 <br />
921
    0x04: prefetch_clean L2 lines evicted by a prefetch request
921
    0x04: (name=prefetch_clean) L2 lines evicted by a prefetch request
922
 <br />
922
 <br />
923
    0x08: prefetch_dirty L2 modified lines evicted by a prefetch request
923
    0x08: (name=prefetch_dirty) L2 modified lines evicted by a prefetch request
924
 <br />
924
 <br />
925
    0x0f: any L2 lines evicted
925
    0x0f: (name=any) L2 lines evicted
926
 <br />
926
 <br />
927
</td>
928
929
</tr>
927
</td>
930
928
929
</tr>
930
931
<tr><td>SQ_MISC</td><td>    Super Queue LRU hints sent to LLC </td><td> 0, 1, 2, 3</td><td>
931
<tr><td>SQ_MISC</td><td>    Super Queue LRU hints sent to LLC </td><td> all</td><td>
932
    0x04: lru_hints Super Queue LRU hints sent to LLC
932
    0x04: (name=lru_hints) Super Queue LRU hints sent to LLC
933
 <br />
933
 <br />
934
    0x10: split_lock Super Queue lock splits across a cache line
934
    0x10: (name=split_lock) Super Queue lock splits across a cache line
935
 <br />
935
 <br />
936
</td>
937
938
</tr>
936
</td>
939
937
938
</tr>
939
940
<tr><td>SQ_FULL_STALL_CYCLES</td><td>   Super Queue full stall cycles </td><td> 0, 1, 2, 3</td><td>
940
<tr><td>SQ_FULL_STALL_CYCLES</td><td>   Super Queue full stall cycles </td><td> all</td><td>
941
    0x01: No unit mask
941
    0x01: No unit mask
942
 <br />
942
 <br />
943
</td>
944
945
</tr>
943
</td>
946
944
945
</tr>
946
947
<tr><td>FP_ASSIST</td><td>  X87 Floating point assists (Precise Event) </td><td> 0, 1, 2, 3</td><td>
947
<tr><td>FP_ASSIST</td><td>  X87 Floating point assists (Precise Event) </td><td> all</td><td>
948
    0x01: all X87 Floating point assists (Precise Event)
948
    0x01: (name=all) X87 Floating point assists (Precise Event)
949
 <br />
949
 <br />
950
    0x02: output X87 Floating point assists for invalid output value (Precise Event)
950
    0x02: (name=output) X87 Floating point assists for invalid output value (Precise Event)
951
 <br />
951
 <br />
952
    0x04: input X87 Floating poiint assists for invalid input value (Precise Event)
952
    0x04: (name=input) X87 Floating poiint assists for invalid input value (Precise Event)
953
 <br />
953
 <br />
954
</td>
955
956
</tr>
954
</td>
957
955
956
</tr>
957
958
<tr><td>SIMD_INT_64</td><td>    SIMD integer 64 bit pack operations </td><td> 0, 1, 2, 3</td><td>
958
<tr><td>SIMD_INT_64</td><td>    SIMD integer 64 bit pack operations </td><td> all</td><td>
959
    0x01: packed_mpy SIMD integer 64 bit packed multiply operations
959
    0x01: (name=packed_mpy) SIMD integer 64 bit packed multiply operations
960
 <br />
960
 <br />
961
    0x02: packed_shift SIMD integer 64 bit shift operations
961
    0x02: (name=packed_shift) SIMD integer 64 bit shift operations
962
 <br />
962
 <br />
963
    0x04: pack SIMD integer 64 bit pack operations
963
    0x04: (name=pack) SIMD integer 64 bit pack operations
964
 <br />
964
 <br />
965
    0x08: unpack SIMD integer 64 bit unpack operations
965
    0x08: (name=unpack) SIMD integer 64 bit unpack operations
966
 <br />
966
 <br />
967
    0x10: packed_logical SIMD integer 64 bit logical operations
967
    0x10: (name=packed_logical) SIMD integer 64 bit logical operations
968
 <br />
968
 <br />
969
    0x20: packed_arith SIMD integer 64 bit arithmetic operations
969
    0x20: (name=packed_arith) SIMD integer 64 bit arithmetic operations
970
 <br />
970
 <br />
971
    0x40: shuffle_move SIMD integer 64 bit shuffle/move operations
971
    0x40: (name=shuffle_move) SIMD integer 64 bit shuffle/move operations
972
 <br />
972
 <br />
973
</td>
974
975
</tr>
973
</td>
976
974
975
</tr>
976

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