Diff of /docs/intel-sandybridge-events [9766c7] .. [28a31d]  Maximize  Restore

Switch to unified view

a/docs/intel-sandybridge-events b/docs/intel-sandybridge-events
...
...
38
</td>
38
</td>
39
39
40
</tr>
40
</tr>
41
41
42
<tr><td>ld_blocks</td><td>  blocked loads </td><td> all</td><td>
42
<tr><td>ld_blocks</td><td>  blocked loads </td><td> all</td><td>
43
    0x01: data_unknown blocked loads due to store buffer blocks with unknown data.
43
    0x01: (name=data_unknown) blocked loads due to store buffer blocks with unknown data.
44
 <br />
44
 <br />
45
    0x02: store_forward loads blocked by overlapping with store buffer that cannot be forwarded
45
    0x02: (name=store_forward) loads blocked by overlapping with store buffer that cannot be forwarded
46
 <br />
46
 <br />
47
    0x08: no_sr This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.
47
    0x08: (name=no_sr) This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.
48
 <br />
48
 <br />
49
    0x10: all_block Number of cases where any load is blocked but has no DCU miss.
49
    0x10: (name=all_block) Number of cases where any load is blocked but has no DCU miss.
50
 <br />
50
 <br />
51
</td>
51
</td>
52
52
53
</tr>
53
</tr>
54
54
55
<tr><td>misalign_mem_ref</td><td>   Misaligned memory references </td><td> all</td><td>
55
<tr><td>misalign_mem_ref</td><td>   Misaligned memory references </td><td> all</td><td>
56
    0x01: loads Speculative cache-line split load uops dispatched to the L1D.
56
    0x01: (name=loads) Speculative cache-line split load uops dispatched to the L1D.
57
 <br />
57
 <br />
58
    0x02: stores Speculative cache-line split Store-address uops dispatched to L1D
58
    0x02: (name=stores) Speculative cache-line split Store-address uops dispatched to L1D
59
 <br />
59
 <br />
60
</td>
60
</td>
61
61
62
</tr>
62
</tr>
63
63
64
<tr><td>ld_blocks_partial</td><td>  Partial loads </td><td> all</td><td>
64
<tr><td>ld_blocks_partial</td><td>  Partial loads </td><td> all</td><td>
65
    0x01: address_alias False dependencies in MOB due to partial compare on address
65
    0x01: (name=address_alias) False dependencies in MOB due to partial compare on address
66
 <br />
66
 <br />
67
    0x08: all_sta_block This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.
67
    0x08: (name=all_sta_block) This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.
68
 <br />
68
 <br />
69
</td>
69
</td>
70
70
71
</tr>
71
</tr>
72
72
73
<tr><td>dtlb_load_misses</td><td>   D-TLB misses </td><td> all</td><td>
73
<tr><td>dtlb_load_misses</td><td>   D-TLB misses </td><td> all</td><td>
74
    0x01: miss_causes_a_walk Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G)
74
    0x01: (name=miss_causes_a_walk) Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G)
75
 <br />
75
 <br />
76
    0x02: walk_completed Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G)
76
    0x02: (name=walk_completed) Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G)
77
 <br />
77
 <br />
78
    0x04: walk_duration Cycles PMH is busy with this walk
78
    0x04: (name=walk_duration) Cycles PMH is busy with this walk
79
 <br />
79
 <br />
80
    0x10: stlb_hit First level miss but second level hit; no page walk.
80
    0x10: (name=stlb_hit) First level miss but second level hit; no page walk.
81
 <br />
81
 <br />
82
</td>
82
</td>
83
83
84
</tr>
84
</tr>
85
85
86
<tr><td>int_misc</td><td>   Instruction decoder events </td><td> all</td><td>
86
<tr><td>int_misc</td><td>   Instruction decoder events </td><td> all</td><td>
87
    0x40: rat_stall_cycles Cycles Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for this thread.
87
    0x40: (name=rat_stall_cycles) Cycles Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for this thread.
88
 <br />
88
 <br />
89
    0x03: recovery_cycles Number of cycles waiting to be recover after Nuke due to all other cases except JEClear. (extra: cmask=1)
89
    0x03: (name=recovery_cycles) Number of cycles waiting to be recover after Nuke due to all other cases except JEClear.
90
 <br />
90
 <br />
91
    0x03: recovery_stalls_count Edge applied to recovery_cycles, thus counts occurrences. (extra: edge cmask=1)
91
    0x03: (name=recovery_stalls_count) Edge applied to recovery_cycles, thus counts occurrences.
92
 <br />
92
 <br />
93
</td>
94
95
</tr>
93
</td>
96
94
95
</tr>
96
97
<tr><td>uops_issued</td><td>    Number of Uops issued </td><td> 0, 1, 2, 3</td><td>
97
<tr><td>uops_issued</td><td>    Number of Uops issued </td><td> all</td><td>
98
    0x01: any Number of Uops issued by the Resource Allocation Table (RAT) to the Reservation Station (RS)
98
    0x01: (name=any) Number of Uops issued by the Resource Allocation Table (RAT) to the Reservation Station (RS)
99
 <br />
99
 <br />
100
    0x01: stall_cycles cycles no uops issued by this thread. (extra: inv cmask=1)
100
    0x01: (name=stall_cycles) cycles no uops issued by this thread.
101
 <br />
101
 <br />
102
</td>
102
</td>
103
103
104
</tr>
104
</tr>
105
105
106
<tr><td>arith</td><td>  Misc ALU events </td><td> all</td><td>
106
<tr><td>arith</td><td>  Misc ALU events </td><td> all</td><td>
107
    0x01: fpu_div_active Cycles that the divider is busy with any divide or sqrt operation.
107
    0x01: (name=fpu_div_active) Cycles that the divider is busy with any divide or sqrt operation.
108
 <br />
108
 <br />
109
    0x01: fpu_div Number of times that the divider is actived, includes INT, SIMD and FP. (extra: edge cmask=1)
109
    0x01: (name=fpu_div) Number of times that the divider is actived, includes INT, SIMD and FP.
110
 <br />
110
 <br />
111
</td>
111
</td>
112
112
113
</tr>
113
</tr>
114
114
...
...
118
</td>
118
</td>
119
119
120
</tr>
120
</tr>
121
121
122
<tr><td>l2_rqsts</td><td>   Requests from L2 cache </td><td> all</td><td>
122
<tr><td>l2_rqsts</td><td>   Requests from L2 cache </td><td> all</td><td>
123
    0x01: demand_data_rd_hit Demand Data Read hit L2, no rejects
123
    0x01: (name=demand_data_rd_hit) Demand Data Read hit L2, no rejects
124
 <br />
124
 <br />
125
    0x04: rfo_hit RFO requests that hit L2 cache
125
    0x04: (name=rfo_hit) RFO requests that hit L2 cache
126
 <br />
126
 <br />
127
    0x08: rfo_miss RFO requests that miss L2 cache
127
    0x08: (name=rfo_miss) RFO requests that miss L2 cache
128
 <br />
128
 <br />
129
    0x10: code_rd_hit L2 cache hits when fetching instructions, code reads.
129
    0x10: (name=code_rd_hit) L2 cache hits when fetching instructions, code reads.
130
 <br />
130
 <br />
131
    0x20: code_rd_miss L2 cache misses when fetching instructions
131
    0x20: (name=code_rd_miss) L2 cache misses when fetching instructions
132
 <br />
132
 <br />
133
    0x40: pf_hit Requests from the L2 hardware prefetchers that hit L2 cache
133
    0x40: (name=pf_hit) Requests from the L2 hardware prefetchers that hit L2 cache
134
 <br />
134
 <br />
135
    0x80: pf_miss Requests from the L2 hardware prefetchers that miss L2 cache
135
    0x80: (name=pf_miss) Requests from the L2 hardware prefetchers that miss L2 cache
136
 <br />
136
 <br />
137
    0x03: all_demand_data_rd Any data read request to L2 cache
137
    0x03: (name=all_demand_data_rd) Any data read request to L2 cache
138
 <br />
138
 <br />
139
    0x0c: all_rfo Any data RFO request to L2 cache
139
    0x0c: (name=all_rfo) Any data RFO request to L2 cache
140
 <br />
140
 <br />
141
    0x30: all_code_rd Any code read request to L2 cache
141
    0x30: (name=all_code_rd) Any code read request to L2 cache
142
 <br />
142
 <br />
143
    0xc0: all_pf Any L2 HW prefetch request to L2 cache
143
    0xc0: (name=all_pf) Any L2 HW prefetch request to L2 cache
144
 <br />
144
 <br />
145
</td>
145
</td>
146
146
147
</tr>
147
</tr>
148
148
149
<tr><td>l2_store_lock_rqsts</td><td>    L2 cache store lock requests </td><td> all</td><td>
149
<tr><td>l2_store_lock_rqsts</td><td>    L2 cache store lock requests </td><td> all</td><td>
150
    0x0f: all RFOs that access cache lines in any state
150
    0x0f: (name=all) RFOs that access cache lines in any state
151
 <br />
151
 <br />
152
    0x01: miss RFO (as a result of regular RFO or Lock request) miss cache - I state
152
    0x01: (name=miss) RFO (as a result of regular RFO or Lock request) miss cache - I state
153
 <br />
153
 <br />
154
    0x04: hit_e RFO (as a result of regular RFO or Lock request) hits cache in E state
154
    0x04: (name=hit_e) RFO (as a result of regular RFO or Lock request) hits cache in E state
155
 <br />
155
 <br />
156
    0x08: hit_m RFO (as a result of regular RFO or Lock request) hits cache in M state
156
    0x08: (name=hit_m) RFO (as a result of regular RFO or Lock request) hits cache in M state
157
 <br />
157
 <br />
158
</td>
158
</td>
159
159
160
</tr>
160
</tr>
161
161
162
<tr><td>l2_l1d_wb_rqsts</td><td>    writebacks from L1D to the L2 cache </td><td> all</td><td>
162
<tr><td>l2_l1d_wb_rqsts</td><td>    writebacks from L1D to the L2 cache </td><td> all</td><td>
163
    0x04: hit_e writebacks from L1D to L2 cache lines in E state
163
    0x04: (name=hit_e) writebacks from L1D to L2 cache lines in E state
164
 <br />
164
 <br />
165
    0x08: hit_m writebacks from L1D to L2 cache lines in M state
165
    0x08: (name=hit_m) writebacks from L1D to L2 cache lines in M state
166
 <br />
166
 <br />
167
</td>
167
</td>
168
168
169
</tr>
169
</tr>
170
170
171
<tr><td>l1d_pend_miss</td><td>  Cycles with L1D load Misses outstanding. </td><td> 2</td><td>
171
<tr><td>l1d_pend_miss</td><td>  Cycles with L1D load Misses outstanding. </td><td> 2</td><td>
172
    0x01: pending Cycles with L1D load Misses outstanding.
172
    0x01: (name=pending) Cycles with L1D load Misses outstanding.
173
 <br />
173
 <br />
174
    0x01: occurences This event counts the number of L1D misses outstanding occurences. (extra: edge cmask=1)
174
    0x01: (name=occurences) This event counts the number of L1D misses outstanding occurences.
175
 <br />
175
 <br />
176
</td>
176
</td>
177
177
178
</tr>
178
</tr>
179
179
180
<tr><td>dtlb_store_misses</td><td>  D-TLB store misses </td><td> all</td><td>
180
<tr><td>dtlb_store_misses</td><td>  D-TLB store misses </td><td> all</td><td>
181
    0x01: miss_causes_a_walk Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G)
181
    0x01: (name=miss_causes_a_walk) Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G)
182
 <br />
182
 <br />
183
    0x02: walk_completed Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G)
183
    0x02: (name=walk_completed) Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G)
184
 <br />
184
 <br />
185
    0x04: walk_duration Cycles PMH is busy with this walk
185
    0x04: (name=walk_duration) Cycles PMH is busy with this walk
186
 <br />
186
 <br />
187
    0x10: stlb_hit First level miss but second level hit; no page walk. Only relevant if multiple levels.
187
    0x10: (name=stlb_hit) First level miss but second level hit; no page walk. Only relevant if multiple levels.
188
 <br />
188
 <br />
189
</td>
189
</td>
190
190
191
</tr>
191
</tr>
192
192
193
<tr><td>load_hit_pre</td><td>   Load dispatches that hit fill buffer </td><td> all</td><td>
193
<tr><td>load_hit_pre</td><td>   Load dispatches that hit fill buffer </td><td> all</td><td>
194
    0x01: sw_pf Load dispatches that hit fill buffer allocated for S/W prefetch.
194
    0x01: (name=sw_pf) Load dispatches that hit fill buffer allocated for S/W prefetch.
195
 <br />
195
 <br />
196
    0x02: hw_pf Load dispatches that hit fill buffer allocated for HW prefetch.
196
    0x02: (name=hw_pf) Load dispatches that hit fill buffer allocated for HW prefetch.
197
 <br />
197
 <br />
198
</td>
198
</td>
199
199
200
</tr>
200
</tr>
201
201
...
...
205
</td>
205
</td>
206
206
207
</tr>
207
</tr>
208
208
209
<tr><td>l1d</td><td>    L1D cache events </td><td> all</td><td>
209
<tr><td>l1d</td><td>    L1D cache events </td><td> all</td><td>
210
    0x01: replacement L1D Data line replacements.
210
    0x01: (name=replacement) L1D Data line replacements.
211
 <br />
211
 <br />
212
    0x02: allocated_in_m L1D M-state Data Cache Lines Allocated
212
    0x02: (name=allocated_in_m) L1D M-state Data Cache Lines Allocated
213
 <br />
213
 <br />
214
    0x04: eviction L1D M-state Data Cache Lines Evicted due to replacement (only)
214
    0x04: (name=eviction) L1D M-state Data Cache Lines Evicted due to replacement (only)
215
 <br />
215
 <br />
216
    0x08: all_m_replacement All Modified lines evicted out of L1D
216
    0x08: (name=all_m_replacement) All Modified lines evicted out of L1D
217
 <br />
217
 <br />
218
</td>
218
</td>
219
219
220
</tr>
220
</tr>
221
221
222
<tr><td>partial_rat_stalls</td><td> Partial RAT stalls </td><td> all</td><td>
222
<tr><td>partial_rat_stalls</td><td> Partial RAT stalls </td><td> all</td><td>
223
    0x20: flags_merge_uop Number of perf sensitive flags-merge uops added by Sandy Bridge u-arch.
223
    0x20: (name=flags_merge_uop) Number of perf sensitive flags-merge uops added by Sandy Bridge u-arch.
224
 <br />
224
 <br />
225
    0x40: slow_lea_window Number of cycles with at least 1 slow Load Effective Address (LEA) uop being allocated.
225
    0x40: (name=slow_lea_window) Number of cycles with at least 1 slow Load Effective Address (LEA) uop being allocated.
226
 <br />
226
 <br />
227
    0x80: mul_single_uop Number of Multiply packed/scalar single precision uops allocated
227
    0x80: (name=mul_single_uop) Number of Multiply packed/scalar single precision uops allocated
228
 <br />
228
 <br />
229
    0x20: flags_merge_uop_cycles Cycles with perf sensitive flags-merge uops added by SandyBridge u-arch. (extra: cmask=1)
229
    0x20: (name=flags_merge_uop_cycles) Cycles with perf sensitive flags-merge uops added by SandyBridge u-arch.
230
 <br />
230
 <br />
231
</td>
232
233
</tr>
231
</td>
234
232
233
</tr>
234
235
<tr><td>resource_stalls2</td><td>   Misc resource stalls </td><td> 0, 1, 2, 3</td><td>
235
<tr><td>resource_stalls2</td><td>   Misc resource stalls </td><td> all</td><td>
236
    0x40: bob_full Cycles Allocator is stalled due Branch Order Buffer (BOB).
236
    0x40: (name=bob_full) Cycles Allocator is stalled due Branch Order Buffer (BOB).
237
 <br />
237
 <br />
238
    0x0f: all_prf_control Resource stalls2 control structures full for physical registers
238
    0x0f: (name=all_prf_control) Resource stalls2 control structures full for physical registers
239
 <br />
239
 <br />
240
    0x0c: all_fl_empty Cycles with either free list is empty
240
    0x0c: (name=all_fl_empty) Cycles with either free list is empty
241
 <br />
241
 <br />
242
    0x4f: ooo_rsrc Resource stalls2 control structures full Physical Register Reclaim Table (PRRT), Physical History Table (PHT), INT or SIMD Free List (FL), Branch Order Buffer (BOB)
242
    0x4f: (name=ooo_rsrc) Resource stalls2 control structures full Physical Register Reclaim Table (PRRT), Physical History Table (PHT), INT or SIMD Free List (FL), Branch Order Buffer (BOB)
243
 <br />
243
 <br />
244
</td>
244
</td>
245
245
246
</tr>
246
</tr>
247
247
248
<tr><td>cpl_cycles</td><td> Unhalted core cycles in specific rings </td><td> all</td><td>
248
<tr><td>cpl_cycles</td><td> Unhalted core cycles in specific rings </td><td> all</td><td>
249
    0x01: ring0 Unhalted core cycles the Thread was in Rings 0.
249
    0x01: (name=ring0) Unhalted core cycles the Thread was in Rings 0.
250
 <br />
250
 <br />
251
    0x01: ring0_trans Transitions from ring123 to Ring0. (extra: edge cmask=1)
251
    0x01: (name=ring0_trans) Transitions from ring123 to Ring0.
252
 <br />
252
 <br />
253
    0x02: ring123 Unhalted core cycles the Thread was in Rings 1/2/3.
253
    0x02: (name=ring123) Unhalted core cycles the Thread was in Rings 1/2/3.
254
 <br />
254
 <br />
255
</td>
256
257
</tr>
255
</td>
258
256
257
</tr>
258
259
<tr><td>rs_events</td><td>  Events for the reservation station </td><td> 0, 1, 2, 3</td><td>
259
<tr><td>rs_events</td><td>  Events for the reservation station </td><td> all</td><td>
260
    0x01: No unit mask
260
    0x01: No unit mask
261
 <br />
261
 <br />
262
</td>
262
</td>
263
263
264
</tr>
264
</tr>
265
265
266
<tr><td>offcore_requests_outstanding</td><td>   Offcore outstanding transactions </td><td> all</td><td>
266
<tr><td>offcore_requests_outstanding</td><td>   Offcore outstanding transactions </td><td> all</td><td>
267
    0x01: demand_data_rd Offcore outstanding Demand Data Read transactions in the SuperQueue (SQ), queue to uncore, every cycle. Includes L1D data hardware prefetches.
267
    0x01: (name=demand_data_rd) Offcore outstanding Demand Data Read transactions in the SuperQueue (SQ), queue to uncore, every cycle. Includes L1D data hardware prefetches.
268
 <br />
268
 <br />
269
    0x01: cycles_with_demand_data_rd cycles there are Offcore outstanding RD data transactions in the SuperQueue (SQ), queue to uncore. (extra: cmask=1)
269
    0x01: (name=cycles_with_demand_data_rd) cycles there are Offcore outstanding RD data transactions in the SuperQueue (SQ), queue to uncore.
270
 <br />
270
 <br />
271
    0x02: demand_code_rd Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.
271
    0x02: (name=demand_code_rd) Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.
272
 <br />
272
 <br />
273
    0x04: demand_rfo Offcore outstanding RFO (store) transactions in the SuperQueue (SQ), queue to uncore, every cycle.
273
    0x04: (name=demand_rfo) Offcore outstanding RFO (store) transactions in the SuperQueue (SQ), queue to uncore, every cycle.
274
 <br />
274
 <br />
275
    0x08: all_data_rd Offcore outstanding all cacheable Core Data Read transactions in the SuperQueue (SQ), queue to uncore, every cycle.
275
    0x08: (name=all_data_rd) Offcore outstanding all cacheable Core Data Read transactions in the SuperQueue (SQ), queue to uncore, every cycle.
276
 <br />
276
 <br />
277
    0x08: cycles_with_data_rd Cycles there are Offcore outstanding all Data read transactions in the SuperQueue (SQ), queue to uncore, every cycle. (extra: cmask=1)
277
    0x08: (name=cycles_with_data_rd) Cycles there are Offcore outstanding all Data read transactions in the SuperQueue (SQ), queue to uncore, every cycle.
278
 <br />
278
 <br />
279
    0x02: cycles_with_demand_code_rd Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle. (extra: cmask=1)
279
    0x02: (name=cycles_with_demand_code_rd) Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.
280
 <br />
280
 <br />
281
    0x04: cycles_with_demand_rfo Cycles with offcore outstanding demand RFO Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle. (extra: cmask=1)
281
    0x04: (name=cycles_with_demand_rfo) Cycles with offcore outstanding demand RFO Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.
282
 <br />
282
 <br />
283
</td>
283
</td>
284
284
285
</tr>
285
</tr>
286
286
287
<tr><td>lock_cycles</td><td>    Cycles due to LOCK prefixes. </td><td> all</td><td>
287
<tr><td>lock_cycles</td><td>    Cycles due to LOCK prefixes. </td><td> all</td><td>
288
    0x01: split_lock_uc_lock_duration Cycles in which the L1D and L2 are locked, due to a UC lock or split lock
288
    0x01: (name=split_lock_uc_lock_duration) Cycles in which the L1D and L2 are locked, due to a UC lock or split lock
289
 <br />
289
 <br />
290
    0x02: cache_lock_duration cycles that theL1D is locked
290
    0x02: (name=cache_lock_duration) cycles that theL1D is locked
291
 <br />
291
 <br />
292
</td>
293
294
</tr>
292
</td>
295
293
294
</tr>
295
296
<tr><td>idq</td><td>    Instruction Decode Queue events </td><td> 0, 1, 2, 3</td><td>
296
<tr><td>idq</td><td>    Instruction Decode Queue events </td><td> all</td><td>
297
    0x02: empty Cycles the Instruction Decode Queue (IDQ) is empty.
297
    0x02: (name=empty) Cycles the Instruction Decode Queue (IDQ) is empty.
298
 <br />
298
 <br />
299
    0x04: mite_uops Number of uops delivered to Instruction Decode Queue (IDQ) from MITE path.
299
    0x04: (name=mite_uops) Number of uops delivered to Instruction Decode Queue (IDQ) from MITE path.
300
 <br />
300
 <br />
301
    0x08: dsb_uops Number of uops delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.
301
    0x08: (name=dsb_uops) Number of uops delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.
302
 <br />
302
 <br />
303
    0x10: ms_dsb_uops Number of Uops delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB).
303
    0x10: (name=ms_dsb_uops) Number of Uops delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB).
304
 <br />
304
 <br />
305
    0x20: ms_mite_uops Number of Uops delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by MITE.
305
    0x20: (name=ms_mite_uops) Number of Uops delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by MITE.
306
 <br />
306
 <br />
307
    0x30: ms_uops Number of Uops were delivered into Instruction Decode Queue (IDQ) from MS, initiated by Decode Stream Buffer (DSB) or MITE.
307
    0x30: (name=ms_uops) Number of Uops were delivered into Instruction Decode Queue (IDQ) from MS, initiated by Decode Stream Buffer (DSB) or MITE.
308
 <br />
308
 <br />
309
    0x30: ms_cycles Number of cycles that Uops were delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB) or MITE. (extra: cmask=1)
309
    0x30: (name=ms_cycles) Number of cycles that Uops were delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB) or MITE.
310
 <br />
310
 <br />
311
    0x04: mite_cycles Cycles MITE is active (extra: cmask=1)
311
    0x04: (name=mite_cycles) Cycles MITE is active
312
 <br />
312
 <br />
313
    0x08: dsb_cycles Cycles Decode Stream Buffer (DSB) is active (extra: cmask=1)
313
    0x08: (name=dsb_cycles) Cycles Decode Stream Buffer (DSB) is active
314
 <br />
314
 <br />
315
    0x10: ms_dsb_cycles Cycles Decode Stream Buffer (DSB) Microcode Sequenser (MS) is active (extra: cmask=1)
315
    0x10: (name=ms_dsb_cycles) Cycles Decode Stream Buffer (DSB) Microcode Sequenser (MS) is active
316
 <br />
316
 <br />
317
    0x10: ms_dsb_occur Occurences of Decode Stream Buffer (DSB) Microcode Sequenser (MS) going active (extra: edge cmask=1)
317
    0x10: (name=ms_dsb_occur) Occurences of Decode Stream Buffer (DSB) Microcode Sequenser (MS) going active
318
 <br />
318
 <br />
319
    0x18: all_dsb_cycles_any_uops Cycles Decode Stream Buffer (DSB) is delivering anything (extra: cmask=1)
319
    0x18: (name=all_dsb_cycles_any_uops) Cycles Decode Stream Buffer (DSB) is delivering anything
320
 <br />
320
 <br />
321
    0x18: all_dsb_cycles_4_uops Cycles Decode Stream Buffer (DSB) is delivering 4 Uops (extra: cmask=4)
321
    0x18: (name=all_dsb_cycles_4_uops) Cycles Decode Stream Buffer (DSB) is delivering 4 Uops
322
 <br />
322
 <br />
323
    0x24: all_mite_cycles_any_uops Cycles MITE is delivering anything (extra: cmask=1)
323
    0x24: (name=all_mite_cycles_any_uops) Cycles MITE is delivering anything
324
 <br />
324
 <br />
325
    0x24: all_mite_cycles_4_uops Cycles MITE is delivering 4 Uops (extra: cmask=4)
325
    0x24: (name=all_mite_cycles_4_uops) Cycles MITE is delivering 4 Uops
326
 <br />
326
 <br />
327
    0x3c: mite_all_uops Number of uops delivered to Instruction Decode Queue (IDQ) from any path.
327
    0x3c: (name=mite_all_uops) Number of uops delivered to Instruction Decode Queue (IDQ) from any path.
328
 <br />
328
 <br />
329
</td>
329
</td>
330
330
331
</tr>
331
</tr>
332
332
...
...
336
</td>
336
</td>
337
337
338
</tr>
338
</tr>
339
339
340
<tr><td>itlb_misses</td><td>    I-TLB misses </td><td> all</td><td>
340
<tr><td>itlb_misses</td><td>    I-TLB misses </td><td> all</td><td>
341
    0x01: miss_causes_a_walk Miss in all TLB levels causes an page walk of any page size (4K/2M/4M)
341
    0x01: (name=miss_causes_a_walk) Miss in all TLB levels causes an page walk of any page size (4K/2M/4M)
342
 <br />
342
 <br />
343
    0x02: walk_completed Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M)
343
    0x02: (name=walk_completed) Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M)
344
 <br />
344
 <br />
345
    0x04: walk_duration Cycles PMH is busy with this walk.
345
    0x04: (name=walk_duration) Cycles PMH is busy with this walk.
346
 <br />
346
 <br />
347
    0x10: stlb_hit First level miss but second level hit; no page walk.
347
    0x10: (name=stlb_hit) First level miss but second level hit; no page walk.
348
 <br />
348
 <br />
349
</td>
349
</td>
350
350
351
</tr>
351
</tr>
352
352
353
<tr><td>ild_stall</td><td>  Instruction decoding stalls </td><td> all</td><td>
353
<tr><td>ild_stall</td><td>  Instruction decoding stalls </td><td> all</td><td>
354
    0x01: lcp Stall "occurrences" due to length changing prefixes (LCP).
354
    0x01: (name=lcp) Stall "occurrences" due to length changing prefixes (LCP).
355
 <br />
355
 <br />
356
    0x04: iq_full Stall cycles when instructions cannot be written because the Instruction Queue (IQ) is full.
356
    0x04: (name=iq_full) Stall cycles when instructions cannot be written because the Instruction Queue (IQ) is full.
357
 <br />
357
 <br />
358
</td>
358
</td>
359
359
360
</tr>
360
</tr>
361
361
362
<tr><td>br_inst_exec</td><td>   Branch instructions </td><td> all</td><td>
362
<tr><td>br_inst_exec</td><td>   Branch instructions </td><td> all</td><td>
363
    0xff: all_branches All branch instructions executed.
363
    0xff: (name=all_branches) All branch instructions executed.
364
 <br />
364
 <br />
365
    0x41: nontaken_conditional All macro conditional nontaken branch instructions.
365
    0x41: (name=nontaken_conditional) All macro conditional nontaken branch instructions.
366
 <br />
366
 <br />
367
    0x81: taken_conditional All macro conditional taken branch instructions.
367
    0x81: (name=taken_conditional) All macro conditional taken branch instructions.
368
 <br />
368
 <br />
369
    0x82: taken_direct_jump All macro unconditional taken branch instructions, excluding calls and indirects.
369
    0x82: (name=taken_direct_jump) All macro unconditional taken branch instructions, excluding calls and indirects.
370
 <br />
370
 <br />
371
    0x84: taken_indirect_jump_non_call_ret All taken indirect branches that are not calls nor returns.
371
    0x84: (name=taken_indirect_jump_non_call_ret) All taken indirect branches that are not calls nor returns.
372
 <br />
372
 <br />
373
    0x88: taken_indirect_near_return All taken indirect branches that have a return mnemonic.
373
    0x88: (name=taken_indirect_near_return) All taken indirect branches that have a return mnemonic.
374
 <br />
374
 <br />
375
    0x90: taken_direct_near_call All taken non-indirect calls.
375
    0x90: (name=taken_direct_near_call) All taken non-indirect calls.
376
 <br />
376
 <br />
377
    0xa0: taken_indirect_near_call All taken indirect calls, including both register and memory indirect.
377
    0xa0: (name=taken_indirect_near_call) All taken indirect calls, including both register and memory indirect.
378
 <br />
378
 <br />
379
    0xc1: all_conditional All macro conditional branch instructions.
379
    0xc1: (name=all_conditional) All macro conditional branch instructions.
380
 <br />
380
 <br />
381
    0xc2: all_direct_jmp All macro unconditional branch instructions, excluding calls and indirects
381
    0xc2: (name=all_direct_jmp) All macro unconditional branch instructions, excluding calls and indirects
382
 <br />
382
 <br />
383
    0xc4: all_indirect_jump_non_call_ret All indirect branches that are not calls nor returns.
383
    0xc4: (name=all_indirect_jump_non_call_ret) All indirect branches that are not calls nor returns.
384
 <br />
384
 <br />
385
    0xc8: all_indirect_near_return All indirect return branches.
385
    0xc8: (name=all_indirect_near_return) All indirect return branches.
386
 <br />
386
 <br />
387
    0xd0: all_direct_near_call All non-indirect calls executed.
387
    0xd0: (name=all_direct_near_call) All non-indirect calls executed.
388
 <br />
388
 <br />
389
</td>
389
</td>
390
390
391
</tr>
391
</tr>
392
392
393
<tr><td>br_misp_exec</td><td>   Mispredicted branch instructions </td><td> all</td><td>
393
<tr><td>br_misp_exec</td><td>   Mispredicted branch instructions </td><td> all</td><td>
394
    0xff: all_branches All mispredicted branch instructions executed.
394
    0xff: (name=all_branches) All mispredicted branch instructions executed.
395
 <br />
395
 <br />
396
    0x41: nontaken_conditional All nontaken mispredicted macro conditional branch instructions.
396
    0x41: (name=nontaken_conditional) All nontaken mispredicted macro conditional branch instructions.
397
 <br />
397
 <br />
398
    0x81: taken_conditional All taken mispredicted macro conditional branch instructions.
398
    0x81: (name=taken_conditional) All taken mispredicted macro conditional branch instructions.
399
 <br />
399
 <br />
400
    0x84: taken_indirect_jump_non_call_ret All taken mispredicted indirect branches that are not calls nor returns.
400
    0x84: (name=taken_indirect_jump_non_call_ret) All taken mispredicted indirect branches that are not calls nor returns.
401
 <br />
401
 <br />
402
    0x88: taken_return_near All taken mispredicted indirect branches that have a return mnemonic.
402
    0x88: (name=taken_return_near) All taken mispredicted indirect branches that have a return mnemonic.
403
 <br />
403
 <br />
404
    0x90: taken_direct_near_call All taken mispredicted non-indirect calls.
404
    0x90: (name=taken_direct_near_call) All taken mispredicted non-indirect calls.
405
 <br />
405
 <br />
406
    0xa0: taken_indirect_near_call All taken mispredicted indirect calls, including both register and memory indirect.
406
    0xa0: (name=taken_indirect_near_call) All taken mispredicted indirect calls, including both register and memory indirect.
407
 <br />
407
 <br />
408
    0xc1: all_conditional All mispredicted macro conditional branch instructions.
408
    0xc1: (name=all_conditional) All mispredicted macro conditional branch instructions.
409
 <br />
409
 <br />
410
    0xc4: all_indirect_jump_non_call_ret All mispredicted indirect branches that are not calls nor returns.
410
    0xc4: (name=all_indirect_jump_non_call_ret) All mispredicted indirect branches that are not calls nor returns.
411
 <br />
411
 <br />
412
    0xd0: all_direct_near_call All mispredicted non-indirect calls
412
    0xd0: (name=all_direct_near_call) All mispredicted non-indirect calls
413
 <br />
413
 <br />
414
</td>
415
416
</tr>
414
</td>
417
415
416
</tr>
417
418
<tr><td>idq_uops_not_delivered</td><td> uops not delivered to IDQ. </td><td> 0, 1, 2, 3</td><td>
418
<tr><td>idq_uops_not_delivered</td><td> uops not delivered to IDQ. </td><td> all</td><td>
419
    0x01: core Count number of non-delivered uops to Resource Allocation Table (RAT).
419
    0x01: (name=core) Count number of non-delivered uops to Resource Allocation Table (RAT).
420
 <br />
420
 <br />
421
    0x01: cycles_0_uops_deliv.core Counts the cycles no uops were delivered (extra: cmask=4)
421
    0x01: (name=cycles_0_uops_deliv.core) Counts the cycles no uops were delivered
422
 <br />
422
 <br />
423
    0x01: cycles_le_1_uop_deliv.core Counts the cycles less than 1 uops were delivered (extra: cmask=3)
423
    0x01: (name=cycles_le_1_uop_deliv.core) Counts the cycles less than 1 uops were delivered
424
 <br />
424
 <br />
425
    0x01: cycles_le_2_uop_deliv.core Counts the cycles less than 2 uops were delivered (extra: cmask=2)
425
    0x01: (name=cycles_le_2_uop_deliv.core) Counts the cycles less than 2 uops were delivered
426
 <br />
426
 <br />
427
    0x01: cycles_le_3_uop_deliv.core Counts the cycles less than 3 uops were delivered (extra: cmask=1)
427
    0x01: (name=cycles_le_3_uop_deliv.core) Counts the cycles less than 3 uops were delivered
428
 <br />
428
 <br />
429
    0x01: cycles_ge_1_uop_deliv.core Cycles when 1 or more uops were delivered to the by the front end. (extra: inv cmask=4)
429
    0x01: (name=cycles_ge_1_uop_deliv.core) Cycles when 1 or more uops were delivered to the by the front end.
430
 <br />
430
 <br />
431
    0x01: cycles_fe_was_ok Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE. (extra: inv cmask=1)
431
    0x01: (name=cycles_fe_was_ok) Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.
432
 <br />
432
 <br />
433
</td>
433
</td>
434
434
435
</tr>
435
</tr>
436
436
437
<tr><td>uops_dispatched_port</td><td>   Count on which ports uops are dispatched. </td><td> all</td><td>
437
<tr><td>uops_dispatched_port</td><td>   Count on which ports uops are dispatched. </td><td> all</td><td>
438
    0x01: port_0 Cycles which a Uop is dispatched on port 0
438
    0x01: (name=port_0) Cycles which a Uop is dispatched on port 0
439
 <br />
439
 <br />
440
    0x02: port_1 Cycles which a Uop is dispatched on port 1
440
    0x02: (name=port_1) Cycles which a Uop is dispatched on port 1
441
 <br />
441
 <br />
442
    0x04: port_2_ld Cycles which a load Uop is dispatched on port 2
442
    0x04: (name=port_2_ld) Cycles which a load Uop is dispatched on port 2
443
 <br />
443
 <br />
444
    0x08: port_2_sta Cycles which a STA Uop is dispatched on port 2
444
    0x08: (name=port_2_sta) Cycles which a STA Uop is dispatched on port 2
445
 <br />
445
 <br />
446
    0x10: port_3_ld Cycles which a load Uop is dispatched on port 3
446
    0x10: (name=port_3_ld) Cycles which a load Uop is dispatched on port 3
447
 <br />
447
 <br />
448
    0x20: port_3_sta Cycles which a STA Uop is dispatched on port 3
448
    0x20: (name=port_3_sta) Cycles which a STA Uop is dispatched on port 3
449
 <br />
449
 <br />
450
    0x40: port_4 Cycles which a Uop is dispatched on port 4
450
    0x40: (name=port_4) Cycles which a Uop is dispatched on port 4
451
 <br />
451
 <br />
452
    0x80: port_5 Cycles which a Uop is dispatched on port 5
452
    0x80: (name=port_5) Cycles which a Uop is dispatched on port 5
453
 <br />
453
 <br />
454
    0x0c: port_2 Uops disptached to port 2, loads and stores (speculative and retired)
454
    0x0c: (name=port_2) Uops disptached to port 2, loads and stores (speculative and retired)
455
 <br />
455
 <br />
456
    0x30: port_3 Uops disptached to port 3, loads and stores (speculative and retired)
456
    0x30: (name=port_3) Uops disptached to port 3, loads and stores (speculative and retired)
457
 <br />
457
 <br />
458
    0x0c: port_2_core Uops disptached to port 2, loads and stores per core (speculative and retired)
458
    0x0c: (name=port_2_core) Uops disptached to port 2, loads and stores per core (speculative and retired)
459
 <br />
459
 <br />
460
    0x30: port_3_core Uops disptached to port 3, loads and stores per core (speculative and retired)
460
    0x30: (name=port_3_core) Uops disptached to port 3, loads and stores per core (speculative and retired)
461
 <br />
461
 <br />
462
</td>
462
</td>
463
463
464
</tr>
464
</tr>
465
465
466
<tr><td>resource_stalls</td><td>    Core resource stalls </td><td> all</td><td>
466
<tr><td>resource_stalls</td><td>    Core resource stalls </td><td> all</td><td>
467
    0x01: any Cycles Allocation is stalled due to Resource Related reason.
467
    0x01: (name=any) Cycles Allocation is stalled due to Resource Related reason.
468
 <br />
468
 <br />
469
    0x02: lb Cycles Allocator is stalled due to Load Buffer full
469
    0x02: (name=lb) Cycles Allocator is stalled due to Load Buffer full
470
 <br />
470
 <br />
471
    0x04: rs Stall due to no eligible Reservation Station (RS) entry available.
471
    0x04: (name=rs) Stall due to no eligible Reservation Station (RS) entry available.
472
 <br />
472
 <br />
473
    0x08: sb Cycles Allocator is stalled due to Store Buffer full (not including draining from synch).
473
    0x08: (name=sb) Cycles Allocator is stalled due to Store Buffer full (not including draining from synch).
474
 <br />
474
 <br />
475
    0x10: rob ROB full cycles.
475
    0x10: (name=rob) ROB full cycles.
476
 <br />
476
 <br />
477
    0x0e: mem_rs Resource stalls due to LB, SB or Reservation Station (RS) being completely in use
477
    0x0e: (name=mem_rs) Resource stalls due to LB, SB or Reservation Station (RS) being completely in use
478
 <br />
478
 <br />
479
    0xf0: ooo_rsrc Resource stalls due to Rob being full, FCSW, MXCSR and OTHER
479
    0xf0: (name=ooo_rsrc) Resource stalls due to Rob being full, FCSW, MXCSR and OTHER
480
 <br />
480
 <br />
481
    0x0a: lb_sb Resource stalls due to load or store buffers
481
    0x0a: (name=lb_sb) Resource stalls due to load or store buffers
482
 <br />
482
 <br />
483
</td>
483
</td>
484
484
485
</tr>
485
</tr>
486
486
487
<tr><td>dsb2mite_switches</td><td>  Number of Decode Stream Buffer (DSB) to MITE switches </td><td> all</td><td>
487
<tr><td>dsb2mite_switches</td><td>  Number of Decode Stream Buffer (DSB) to MITE switches </td><td> all</td><td>
488
    0x01: count Number of Decode Stream Buffer (DSB) to MITE switches
488
    0x01: (name=count) Number of Decode Stream Buffer (DSB) to MITE switches
489
 <br />
489
 <br />
490
    0x02: penalty_cycles Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.
490
    0x02: (name=penalty_cycles) Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.
491
 <br />
491
 <br />
492
</td>
492
</td>
493
493
494
</tr>
494
</tr>
495
495
496
<tr><td>dsb_fill</td><td>   DSB fill events </td><td> all</td><td>
496
<tr><td>dsb_fill</td><td>   DSB fill events </td><td> all</td><td>
497
    0x02: other_cancel Count number of times a valid DSB fill has been actually cancelled for any reason.
497
    0x02: (name=other_cancel) Count number of times a valid DSB fill has been actually cancelled for any reason.
498
 <br />
498
 <br />
499
    0x08: exceed_dsb_lines Decode Stream Buffer (DSB) Fill encountered > 3 Decode Stream Buffer (DSB) lines.
499
    0x08: (name=exceed_dsb_lines) Decode Stream Buffer (DSB) Fill encountered > 3 Decode Stream Buffer (DSB) lines.
500
 <br />
500
 <br />
501
    0x0a: all_cancel Count number of times a valid Decode Stream Buffer (DSB) fill has been actually cancelled for any reason.
501
    0x0a: (name=all_cancel) Count number of times a valid Decode Stream Buffer (DSB) fill has been actually cancelled for any reason.
502
 <br />
502
 <br />
503
</td>
503
</td>
504
504
505
</tr>
505
</tr>
506
506
...
...
510
</td>
510
</td>
511
511
512
</tr>
512
</tr>
513
513
514
<tr><td>offcore_requests</td><td>   Requests sent outside the core </td><td> all</td><td>
514
<tr><td>offcore_requests</td><td>   Requests sent outside the core </td><td> all</td><td>
515
    0x01: demand_data_rd Demand Data Read requests sent to uncore
515
    0x01: (name=demand_data_rd) Demand Data Read requests sent to uncore
516
 <br />
516
 <br />
517
    0x02: demand_code_rd Offcore Code read requests. Includes Cacheable and Un-cacheables.
517
    0x02: (name=demand_code_rd) Offcore Code read requests. Includes Cacheable and Un-cacheables.
518
 <br />
518
 <br />
519
    0x04: demand_rfo Offcore Demand RFOs. Includes regular RFO, Locks, ItoM.
519
    0x04: (name=demand_rfo) Offcore Demand RFOs. Includes regular RFO, Locks, ItoM.
520
 <br />
520
 <br />
521
    0x08: all_data_rd Offcore Demand and prefetch data reads returned to the core.
521
    0x08: (name=all_data_rd) Offcore Demand and prefetch data reads returned to the core.
522
 <br />
522
 <br />
523
</td>
524
525
</tr>
523
</td>
526
524
525
</tr>
526
527
<tr><td>uops_dispatched</td><td>    uops dispatched </td><td> 0, 1, 2, 3</td><td>
527
<tr><td>uops_dispatched</td><td>    uops dispatched </td><td> all</td><td>
528
    0x01: thread Counts total number of uops to be dispatched per-thread each cycle.
528
    0x01: (name=thread) Counts total number of uops to be dispatched per-thread each cycle.
529
 <br />
529
 <br />
530
    0x01: stall_cycles Counts number of cycles no uops were dispatced to be executed on this thread. (extra: inv cmask=1)
530
    0x01: (name=stall_cycles) Counts number of cycles no uops were dispatced to be executed on this thread.
531
 <br />
531
 <br />
532
    0x02: core Counts total number of uops dispatched from any thread
532
    0x02: (name=core) Counts total number of uops dispatched from any thread
533
 <br />
533
 <br />
534
</td>
534
</td>
535
535
536
</tr>
536
</tr>
537
537
...
...
548
</td>
548
</td>
549
549
550
</tr>
550
</tr>
551
551
552
<tr><td>tlb_flush</td><td>  TLB flushes </td><td> all</td><td>
552
<tr><td>tlb_flush</td><td>  TLB flushes </td><td> all</td><td>
553
    0x01: dtlb_thread Count number of DTLB flushes of thread-specific entries.
553
    0x01: (name=dtlb_thread) Count number of DTLB flushes of thread-specific entries.
554
 <br />
554
 <br />
555
    0x20: stlb_any Count number of any STLB flushes
555
    0x20: (name=stlb_any) Count number of any STLB flushes
556
 <br />
556
 <br />
557
</td>
557
</td>
558
558
559
</tr>
559
</tr>
560
560
561
<tr><td>l1d_blocks</td><td> L1D cache blocking events </td><td> all</td><td>
561
<tr><td>l1d_blocks</td><td> L1D cache blocking events </td><td> all</td><td>
562
    0x01: ld_bank_conflict Any dispatched loads cancelled due to DCU bank conflict
562
    0x01: (name=ld_bank_conflict) Any dispatched loads cancelled due to DCU bank conflict
563
 <br />
563
 <br />
564
    0x05: bank_conflict_cycles Cycles with l1d blocks due to bank conflicts (extra: cmask=1)
564
    0x05: (name=bank_conflict_cycles) Cycles with l1d blocks due to bank conflicts
565
 <br />
565
 <br />
566
</td>
566
</td>
567
567
568
</tr>
568
</tr>
569
569
...
...
573
</td>
573
</td>
574
574
575
</tr>
575
</tr>
576
576
577
<tr><td>other_assists</td><td>  Instructions that needed an assist </td><td> all</td><td>
577
<tr><td>other_assists</td><td>  Instructions that needed an assist </td><td> all</td><td>
578
    0x02: itlb_miss_retired Instructions that experienced an ITLB miss. Non Pebs
578
    0x02: (name=itlb_miss_retired) Instructions that experienced an ITLB miss. Non Pebs
579
 <br />
579
 <br />
580
    0x10: avx_to_sse Number of transitions from AVX-256 to legacy SSE when penalty applicable Non Pebs
580
    0x10: (name=avx_to_sse) Number of transitions from AVX-256 to legacy SSE when penalty applicable Non Pebs
581
 <br />
581
 <br />
582
    0x20: sse_to_avx Number of transitions from legacy SSE to AVX-256 when penalty applicable Non Pebs
582
    0x20: (name=sse_to_avx) Number of transitions from legacy SSE to AVX-256 when penalty applicable Non Pebs
583
 <br />
583
 <br />
584
</td>
585
586
</tr>
584
</td>
587
585
586
</tr>
587
588
<tr><td>uops_retired</td><td>   uops that actually retired. </td><td> 0, 1, 2, 3</td><td>
588
<tr><td>uops_retired</td><td>   uops that actually retired. </td><td> all</td><td>
589
    0x01: all All uops that actually retired.
589
    0x01: (name=all) All uops that actually retired.
590
 <br />
590
 <br />
591
    0x02: retire_slots number of retirement slots used non PEBS
591
    0x02: (name=retire_slots) number of retirement slots used non PEBS
592
 <br />
592
 <br />
593
    0x01: stall_cycles Cycles no executable uops retired (extra: inv cmask=1)
593
    0x01: (name=stall_cycles) Cycles no executable uops retired
594
 <br />
594
 <br />
595
    0x01: total_cycles Number of cycles using always true condition applied to non PEBS uops retired event. (extra: inv cmask=10)
595
    0x01: (name=total_cycles) Number of cycles using always true condition applied to non PEBS uops retired event.
596
 <br />
596
 <br />
597
</td>
597
</td>
598
598
599
</tr>
599
</tr>
600
600
601
<tr><td>machine_clears</td><td> Number of Machine Clears detected. </td><td> all</td><td>
601
<tr><td>machine_clears</td><td> Number of Machine Clears detected. </td><td> all</td><td>
602
    0x02: memory_ordering Number of Memory Ordering Machine Clears detected.
602
    0x02: (name=memory_ordering) Number of Memory Ordering Machine Clears detected.
603
 <br />
603
 <br />
604
    0x04: smc Number of Self-modifying code (SMC) Machine Clears detected.
604
    0x04: (name=smc) Number of Self-modifying code (SMC) Machine Clears detected.
605
 <br />
605
 <br />
606
    0x20: maskmov Number of AVX masked mov Machine Clears detected.
606
    0x20: (name=maskmov) Number of AVX masked mov Machine Clears detected.
607
 <br />
607
 <br />
608
</td>
609
610
</tr>
608
</td>
611
609
610
</tr>
611
612
<tr><td>br_inst_retired</td><td>    Counts branch instructions retired </td><td> 0, 1, 2, 3</td><td>
612
<tr><td>br_inst_retired</td><td>    Counts branch instructions retired </td><td> all</td><td>
613
    0x01: conditional Counts all taken and not taken macro conditional branch instructions.
613
    0x01: (name=conditional) Counts all taken and not taken macro conditional branch instructions.
614
 <br />
614
 <br />
615
    0x02: near_call Counts all macro direct and indirect near calls. non PEBS
615
    0x02: (name=near_call) Counts all macro direct and indirect near calls. non PEBS
616
 <br />
616
 <br />
617
    0x08: near_return This event counts the number of near ret instructions retired.
617
    0x08: (name=near_return) This event counts the number of near ret instructions retired.
618
 <br />
618
 <br />
619
    0x10: not_taken Counts all not taken macro branch instructions retired.
619
    0x10: (name=not_taken) Counts all not taken macro branch instructions retired.
620
 <br />
620
 <br />
621
    0x20: near_taken Counts the number of near branch taken instructions retired.
621
    0x20: (name=near_taken) Counts the number of near branch taken instructions retired.
622
 <br />
622
 <br />
623
    0x40: far_branch Counts the number of far branch instructions retired.
623
    0x40: (name=far_branch) Counts the number of far branch instructions retired.
624
 <br />
624
 <br />
625
    0x04: all_branches_ps Counts all taken and not taken macro branches including far branches.(Precise Event)
625
    0x04: (name=all_branches_ps) Counts all taken and not taken macro branches including far branches.(Precise Event)
626
 <br />
626
 <br />
627
    0x02: near_call_r3 Ring123 only near calls (non precise)
627
    0x02: (name=near_call_r3) Ring123 only near calls (non precise)
628
 <br />
628
 <br />
629
    0x02: near_call_r3_ps Ring123 only near calls (precise event)
629
    0x02: (name=near_call_r3_ps) Ring123 only near calls (precise event)
630
 <br />
630
 <br />
631
</td>
632
633
</tr>
631
</td>
634
632
633
</tr>
634
635
<tr><td>br_misp_retired</td><td>    Counts mispredicted branch instructions </td><td> 0, 1, 2, 3</td><td>
635
<tr><td>br_misp_retired</td><td>    Counts mispredicted branch instructions </td><td> all</td><td>
636
    0x01: conditional All mispredicted macro conditional branch instructions.
636
    0x01: (name=conditional) All mispredicted macro conditional branch instructions.
637
 <br />
637
 <br />
638
    0x02: near_call All macro direct and indirect near calls
638
    0x02: (name=near_call) All macro direct and indirect near calls
639
 <br />
639
 <br />
640
    0x10: not_taken number of branch instructions retired that were mispredicted and not-taken.
640
    0x10: (name=not_taken) number of branch instructions retired that were mispredicted and not-taken.
641
 <br />
641
 <br />
642
    0x20: taken number of branch instructions retired that were mispredicted and taken.
642
    0x20: (name=taken) number of branch instructions retired that were mispredicted and taken.
643
 <br />
643
 <br />
644
    0x04: all_branches_ps all macro branches (Precise Event)
644
    0x04: (name=all_branches_ps) all macro branches (Precise Event)
645
 <br />
645
 <br />
646
</td>
647
648
</tr>
646
</td>
649
647
648
</tr>
649
650
<tr><td>fp_assist</td><td>  Counts floating point assists </td><td> 0, 1, 2, 3</td><td>
650
<tr><td>fp_assist</td><td>  Counts floating point assists </td><td> all</td><td>
651
    0x1e: any Counts any FP_ASSIST umask was incrementing. (extra: cmask=1)
651
    0x1e: (name=any) Counts any FP_ASSIST umask was incrementing.
652
 <br />
652
 <br />
653
    0x02: x87_output output - Numeric Overflow, Numeric Underflow, Inexact Result
653
    0x02: (name=x87_output) output - Numeric Overflow, Numeric Underflow, Inexact Result
654
 <br />
654
 <br />
655
    0x04: x87_input input - Invalid Operation, Denormal Operand, SNaN Operand
655
    0x04: (name=x87_input) input - Invalid Operation, Denormal Operand, SNaN Operand
656
 <br />
656
 <br />
657
    0x08: simd_output Any output SSE* FP Assist - Numeric Overflow, Numeric Underflow.
657
    0x08: (name=simd_output) Any output SSE* FP Assist - Numeric Overflow, Numeric Underflow.
658
 <br />
658
 <br />
659
    0x10: simd_input Any input SSE* FP Assist
659
    0x10: (name=simd_input) Any input SSE* FP Assist
660
 <br />
660
 <br />
661
</td>
661
</td>
662
662
663
</tr>
663
</tr>
664
664
...
...
681
 <br />
681
 <br />
682
</td>
682
</td>
683
683
684
</tr>
684
</tr>
685
685
686
<tr><td>mem_uops_retired</td><td>   Count uops with memory accessed retired </td><td> 0, 1, 2, 3</td><td>
686
<tr><td>mem_uops_retired</td><td>   Count uops with memory accessed retired </td><td> all</td><td>
687
    0x11: stlb_miss_loads STLB misses dues to retired loads
687
    0x11: (name=stlb_miss_loads) STLB misses dues to retired loads
688
 <br />
688
 <br />
689
    0x12: stlb_miss_stores STLB misses dues to retired stores
689
    0x12: (name=stlb_miss_stores) STLB misses dues to retired stores
690
 <br />
690
 <br />
691
    0x21: lock_loads Locked retired loads
691
    0x21: (name=lock_loads) Locked retired loads
692
 <br />
692
 <br />
693
    0x41: split_loads Retired loads causing cacheline splits
693
    0x41: (name=split_loads) Retired loads causing cacheline splits
694
 <br />
694
 <br />
695
    0x42: split_stores Retired stores causing cacheline splits
695
    0x42: (name=split_stores) Retired stores causing cacheline splits
696
 <br />
696
 <br />
697
    0x81: all_loads Any retired loads
697
    0x81: (name=all_loads) Any retired loads
698
 <br />
698
 <br />
699
    0x82: all_stores Any retired stores
699
    0x82: (name=all_stores) Any retired stores
700
 <br />
700
 <br />
701
</td>
702
703
</tr>
701
</td>
704
702
703
</tr>
704
705
<tr><td>mem_load_uops_retired</td><td>  Memory load uops. </td><td> 0, 1, 2, 3</td><td>
705
<tr><td>mem_load_uops_retired</td><td>  Memory load uops. </td><td> all</td><td>
706
    0x01: l1_hit Load hit in nearest-level (L1D) cache
706
    0x01: (name=l1_hit) Load hit in nearest-level (L1D) cache
707
 <br />
707
 <br />
708
    0x02: l2_hit Load hit in mid-level (L2) cache
708
    0x02: (name=l2_hit) Load hit in mid-level (L2) cache
709
 <br />
709
 <br />
710
    0x04: llc_hit Load hit in last-level (L3) cache with no snoop needed
710
    0x04: (name=llc_hit) Load hit in last-level (L3) cache with no snoop needed
711
 <br />
711
 <br />
712
    0x40: hit_lfb A load missed L1D but hit the Fill Buffer
712
    0x40: (name=hit_lfb) A load missed L1D but hit the Fill Buffer
713
 <br />
713
 <br />
714
</td>
715
716
</tr>
714
</td>
717
715
716
</tr>
717
718
<tr><td>mem_load_uops_llc_hit_retired</td><td>  Memory load uops with LLC (Last level cache) hit </td><td> 0, 1, 2, 3</td><td>
718
<tr><td>mem_load_uops_llc_hit_retired</td><td>  Memory load uops with LLC (Last level cache) hit </td><td> all</td><td>
719
    0x01: xsnp_miss Load LLC Hit and a cross-core Snoop missed in on-pkg core cache
719
    0x01: (name=xsnp_miss) Load LLC Hit and a cross-core Snoop missed in on-pkg core cache
720
 <br />
720
 <br />
721
    0x02: xsnp_hit Load LLC Hit and a cross-core Snoop hits in on-pkg core cache
721
    0x02: (name=xsnp_hit) Load LLC Hit and a cross-core Snoop hits in on-pkg core cache
722
 <br />
722
 <br />
723
    0x04: xsnp_hitm Load had HitM Response from a core on same socket (shared LLC).
723
    0x04: (name=xsnp_hitm) Load had HitM Response from a core on same socket (shared LLC).
724
 <br />
724
 <br />
725
    0x08: xsnp_none Load hit in last-level (L3) cache with no snoop needed.
725
    0x08: (name=xsnp_none) Load hit in last-level (L3) cache with no snoop needed.
726
 <br />
726
 <br />
727
</td>
728
729
</tr>
727
</td>
730
728
729
</tr>
730
731
<tr><td>mem_load_uops_misc_retired</td><td> Memory load uops retired </td><td> 0, 1, 2, 3</td><td>
731
<tr><td>mem_load_uops_misc_retired</td><td> Memory load uops retired </td><td> all</td><td>
732
    0x02: No unit mask
732
    0x02: No unit mask
733
 <br />
733
 <br />
734
</td>
734
</td>
735
735
736
</tr>
736
</tr>
737
737
738
<tr><td>l2_trans</td><td>   L2 cache accesses </td><td> all</td><td>
738
<tr><td>l2_trans</td><td>   L2 cache accesses </td><td> all</td><td>
739
    0x80: all_requests Transactions accessing L2 pipe
739
    0x80: (name=all_requests) Transactions accessing L2 pipe
740
 <br />
740
 <br />
741
    0x01: demand_data_rd Demand Data Read requests that access L2 cache, includes L1D prefetches.
741
    0x01: (name=demand_data_rd) Demand Data Read requests that access L2 cache, includes L1D prefetches.
742
 <br />
742
 <br />
743
    0x02: rfo RFO requests that access L2 cache
743
    0x02: (name=rfo) RFO requests that access L2 cache
744
 <br />
744
 <br />
745
    0x04: code_rd L2 cache accesses when fetching instructions including L1D code prefetches
745
    0x04: (name=code_rd) L2 cache accesses when fetching instructions including L1D code prefetches
746
 <br />
746
 <br />
747
    0x08: all_pf L2 or LLC HW prefetches that access L2 cache
747
    0x08: (name=all_pf) L2 or LLC HW prefetches that access L2 cache
748
 <br />
748
 <br />
749
    0x10: l1d_wb L1D writebacks that access L2 cache
749
    0x10: (name=l1d_wb) L1D writebacks that access L2 cache
750
 <br />
750
 <br />
751
    0x20: l2_fill L2 fill requests that access L2 cache
751
    0x20: (name=l2_fill) L2 fill requests that access L2 cache
752
 <br />
752
 <br />
753
    0x40: l2_wb L2 writebacks that access L2 cache
753
    0x40: (name=l2_wb) L2 writebacks that access L2 cache
754
 <br />
754
 <br />
755
</td>
755
</td>
756
756
757
</tr>
757
</tr>
758
758
759
<tr><td>l2_lines_in</td><td>    L2 cache lines in </td><td> all</td><td>
759
<tr><td>l2_lines_in</td><td>    L2 cache lines in </td><td> all</td><td>
760
    0x07: all L2 cache lines filling L2
760
    0x07: (name=all) L2 cache lines filling L2
761
 <br />
761
 <br />
762
    0x01: i L2 cache lines in I state filling L2
762
    0x01: (name=i) L2 cache lines in I state filling L2
763
 <br />
763
 <br />
764
    0x02: s L2 cache lines in S state filling L2
764
    0x02: (name=s) L2 cache lines in S state filling L2
765
 <br />
765
 <br />
766
    0x04: e L2 cache lines in E state filling L2
766
    0x04: (name=e) L2 cache lines in E state filling L2
767
 <br />
767
 <br />
768
</td>
768
</td>
769
769
770
</tr>
770
</tr>
771
771
772
<tr><td>l2_lines_out</td><td>   L2 cache lines out </td><td> all</td><td>
772
<tr><td>l2_lines_out</td><td>   L2 cache lines out </td><td> all</td><td>
773
    0x01: demand_clean Clean line evicted by a demand
773
    0x01: (name=demand_clean) Clean line evicted by a demand
774
 <br />
774
 <br />
775
    0x02: demand_dirty Dirty line evicted by a demand
775
    0x02: (name=demand_dirty) Dirty line evicted by a demand
776
 <br />
776
 <br />
777
    0x04: pf_clean Clean line evicted by an L2 Prefetch
777
    0x04: (name=pf_clean) Clean line evicted by an L2 Prefetch
778
 <br />
778
 <br />
779
    0x08: pf_dirty Dirty line evicted by an L2 Prefetch
779
    0x08: (name=pf_dirty) Dirty line evicted by an L2 Prefetch
780
 <br />
780
 <br />
781
    0x0a: dirty_all Any Dirty line evicted
781
    0x0a: (name=dirty_all) Any Dirty line evicted
782
 <br />
782
 <br />
783
</td>
783
</td>
784
784
785
</tr>
785
</tr>
786
786

Get latest updates about Open Source Projects, Conferences and News.

Sign up for the SourceForge newsletter:





No, thanks