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<tr><td>CPU_CLK_UNHALTED</td><td>	Clock cycles when not halted </td><td> all</td><td>
</td>

</tr>

<tr><td>UNHALTED_REFERENCE_CYCLES</td><td>	Unhalted reference cycles </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>INST_RETIRED</td><td>	number of instructions retired </td><td> all</td><td>
</td>

</tr>

<tr><td>LLC_MISSES</td><td>	Last level cache demand requests from this core that missed the LLC </td><td> all</td><td>
	0x41: No unit mask
 <br />
</td>

</tr>

<tr><td>LLC_REFS</td><td>	Last level cache demand requests from this core </td><td> all</td><td>
	0x4f: No unit mask
 <br />
</td>

</tr>

<tr><td>BR_INST_RETIRED</td><td>	number of branch instructions retired </td><td> all</td><td>
</td>

</tr>

<tr><td>BR_MISS_PRED_RETIRED</td><td>	number of mispredicted branches retired (precise) </td><td> all</td><td>
</td>

</tr>

<tr><td>ld_blocks</td><td>	blocked loads </td><td> all</td><td>
	0x01: (name=data_unknown) blocked loads due to store buffer blocks with unknown data.
 <br />
	0x02: (name=store_forward) loads blocked by overlapping with store buffer that cannot be forwarded
 <br />
	0x08: (name=no_sr) This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.
 <br />
	0x10: (name=all_block) Number of cases where any load is blocked but has no DCU miss.
 <br />
</td>

</tr>

<tr><td>misalign_mem_ref</td><td>	Misaligned memory references </td><td> all</td><td>
	0x01: (name=loads) Speculative cache-line split load uops dispatched to the L1D.
 <br />
	0x02: (name=stores) Speculative cache-line split Store-address uops dispatched to L1D
 <br />
</td>

</tr>

<tr><td>ld_blocks_partial</td><td>	Partial loads </td><td> all</td><td>
	0x01: (name=address_alias) False dependencies in MOB due to partial compare on address
 <br />
	0x08: (name=all_sta_block) This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.
 <br />
</td>

</tr>

<tr><td>dtlb_load_misses</td><td>	D-TLB misses </td><td> all</td><td>
	0x01: (name=miss_causes_a_walk) Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G)
 <br />
	0x02: (name=walk_completed) Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G)
 <br />
	0x04: (name=walk_duration) Cycles PMH is busy with this walk
 <br />
	0x10: (name=stlb_hit) First level miss but second level hit; no page walk.
 <br />
</td>

</tr>

<tr><td>int_misc</td><td>	Instruction decoder events </td><td> all</td><td>
	0x40: (name=rat_stall_cycles) Cycles Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for this thread.
 <br />
	0x03: (name=recovery_cycles) Number of cycles waiting to be recover after Nuke due to all other cases except JEClear.
 <br />
	0x03: (name=recovery_stalls_count) Edge applied to recovery_cycles, thus counts occurrences.
 <br />
</td>

</tr>

<tr><td>uops_issued</td><td>	Number of Uops issued </td><td> all</td><td>
	0x01: (name=any) Number of Uops issued by the Resource Allocation Table (RAT) to the Reservation Station (RS)
 <br />
	0x01: (name=stall_cycles) cycles no uops issued by this thread.
 <br />
</td>

</tr>

<tr><td>arith</td><td>	Misc ALU events </td><td> all</td><td>
	0x01: (name=fpu_div_active) Cycles that the divider is busy with any divide or sqrt operation.
 <br />
	0x01: (name=fpu_div) Number of times that the divider is actived, includes INT, SIMD and FP.
 <br />
</td>

</tr>

<tr><td>insts_written_to_iq</td><td>	Number of instructions written to Instruction Queue (IQ) this cycle. </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>l2_rqsts</td><td>	Requests from L2 cache </td><td> all</td><td>
	0x01: (name=demand_data_rd_hit) Demand Data Read hit L2, no rejects
 <br />
	0x04: (name=rfo_hit) RFO requests that hit L2 cache
 <br />
	0x08: (name=rfo_miss) RFO requests that miss L2 cache
 <br />
	0x10: (name=code_rd_hit) L2 cache hits when fetching instructions, code reads.
 <br />
	0x20: (name=code_rd_miss) L2 cache misses when fetching instructions
 <br />
	0x40: (name=pf_hit) Requests from the L2 hardware prefetchers that hit L2 cache
 <br />
	0x80: (name=pf_miss) Requests from the L2 hardware prefetchers that miss L2 cache
 <br />
	0x03: (name=all_demand_data_rd) Any data read request to L2 cache
 <br />
	0x0c: (name=all_rfo) Any data RFO request to L2 cache
 <br />
	0x30: (name=all_code_rd) Any code read request to L2 cache
 <br />
	0xc0: (name=all_pf) Any L2 HW prefetch request to L2 cache
 <br />
</td>

</tr>

<tr><td>l2_store_lock_rqsts</td><td>	L2 cache store lock requests </td><td> all</td><td>
	0x0f: (name=all) RFOs that access cache lines in any state
 <br />
	0x01: (name=miss) RFO (as a result of regular RFO or Lock request) miss cache - I state
 <br />
	0x04: (name=hit_e) RFO (as a result of regular RFO or Lock request) hits cache in E state
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	0x08: (name=hit_m) RFO (as a result of regular RFO or Lock request) hits cache in M state
 <br />
</td>

</tr>

<tr><td>l2_l1d_wb_rqsts</td><td>	writebacks from L1D to the L2 cache </td><td> all</td><td>
	0x04: (name=hit_e) writebacks from L1D to L2 cache lines in E state
 <br />
	0x08: (name=hit_m) writebacks from L1D to L2 cache lines in M state
 <br />
</td>

</tr>

<tr><td>l1d_pend_miss</td><td>	Cycles with L1D load Misses outstanding. </td><td> 2</td><td>
	0x01: (name=pending) Cycles with L1D load Misses outstanding.
 <br />
	0x01: (name=occurences) This event counts the number of L1D misses outstanding occurences.
 <br />
</td>

</tr>

<tr><td>dtlb_store_misses</td><td>	D-TLB store misses </td><td> all</td><td>
	0x01: (name=miss_causes_a_walk) Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G)
 <br />
	0x02: (name=walk_completed) Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G)
 <br />
	0x04: (name=walk_duration) Cycles PMH is busy with this walk
 <br />
	0x10: (name=stlb_hit) First level miss but second level hit; no page walk. Only relevant if multiple levels.
 <br />
</td>

</tr>

<tr><td>load_hit_pre</td><td>	Load dispatches that hit fill buffer </td><td> all</td><td>
	0x01: (name=sw_pf) Load dispatches that hit fill buffer allocated for S/W prefetch.
 <br />
	0x02: (name=hw_pf) Load dispatches that hit fill buffer allocated for HW prefetch.
 <br />
</td>

</tr>

<tr><td>hw_pre_req</td><td>	Hardware Prefetch requests </td><td> all</td><td>
	0x02: No unit mask
 <br />
</td>

</tr>

<tr><td>l1d</td><td>	L1D cache events </td><td> all</td><td>
	0x01: (name=replacement) L1D Data line replacements.
 <br />
	0x02: (name=allocated_in_m) L1D M-state Data Cache Lines Allocated
 <br />
	0x04: (name=eviction) L1D M-state Data Cache Lines Evicted due to replacement (only)
 <br />
	0x08: (name=all_m_replacement) All Modified lines evicted out of L1D
 <br />
</td>

</tr>

<tr><td>partial_rat_stalls</td><td>	Partial RAT stalls </td><td> all</td><td>
	0x20: (name=flags_merge_uop) Number of perf sensitive flags-merge uops added by Sandy Bridge u-arch.
 <br />
	0x40: (name=slow_lea_window) Number of cycles with at least 1 slow Load Effective Address (LEA) uop being allocated.
 <br />
	0x80: (name=mul_single_uop) Number of Multiply packed/scalar single precision uops allocated
 <br />
	0x20: (name=flags_merge_uop_cycles) Cycles with perf sensitive flags-merge uops added by SandyBridge u-arch.
 <br />
</td>

</tr>

<tr><td>resource_stalls2</td><td>	Misc resource stalls </td><td> all</td><td>
	0x40: (name=bob_full) Cycles Allocator is stalled due Branch Order Buffer (BOB).
 <br />
	0x0f: (name=all_prf_control) Resource stalls2 control structures full for physical registers
 <br />
	0x0c: (name=all_fl_empty) Cycles with either free list is empty
 <br />
	0x4f: (name=ooo_rsrc) Resource stalls2 control structures full Physical Register Reclaim Table (PRRT), Physical History Table (PHT), INT or SIMD Free List (FL), Branch Order Buffer (BOB)
 <br />
</td>

</tr>

<tr><td>cpl_cycles</td><td>	Unhalted core cycles in specific rings </td><td> all</td><td>
	0x01: (name=ring0) Unhalted core cycles the Thread was in Rings 0.
 <br />
	0x01: (name=ring0_trans) Transitions from ring123 to Ring0.
 <br />
	0x02: (name=ring123) Unhalted core cycles the Thread was in Rings 1/2/3.
 <br />
</td>

</tr>

<tr><td>rs_events</td><td>	Events for the reservation station </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>offcore_requests_outstanding</td><td>	Offcore outstanding transactions </td><td> all</td><td>
	0x01: (name=demand_data_rd) Offcore outstanding Demand Data Read transactions in the SuperQueue (SQ), queue to uncore, every cycle. Includes L1D data hardware prefetches.
 <br />
	0x01: (name=cycles_with_demand_data_rd) cycles there are Offcore outstanding RD data transactions in the SuperQueue (SQ), queue to uncore.
 <br />
	0x02: (name=demand_code_rd) Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.
 <br />
	0x04: (name=demand_rfo) Offcore outstanding RFO (store) transactions in the SuperQueue (SQ), queue to uncore, every cycle.
 <br />
	0x08: (name=all_data_rd) Offcore outstanding all cacheable Core Data Read transactions in the SuperQueue (SQ), queue to uncore, every cycle.
 <br />
	0x08: (name=cycles_with_data_rd) Cycles there are Offcore outstanding all Data read transactions in the SuperQueue (SQ), queue to uncore, every cycle.
 <br />
	0x02: (name=cycles_with_demand_code_rd) Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.
 <br />
	0x04: (name=cycles_with_demand_rfo) Cycles with offcore outstanding demand RFO Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.
 <br />
</td>

</tr>

<tr><td>lock_cycles</td><td>	Cycles due to LOCK prefixes. </td><td> all</td><td>
	0x01: (name=split_lock_uc_lock_duration) Cycles in which the L1D and L2 are locked, due to a UC lock or split lock
 <br />
	0x02: (name=cache_lock_duration) cycles that theL1D is locked
 <br />
</td>

</tr>

<tr><td>idq</td><td>	Instruction Decode Queue events </td><td> all</td><td>
	0x02: (name=empty) Cycles the Instruction Decode Queue (IDQ) is empty.
 <br />
	0x04: (name=mite_uops) Number of uops delivered to Instruction Decode Queue (IDQ) from MITE path.
 <br />
	0x08: (name=dsb_uops) Number of uops delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.
 <br />
	0x10: (name=ms_dsb_uops) Number of Uops delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB).
 <br />
	0x20: (name=ms_mite_uops) Number of Uops delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by MITE.
 <br />
	0x30: (name=ms_uops) Number of Uops were delivered into Instruction Decode Queue (IDQ) from MS, initiated by Decode Stream Buffer (DSB) or MITE.
 <br />
	0x30: (name=ms_cycles) Number of cycles that Uops were delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB) or MITE.
 <br />
	0x04: (name=mite_cycles) Cycles MITE is active
 <br />
	0x08: (name=dsb_cycles) Cycles Decode Stream Buffer (DSB) is active
 <br />
	0x10: (name=ms_dsb_cycles) Cycles Decode Stream Buffer (DSB) Microcode Sequenser (MS) is active
 <br />
	0x10: (name=ms_dsb_occur) Occurences of Decode Stream Buffer (DSB) Microcode Sequenser (MS) going active
 <br />
	0x18: (name=all_dsb_cycles_any_uops) Cycles Decode Stream Buffer (DSB) is delivering anything
 <br />
	0x18: (name=all_dsb_cycles_4_uops) Cycles Decode Stream Buffer (DSB) is delivering 4 Uops
 <br />
	0x24: (name=all_mite_cycles_any_uops) Cycles MITE is delivering anything
 <br />
	0x24: (name=all_mite_cycles_4_uops) Cycles MITE is delivering 4 Uops
 <br />
	0x3c: (name=mite_all_uops) Number of uops delivered to Instruction Decode Queue (IDQ) from any path.
 <br />
</td>

</tr>

<tr><td>icache</td><td>	Instruction cache events </td><td> all</td><td>
	0x02: No unit mask
 <br />
</td>

</tr>

<tr><td>itlb_misses</td><td>	I-TLB misses </td><td> all</td><td>
	0x01: (name=miss_causes_a_walk) Miss in all TLB levels causes an page walk of any page size (4K/2M/4M)
 <br />
	0x02: (name=walk_completed) Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M)
 <br />
	0x04: (name=walk_duration) Cycles PMH is busy with this walk.
 <br />
	0x10: (name=stlb_hit) First level miss but second level hit; no page walk.
 <br />
</td>

</tr>

<tr><td>ild_stall</td><td>	Instruction decoding stalls </td><td> all</td><td>
	0x01: (name=lcp) Stall "occurrences" due to length changing prefixes (LCP).
 <br />
	0x04: (name=iq_full) Stall cycles when instructions cannot be written because the Instruction Queue (IQ) is full.
 <br />
</td>

</tr>

<tr><td>br_inst_exec</td><td>	Branch instructions </td><td> all</td><td>
	0xff: (name=all_branches) All branch instructions executed.
 <br />
	0x41: (name=nontaken_conditional) All macro conditional nontaken branch instructions.
 <br />
	0x81: (name=taken_conditional) All macro conditional taken branch instructions.
 <br />
	0x82: (name=taken_direct_jump) All macro unconditional taken branch instructions, excluding calls and indirects.
 <br />
	0x84: (name=taken_indirect_jump_non_call_ret) All taken indirect branches that are not calls nor returns.
 <br />
	0x88: (name=taken_indirect_near_return) All taken indirect branches that have a return mnemonic.
 <br />
	0x90: (name=taken_direct_near_call) All taken non-indirect calls.
 <br />
	0xa0: (name=taken_indirect_near_call) All taken indirect calls, including both register and memory indirect.
 <br />
	0xc1: (name=all_conditional) All macro conditional branch instructions.
 <br />
	0xc2: (name=all_direct_jmp) All macro unconditional branch instructions, excluding calls and indirects
 <br />
	0xc4: (name=all_indirect_jump_non_call_ret) All indirect branches that are not calls nor returns.
 <br />
	0xc8: (name=all_indirect_near_return) All indirect return branches.
 <br />
	0xd0: (name=all_direct_near_call) All non-indirect calls executed.
 <br />
</td>

</tr>

<tr><td>br_misp_exec</td><td>	Mispredicted branch instructions </td><td> all</td><td>
	0xff: (name=all_branches) All mispredicted branch instructions executed.
 <br />
	0x41: (name=nontaken_conditional) All nontaken mispredicted macro conditional branch instructions.
 <br />
	0x81: (name=taken_conditional) All taken mispredicted macro conditional branch instructions.
 <br />
	0x84: (name=taken_indirect_jump_non_call_ret) All taken mispredicted indirect branches that are not calls nor returns.
 <br />
	0x88: (name=taken_return_near) All taken mispredicted indirect branches that have a return mnemonic.
 <br />
	0x90: (name=taken_direct_near_call) All taken mispredicted non-indirect calls.
 <br />
	0xa0: (name=taken_indirect_near_call) All taken mispredicted indirect calls, including both register and memory indirect.
 <br />
	0xc1: (name=all_conditional) All mispredicted macro conditional branch instructions.
 <br />
	0xc4: (name=all_indirect_jump_non_call_ret) All mispredicted indirect branches that are not calls nor returns.
 <br />
	0xd0: (name=all_direct_near_call) All mispredicted non-indirect calls
 <br />
</td>

</tr>

<tr><td>idq_uops_not_delivered</td><td>	uops not delivered to IDQ. </td><td> all</td><td>
	0x01: (name=core) Count number of non-delivered uops to Resource Allocation Table (RAT).
 <br />
	0x01: (name=cycles_0_uops_deliv.core) Counts the cycles no uops were delivered
 <br />
	0x01: (name=cycles_le_1_uop_deliv.core) Counts the cycles less than 1 uops were delivered
 <br />
	0x01: (name=cycles_le_2_uop_deliv.core) Counts the cycles less than 2 uops were delivered
 <br />
	0x01: (name=cycles_le_3_uop_deliv.core) Counts the cycles less than 3 uops were delivered
 <br />
	0x01: (name=cycles_ge_1_uop_deliv.core) Cycles when 1 or more uops were delivered to the by the front end.
 <br />
	0x01: (name=cycles_fe_was_ok) Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.
 <br />
</td>

</tr>

<tr><td>uops_dispatched_port</td><td>	Count on which ports uops are dispatched. </td><td> all</td><td>
	0x01: (name=port_0) Cycles which a Uop is dispatched on port 0
 <br />
	0x02: (name=port_1) Cycles which a Uop is dispatched on port 1
 <br />
	0x04: (name=port_2_ld) Cycles which a load Uop is dispatched on port 2
 <br />
	0x08: (name=port_2_sta) Cycles which a STA Uop is dispatched on port 2
 <br />
	0x10: (name=port_3_ld) Cycles which a load Uop is dispatched on port 3
 <br />
	0x20: (name=port_3_sta) Cycles which a STA Uop is dispatched on port 3
 <br />
	0x40: (name=port_4) Cycles which a Uop is dispatched on port 4
 <br />
	0x80: (name=port_5) Cycles which a Uop is dispatched on port 5
 <br />
	0x0c: (name=port_2) Uops disptached to port 2, loads and stores (speculative and retired)
 <br />
	0x30: (name=port_3) Uops disptached to port 3, loads and stores (speculative and retired)
 <br />
	0x0c: (name=port_2_core) Uops disptached to port 2, loads and stores per core (speculative and retired)
 <br />
	0x30: (name=port_3_core) Uops disptached to port 3, loads and stores per core (speculative and retired)
 <br />
</td>

</tr>

<tr><td>resource_stalls</td><td>	Core resource stalls </td><td> all</td><td>
	0x01: (name=any) Cycles Allocation is stalled due to Resource Related reason.
 <br />
	0x02: (name=lb) Cycles Allocator is stalled due to Load Buffer full
 <br />
	0x04: (name=rs) Stall due to no eligible Reservation Station (RS) entry available.
 <br />
	0x08: (name=sb) Cycles Allocator is stalled due to Store Buffer full (not including draining from synch).
 <br />
	0x10: (name=rob) ROB full cycles.
 <br />
	0x0e: (name=mem_rs) Resource stalls due to LB, SB or Reservation Station (RS) being completely in use
 <br />
	0xf0: (name=ooo_rsrc) Resource stalls due to Rob being full, FCSW, MXCSR and OTHER
 <br />
	0x0a: (name=lb_sb) Resource stalls due to load or store buffers
 <br />
</td>

</tr>

<tr><td>dsb2mite_switches</td><td>	Number of Decode Stream Buffer (DSB) to MITE switches </td><td> all</td><td>
	0x01: (name=count) Number of Decode Stream Buffer (DSB) to MITE switches
 <br />
	0x02: (name=penalty_cycles) Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.
 <br />
</td>

</tr>

<tr><td>dsb_fill</td><td>	DSB fill events </td><td> all</td><td>
	0x02: (name=other_cancel) Count number of times a valid DSB fill has been actually cancelled for any reason.
 <br />
	0x08: (name=exceed_dsb_lines) Decode Stream Buffer (DSB) Fill encountered > 3 Decode Stream Buffer (DSB) lines.
 <br />
	0x0a: (name=all_cancel) Count number of times a valid Decode Stream Buffer (DSB) fill has been actually cancelled for any reason.
 <br />
</td>

</tr>

<tr><td>itlb</td><td>	ITLB events </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>offcore_requests</td><td>	Requests sent outside the core </td><td> all</td><td>
	0x01: (name=demand_data_rd) Demand Data Read requests sent to uncore
 <br />
	0x02: (name=demand_code_rd) Offcore Code read requests. Includes Cacheable and Un-cacheables.
 <br />
	0x04: (name=demand_rfo) Offcore Demand RFOs. Includes regular RFO, Locks, ItoM.
 <br />
	0x08: (name=all_data_rd) Offcore Demand and prefetch data reads returned to the core.
 <br />
</td>

</tr>

<tr><td>uops_dispatched</td><td>	uops dispatched </td><td> all</td><td>
	0x01: (name=thread) Counts total number of uops to be dispatched per-thread each cycle.
 <br />
	0x01: (name=stall_cycles) Counts number of cycles no uops were dispatced to be executed on this thread.
 <br />
	0x02: (name=core) Counts total number of uops dispatched from any thread
 <br />
</td>

</tr>

<tr><td>offcore_requests_buffer</td><td>	Offcore requests buffer events </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>agu_bypass_cancel</td><td>	AGU bypass cancel </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>tlb_flush</td><td>	TLB flushes </td><td> all</td><td>
	0x01: (name=dtlb_thread) Count number of DTLB flushes of thread-specific entries.
 <br />
	0x20: (name=stlb_any) Count number of any STLB flushes
 <br />
</td>

</tr>

<tr><td>l1d_blocks</td><td>	L1D cache blocking events </td><td> all</td><td>
	0x01: (name=ld_bank_conflict) Any dispatched loads cancelled due to DCU bank conflict
 <br />
	0x05: (name=bank_conflict_cycles) Cycles with l1d blocks due to bank conflicts
 <br />
</td>

</tr>

<tr><td>inst_retired</td><td>	Instructions retired </td><td> 1</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>other_assists</td><td>	Instructions that needed an assist </td><td> all</td><td>
	0x02: (name=itlb_miss_retired) Instructions that experienced an ITLB miss. Non Pebs
 <br />
	0x10: (name=avx_to_sse) Number of transitions from AVX-256 to legacy SSE when penalty applicable Non Pebs
 <br />
	0x20: (name=sse_to_avx) Number of transitions from legacy SSE to AVX-256 when penalty applicable Non Pebs
 <br />
</td>

</tr>

<tr><td>uops_retired</td><td>	uops that actually retired. </td><td> all</td><td>
	0x01: (name=all) All uops that actually retired.
 <br />
	0x02: (name=retire_slots) number of retirement slots used non PEBS
 <br />
	0x01: (name=stall_cycles) Cycles no executable uops retired
 <br />
	0x01: (name=total_cycles) Number of cycles using always true condition applied to non PEBS uops retired event.
 <br />
</td>

</tr>

<tr><td>machine_clears</td><td>	Number of Machine Clears detected. </td><td> all</td><td>
	0x02: (name=memory_ordering) Number of Memory Ordering Machine Clears detected.
 <br />
	0x04: (name=smc) Number of Self-modifying code (SMC) Machine Clears detected.
 <br />
	0x20: (name=maskmov) Number of AVX masked mov Machine Clears detected.
 <br />
</td>

</tr>

<tr><td>br_inst_retired</td><td>	Counts branch instructions retired </td><td> all</td><td>
	0x01: (name=conditional) Counts all taken and not taken macro conditional branch instructions.
 <br />
	0x02: (name=near_call) Counts all macro direct and indirect near calls. non PEBS
 <br />
	0x08: (name=near_return) This event counts the number of near ret instructions retired.
 <br />
	0x10: (name=not_taken) Counts all not taken macro branch instructions retired.
 <br />
	0x20: (name=near_taken) Counts the number of near branch taken instructions retired.
 <br />
	0x40: (name=far_branch) Counts the number of far branch instructions retired.
 <br />
	0x04: (name=all_branches_ps) Counts all taken and not taken macro branches including far branches.(Precise Event)
 <br />
	0x02: (name=near_call_r3) Ring123 only near calls (non precise)
 <br />
	0x02: (name=near_call_r3_ps) Ring123 only near calls (precise event)
 <br />
</td>

</tr>

<tr><td>br_misp_retired</td><td>	Counts mispredicted branch instructions </td><td> all</td><td>
	0x01: (name=conditional) All mispredicted macro conditional branch instructions.
 <br />
	0x02: (name=near_call) All macro direct and indirect near calls
 <br />
	0x10: (name=not_taken) number of branch instructions retired that were mispredicted and not-taken.
 <br />
	0x20: (name=taken) number of branch instructions retired that were mispredicted and taken.
 <br />
	0x04: (name=all_branches_ps) all macro branches (Precise Event)
 <br />
</td>

</tr>

<tr><td>fp_assist</td><td>	Counts floating point assists </td><td> all</td><td>
	0x1e: (name=any) Counts any FP_ASSIST umask was incrementing.
 <br />
	0x02: (name=x87_output) output - Numeric Overflow, Numeric Underflow, Inexact Result
 <br />
	0x04: (name=x87_input) input - Invalid Operation, Denormal Operand, SNaN Operand
 <br />
	0x08: (name=simd_output) Any output SSE* FP Assist - Numeric Overflow, Numeric Underflow.
 <br />
	0x10: (name=simd_input) Any input SSE* FP Assist
 <br />
</td>

</tr>

<tr><td>hw_interrupts</td><td>	Number of hardware interrupts received by the processor. </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>rob_misc_events</td><td>	Count ROB (Register Reorder Buffer) events. </td><td> all</td><td>
	0x20: No unit mask
 <br />
</td>

</tr>

<tr><td>mem_trans_retired</td><td>	Count memory transactions </td><td> 3</td><td>
	0x02: No unit mask
 <br />
</td>

</tr>

<tr><td>mem_uops_retired</td><td>	Count uops with memory accessed retired </td><td> all</td><td>
	0x11: (name=stlb_miss_loads) STLB misses dues to retired loads
 <br />
	0x12: (name=stlb_miss_stores) STLB misses dues to retired stores
 <br />
	0x21: (name=lock_loads) Locked retired loads
 <br />
	0x41: (name=split_loads) Retired loads causing cacheline splits
 <br />
	0x42: (name=split_stores) Retired stores causing cacheline splits
 <br />
	0x81: (name=all_loads) Any retired loads
 <br />
	0x82: (name=all_stores) Any retired stores
 <br />
</td>

</tr>

<tr><td>mem_load_uops_retired</td><td>	Memory load uops. </td><td> all</td><td>
	0x01: (name=l1_hit) Load hit in nearest-level (L1D) cache
 <br />
	0x02: (name=l2_hit) Load hit in mid-level (L2) cache
 <br />
	0x04: (name=llc_hit) Load hit in last-level (L3) cache with no snoop needed
 <br />
	0x40: (name=hit_lfb) A load missed L1D but hit the Fill Buffer
 <br />
</td>

</tr>

<tr><td>mem_load_uops_llc_hit_retired</td><td>	Memory load uops with LLC (Last level cache) hit </td><td> all</td><td>
	0x01: (name=xsnp_miss) Load LLC Hit and a cross-core Snoop missed in on-pkg core cache
 <br />
	0x02: (name=xsnp_hit) Load LLC Hit and a cross-core Snoop hits in on-pkg core cache
 <br />
	0x04: (name=xsnp_hitm) Load had HitM Response from a core on same socket (shared LLC).
 <br />
	0x08: (name=xsnp_none) Load hit in last-level (L3) cache with no snoop needed.
 <br />
</td>

</tr>

<tr><td>mem_load_uops_misc_retired</td><td>	Memory load uops retired </td><td> all</td><td>
	0x02: No unit mask
 <br />
</td>

</tr>

<tr><td>l2_trans</td><td>	L2 cache accesses </td><td> all</td><td>
	0x80: (name=all_requests) Transactions accessing L2 pipe
 <br />
	0x01: (name=demand_data_rd) Demand Data Read requests that access L2 cache, includes L1D prefetches.
 <br />
	0x02: (name=rfo) RFO requests that access L2 cache
 <br />
	0x04: (name=code_rd) L2 cache accesses when fetching instructions including L1D code prefetches
 <br />
	0x08: (name=all_pf) L2 or LLC HW prefetches that access L2 cache
 <br />
	0x10: (name=l1d_wb) L1D writebacks that access L2 cache
 <br />
	0x20: (name=l2_fill) L2 fill requests that access L2 cache
 <br />
	0x40: (name=l2_wb) L2 writebacks that access L2 cache
 <br />
</td>

</tr>

<tr><td>l2_lines_in</td><td>	L2 cache lines in </td><td> all</td><td>
	0x07: (name=all) L2 cache lines filling L2
 <br />
	0x01: (name=i) L2 cache lines in I state filling L2
 <br />
	0x02: (name=s) L2 cache lines in S state filling L2
 <br />
	0x04: (name=e) L2 cache lines in E state filling L2
 <br />
</td>

</tr>

<tr><td>l2_lines_out</td><td>	L2 cache lines out </td><td> all</td><td>
	0x01: (name=demand_clean) Clean line evicted by a demand
 <br />
	0x02: (name=demand_dirty) Dirty line evicted by a demand
 <br />
	0x04: (name=pf_clean) Clean line evicted by an L2 Prefetch
 <br />
	0x08: (name=pf_dirty) Dirty line evicted by an L2 Prefetch
 <br />
	0x0a: (name=dirty_all) Any Dirty line evicted
 <br />
</td>

</tr>

<tr><td>sq_misc</td><td>	Store queue misc events </td><td> all</td><td>
	0x10: No unit mask
 <br />
</td>

</tr>

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