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<tr><td>CPU_CLK_UNHALTED</td><td>	Clock cycles when not halted </td><td> 0, 1</td><td>
	0x00: Unhalted core cycles
 <br />
	0x01: Unhalted bus cycles
 <br />
	0x02: Unhalted bus cycles of this core while the other core is halted
 <br />
</td>

</tr>

<tr><td>INST_RETIRED_ANY_P</td><td>	number of instructions retired </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>L2_RQSTS</td><td>	number of L2 cache requests </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x30: prefetch: all inclusive
 <br />
	0x10: prefetch: Hardware prefetch only
 <br />
	0x00: prefetch: exclude hardware prefetch
 <br />
	0x08: (M)ESI: Modified
 <br />
	0x04: M(E)SI: Exclusive
 <br />
	0x02: ME(S)I: Shared
 <br />
	0x01: MES(I): Invalid
 <br />
</td>

</tr>

<tr><td>LLC_MISSES</td><td>	L2 cache demand requests from this core that missed the L2 </td><td> 0, 1</td><td>
	0x41: No unit mask
 <br />
</td>

</tr>

<tr><td>LLC_REFS</td><td>	L2 cache demand requests from this core </td><td> 0, 1</td><td>
	0x4f: No unit mask
 <br />
</td>

</tr>

<tr><td>LOAD_BLOCK</td><td>	events pertaining to loads </td><td> 0, 1</td><td>
	0x02: (name=STA) Loads blocked by a preceding store with unknown address.
 <br />
	0x04: (name=STD) Loads blocked by a preceding store with unknown data.
 <br />
	0x08: (name=OVERLAP_STORE) Loads that partially overlap an earlier store, or 4K aliased with a previous store.
 <br />
	0x10: (name=UNTIL_RETIRE) Loads blocked until retirement.
 <br />
	0x20: (name=L1D) Loads blocked by the L1 data cache.
 <br />
</td>

</tr>

<tr><td>STORE_BLOCK</td><td>	events pertaining to stores </td><td> 0, 1</td><td>
	0x01: (name=SB_DRAIN_CYCLES) Cycles while stores are blocked due to store buffer drain.
 <br />
	0x02: (name=ORDER) Cycles while store is waiting for a preceding store to be globally observed.
 <br />
	0x08: (name=NOOP) A store is blocked due to a conflict with an external or internal snoop.
 <br />
</td>

</tr>

<tr><td>MISALIGN_MEM_REF</td><td>	number of misaligned data memory references </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>SEGMENT_REG_LOADS</td><td>	number of segment register loads </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>SSE_PRE_EXEC</td><td>	number of SSE pre-fetch/weakly ordered insns retired </td><td> 0, 1</td><td>
	0x00: prefetch NTA instructions executed.
 <br />
	0x01: prefetch T1 instructions executed.
 <br />
	0x02: prefetch T1 and T2 instructions executed.
 <br />
	0x03: SSE weakly-ordered stores
 <br />
</td>

</tr>

<tr><td>DTLB_MISSES</td><td>	DTLB miss events </td><td> 0, 1</td><td>
	0x01: (name=ANY) Memory accesses that missed the DTLB.
 <br />
	0x02: (name=MISS_LD) DTLB misses due to load operations.
 <br />
	0x04: (name=L0_MISS_LD) L0 DTLB misses due to load operations.
 <br />
	0x08: (name=MISS_ST) TLB misses due to store operations.
 <br />
</td>

</tr>

<tr><td>MEMORY_DISAMBIGUATION</td><td>	Memory disambiguation reset cycles. </td><td> 0, 1</td><td>
	0x01: (name=RESET) Memory disambiguation reset cycles.
 <br />
	0x02: (name=SUCCESS) Number of loads that were successfully disambiguated.
 <br />
</td>

</tr>

<tr><td>PAGE_WALKS</td><td>	Page table walk events </td><td> 0, 1</td><td>
	0x01: (name=COUNT) Number of page-walks executed.
 <br />
	0x02: (name=CYCLES) Duration of page-walks in core cycles.
 <br />
</td>

</tr>

<tr><td>FLOPS</td><td>	number of FP computational micro-ops executed </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>FP_ASSIST</td><td>	number of FP assists </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>MUL</td><td>	number of multiplies </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>DIV</td><td>	number of divides </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>CYCLES_DIV_BUSY</td><td>	cycles divider is busy </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>IDLE_DURING_DIV</td><td>	cycles divider is busy and all other execution units are idle. </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>DELAYED_BYPASS</td><td>	Delayed bypass events </td><td> 0, 1</td><td>
	0x00: (name=FP) Delayed bypass to FP operation.
 <br />
	0x01: (name=SIMD) Delayed bypass to SIMD operation.
 <br />
	0x02: (name=LOAD) Delayed bypass to load operation.
 <br />
</td>

</tr>

<tr><td>L2_ADS</td><td>	Cycles the L2 address bus is in use. </td><td> 0, 1</td><td>
	0xc0: All cores
 <br />
	0x40: This core
 <br />
</td>

</tr>

<tr><td>L2_DBUS_BUSY_RD</td><td>	Cycles the L2 transfers data to the core. </td><td> 0, 1</td><td>
	0xc0: All cores
 <br />
	0x40: This core
 <br />
</td>

</tr>

<tr><td>L2_LINES_IN</td><td>	number of allocated lines in L2 </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x30: prefetch: all inclusive
 <br />
	0x10: prefetch: Hardware prefetch only
 <br />
	0x00: prefetch: exclude hardware prefetch
 <br />
</td>

</tr>

<tr><td>L2_M_LINES_IN</td><td>	number of modified lines allocated in L2 </td><td> 0, 1</td><td>
	0xc0: All cores
 <br />
	0x40: This core
 <br />
</td>

</tr>

<tr><td>L2_LINES_OUT</td><td>	number of recovered lines from L2 </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x30: prefetch: all inclusive
 <br />
	0x10: prefetch: Hardware prefetch only
 <br />
	0x00: prefetch: exclude hardware prefetch
 <br />
</td>

</tr>

<tr><td>L2_M_LINES_OUT</td><td>	number of modified lines removed from L2 </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x30: prefetch: all inclusive
 <br />
	0x10: prefetch: Hardware prefetch only
 <br />
	0x00: prefetch: exclude hardware prefetch
 <br />
</td>

</tr>

<tr><td>L2_IFETCH</td><td>	number of L2 cacheable instruction fetches </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x08: (M)ESI: Modified
 <br />
	0x04: M(E)SI: Exclusive
 <br />
	0x02: ME(S)I: Shared
 <br />
	0x01: MES(I): Invalid
 <br />
</td>

</tr>

<tr><td>L2_LD</td><td>	number of L2 data loads </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x30: prefetch: all inclusive
 <br />
	0x10: prefetch: Hardware prefetch only
 <br />
	0x00: prefetch: exclude hardware prefetch
 <br />
	0x08: (M)ESI: Modified
 <br />
	0x04: M(E)SI: Exclusive
 <br />
	0x02: ME(S)I: Shared
 <br />
	0x01: MES(I): Invalid
 <br />
</td>

</tr>

<tr><td>L2_ST</td><td>	number of L2 data stores </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x08: (M)ESI: Modified
 <br />
	0x04: M(E)SI: Exclusive
 <br />
	0x02: ME(S)I: Shared
 <br />
	0x01: MES(I): Invalid
 <br />
</td>

</tr>

<tr><td>L2_LOCK</td><td>	number of locked L2 data accesses </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x08: (M)ESI: Modified
 <br />
	0x04: M(E)SI: Exclusive
 <br />
	0x02: ME(S)I: Shared
 <br />
	0x01: MES(I): Invalid
 <br />
</td>

</tr>

<tr><td>L2_REJECT_BUSQ</td><td>	Rejected L2 cache requests </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x30: prefetch: all inclusive
 <br />
	0x10: prefetch: Hardware prefetch only
 <br />
	0x00: prefetch: exclude hardware prefetch
 <br />
	0x08: (M)ESI: Modified
 <br />
	0x04: M(E)SI: Exclusive
 <br />
	0x02: ME(S)I: Shared
 <br />
	0x01: MES(I): Invalid
 <br />
</td>

</tr>

<tr><td>L2_NO_REQ</td><td>	Cycles no L2 cache requests are pending </td><td> 0, 1</td><td>
	0xc0: All cores
 <br />
	0x40: This core
 <br />
</td>

</tr>

<tr><td>EIST_TRANS_ALL</td><td>	Intel(tm) Enhanced SpeedStep(r) Technology transitions </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>THERMAL_TRIP</td><td>	Number of thermal trips </td><td> 0, 1</td><td>
	0xc0: No unit mask
 <br />
</td>

</tr>

<tr><td>L1D_CACHE_LD</td><td>	L1 cacheable data read operations </td><td> 0, 1</td><td>
	0x08: (M)ESI: Modified
 <br />
	0x04: M(E)SI: Exclusive
 <br />
	0x02: ME(S)I: Shared
 <br />
	0x01: MES(I): Invalid
 <br />
</td>

</tr>

<tr><td>L1D_CACHE_ST</td><td>	L1 cacheable data write operations </td><td> 0, 1</td><td>
	0x08: (M)ESI: Modified
 <br />
	0x04: M(E)SI: Exclusive
 <br />
	0x02: ME(S)I: Shared
 <br />
	0x01: MES(I): Invalid
 <br />
</td>

</tr>

<tr><td>L1D_CACHE_LOCK</td><td>	L1 cacheable lock read operations </td><td> 0, 1</td><td>
	0x08: (M)ESI: Modified
 <br />
	0x04: M(E)SI: Exclusive
 <br />
	0x02: ME(S)I: Shared
 <br />
	0x01: MES(I): Invalid
 <br />
</td>

</tr>

<tr><td>L1D_CACHE_LOCK_DURATION</td><td>	Duration of L1 data cacheable locked operations </td><td> 0, 1</td><td>
	0x10: No unit mask
 <br />
</td>

</tr>

<tr><td>L1D_ALL_REF</td><td>	All references to the L1 data cache </td><td> 0, 1</td><td>
	0x10: No unit mask
 <br />
</td>

</tr>

<tr><td>L1D_ALL_CACHE_REF</td><td>	L1 data cacheable reads and writes </td><td> 0, 1</td><td>
	0x02: No unit mask
 <br />
</td>

</tr>

<tr><td>L1D_REPL</td><td>	Cache lines allocated in the L1 data cache </td><td> 0, 1</td><td>
	0x0f: No unit mask
 <br />
</td>

</tr>

<tr><td>L1D_M_REPL</td><td>	Modified cache lines allocated in the L1 data cache </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>L1D_M_EVICT</td><td>	Modified cache lines evicted from the L1 data cache </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>L1D_PEND_MISS</td><td>	Total number of outstanding L1 data cache misses at any cycle </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>L1D_SPLIT</td><td>	Cache line split load/stores </td><td> 0, 1</td><td>
	0x01: split loads
 <br />
	0x02: split stores
 <br />
</td>

</tr>

<tr><td>SSE_PREF_MISS</td><td>	SSE instructions that missed all caches </td><td> 0, 1</td><td>
	0x00: PREFETCHNTA
 <br />
	0x01: PREFETCHT0
 <br />
	0x02: PREFETCHT1/PREFETCHT2
 <br />
</td>

</tr>

<tr><td>LOAD_HIT_PRE</td><td>	Load operations conflicting with a software prefetch to the same address </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>L1D_PREFETCH</td><td>	L1 data cache prefetch requests </td><td> 0, 1</td><td>
	0x10: No unit mask
 <br />
</td>

</tr>

<tr><td>BUS_REQ_OUTSTANDING</td><td>	Outstanding cacheable data read bus requests duration </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x00: bus: this agent
 <br />
	0x20: bus: include all agents
 <br />
</td>

</tr>

<tr><td>BUS_BNR_DRV</td><td>	Number of Bus Not Ready signals asserted </td><td> 0, 1</td><td>
	0x00: this agent
 <br />
	0x20: include all agents
 <br />
</td>

</tr>

<tr><td>BUS_DRDY_CLOCKS</td><td>	Bus cycles when data is sent on the bus </td><td> 0, 1</td><td>
	0x00: this agent
 <br />
	0x20: include all agents
 <br />
</td>

</tr>

<tr><td>BUS_LOCK_CLOCKS</td><td>	Bus cycles when a LOCK signal is asserted </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x00: bus: this agent
 <br />
	0x20: bus: include all agents
 <br />
</td>

</tr>

<tr><td>BUS_DATA_RCV</td><td>	Bus cycles while processor receives data </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x00: bus: this agent
 <br />
	0x20: bus: include all agents
 <br />
</td>

</tr>

<tr><td>BUS_TRAN_BRD</td><td>	Burst read bus transactions </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x00: bus: this agent
 <br />
	0x20: bus: include all agents
 <br />
</td>

</tr>

<tr><td>BUS_TRAN_RFO</td><td>	number of completed read for ownership transactions </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x00: bus: this agent
 <br />
	0x20: bus: include all agents
 <br />
</td>

</tr>

<tr><td>BUS_TRAN_WB</td><td>	number of explicit writeback bus transactions </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x00: bus: this agent
 <br />
	0x20: bus: include all agents
 <br />
</td>

</tr>

<tr><td>BUS_TRAN_IFETCH</td><td>	number of instruction fetch transactions </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x00: bus: this agent
 <br />
	0x20: bus: include all agents
 <br />
</td>

</tr>

<tr><td>BUS_TRAN_INVAL</td><td>	number of invalidate transactions </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x00: bus: this agent
 <br />
	0x20: bus: include all agents
 <br />
</td>

</tr>

<tr><td>BUS_TRAN_PWR</td><td>	number of partial write bus transactions </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x00: bus: this agent
 <br />
	0x20: bus: include all agents
 <br />
</td>

</tr>

<tr><td>BUS_TRANS_P</td><td>	number of partial bus transactions </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x00: bus: this agent
 <br />
	0x20: bus: include all agents
 <br />
</td>

</tr>

<tr><td>BUS_TRANS_IO</td><td>	number of I/O bus transactions </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x00: bus: this agent
 <br />
	0x20: bus: include all agents
 <br />
</td>

</tr>

<tr><td>BUS_TRANS_DEF</td><td>	number of completed defer transactions </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x00: bus: this agent
 <br />
	0x20: bus: include all agents
 <br />
</td>

</tr>

<tr><td>BUS_TRAN_BURST</td><td>	number of completed burst transactions </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x00: bus: this agent
 <br />
	0x20: bus: include all agents
 <br />
</td>

</tr>

<tr><td>BUS_TRAN_MEM</td><td>	number of completed memory transactions </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x00: bus: this agent
 <br />
	0x20: bus: include all agents
 <br />
</td>

</tr>

<tr><td>BUS_TRAN_ANY</td><td>	number of any completed bus transactions </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x00: bus: this agent
 <br />
	0x20: bus: include all agents
 <br />
</td>

</tr>

<tr><td>EXT_SNOOP</td><td>	External snoops </td><td> 0, 1</td><td>
	0x00: bus: this agent
 <br />
	0x20: bus: include all agents
 <br />
	0x08: snoop: HITM snoops
 <br />
	0x02: snoop: HIT snoops
 <br />
	0x01: snoop: CLEAN snoops
 <br />
</td>

</tr>

<tr><td>CMP_SNOOP</td><td>	L1 data cache is snooped by other core </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x01: snoop: CMP2I snoops
 <br />
	0x02: snoop: CMP2S snoops
 <br />
</td>

</tr>

<tr><td>BUS_HIT_DRV</td><td>	HIT signal asserted </td><td> 0, 1</td><td>
	0x00: this agent
 <br />
	0x20: include all agents
 <br />
</td>

</tr>

<tr><td>BUS_HITM_DRV</td><td>	HITM signal asserted </td><td> 0, 1</td><td>
	0x00: this agent
 <br />
	0x20: include all agents
 <br />
</td>

</tr>

<tr><td>BUSQ_EMPTY</td><td>	Bus queue is empty </td><td> 0, 1</td><td>
	0xc0: All cores
 <br />
	0x40: This core
 <br />
</td>

</tr>

<tr><td>SNOOP_STALL_DRV</td><td>	Bus stalled for snoops </td><td> 0, 1</td><td>
	0xc0: core: all cores
 <br />
	0x40: core: this core
 <br />
	0x00: bus: this agent
 <br />
	0x20: bus: include all agents
 <br />
</td>

</tr>

<tr><td>BUS_IO_WAIT</td><td>	IO requests waiting in the bus queue </td><td> 0, 1</td><td>
	0xc0: All cores
 <br />
	0x40: This core
 <br />
</td>

</tr>

<tr><td>L1I_READS</td><td>	number of instruction fetches </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>L1I_MISSES</td><td>	number of instruction fetch misses </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>ITLB</td><td>	number of ITLB misses </td><td> 0, 1</td><td>
	0x02: ITLB small page misses
 <br />
	0x10: ITLB large page misses
 <br />
	0x40: ITLB flushes
 <br />
</td>

</tr>

<tr><td>INST_QUEUE_FULL</td><td>	cycles during which the instruction queue is full </td><td> 0, 1</td><td>
	0x02: No unit mask
 <br />
</td>

</tr>

<tr><td>IFU_MEM_STALL</td><td>	cycles instruction fetch pipe is stalled </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>ILD_STALL</td><td>	cycles instruction length decoder is stalled </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>BR_INST_EXEC</td><td>	Branch instructions executed (not necessarily retired) </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>BR_MISSP_EXEC</td><td>	Branch instructions executed that were mispredicted at execution </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>BR_BAC_MISSP_EXEC</td><td>	Branch instructions executed that were mispredicted at Front End (BAC) </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>BR_CND_EXEC</td><td>	Conditional Branch instructions executed </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>BR_CND_MISSP_EXEC</td><td>	Conditional Branch instructions executed that were mispredicted </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>BR_IND_EXEC</td><td>	Indirect Branch instructions executed </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>BR_IND_MISSP_EXEC</td><td>	Indirect Branch instructions executed that were mispredicted </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>BR_RET_EXEC</td><td>	Return Branch instructions executed </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>BR_RET_MISSP_EXEC</td><td>	Return Branch instructions executed that were mispredicted at Execution </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>BR_RET_BAC_MISSP_EXEC</td><td>	Branch instructions executed that were mispredicted at Front End (BAC) </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>BR_CALL_EXEC</td><td>	CALL instruction executed </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>BR_CALL_MISSP_EXEC</td><td>	CALL instruction executed and miss predicted </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>BR_IND_CALL_EXEC</td><td>	Indirect CALL instruction executed </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>BR_TKN_BUBBLE_1</td><td>	Branch predicted taken with bubble 1 </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>BR_TKN_BUBBLE_2</td><td>	Branch predicted taken with bubble 2 </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>RS_UOPS_DISPATCHED</td><td>	Micro-ops dispatched for execution </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>RS_UOPS_DISPATCHED_NONE</td><td>	No Micro-ops dispatched for execution </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>MACRO_INSTS</td><td>	instructions decoded </td><td> 0, 1</td><td>
	0x01: Instructions decoded
 <br />
	0x08: CISC Instructions decoded
 <br />
</td>

</tr>

<tr><td>ESP</td><td>	ESP register events </td><td> 0, 1</td><td>
	0x01: ESP register content synchronizations
 <br />
	0x02: ESP register automatic additions
 <br />
</td>

</tr>

<tr><td>SIMD_UOPS_EXEC</td><td>	SIMD micro-ops executed (excluding stores) </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>SIMD_SAT_UOP_EXEC</td><td>	number of SIMD saturating instructions executed </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>SIMD_UOP_TYPE_EXEC</td><td>	number of SIMD packing instructions </td><td> 0, 1</td><td>
	0x01: SIMD packed multiplies
 <br />
	0x02: SIMD packed shifts
 <br />
	0x04: SIMD pack operations
 <br />
	0x08: SIMD unpack operations
 <br />
	0x10: SIMD packed logical
 <br />
	0x20: SIMD packed arithmetic
 <br />
	0x3f: all of the above
 <br />
</td>

</tr>

<tr><td>INST_RETIRED</td><td>	number of instructions retired </td><td> 0, 1</td><td>
	0x00: (name=Any) Any
 <br />
	0x01: (name=Loads) Loads
 <br />
	0x02: (name=Stores) Stores
 <br />
	0x04: (name=Other) Other
 <br />
</td>

</tr>

<tr><td>X87_OPS_RETIRED</td><td>	number of computational FP operations retired </td><td> 0, 1</td><td>
	0x01: FXCH instructions retired
 <br />
	0xfe: Retired floating-point computational operations (precise)
 <br />
</td>

</tr>

<tr><td>UOPS_RETIRED</td><td>	number of UOPs retired </td><td> 0, 1</td><td>
	0x01: Fused load+op or load+indirect branch retired
 <br />
	0x02: Fused store address + data retired
 <br />
	0x04: Retired instruction pairs fused into one micro-op
 <br />
	0x07: Fused micro-ops retired
 <br />
	0x08: Non-fused micro-ops retired
 <br />
	0x0f: Micro-ops retired
 <br />
</td>

</tr>

<tr><td>MACHINE_NUKES_SMC</td><td>	number of pipeline flushing events </td><td> 0, 1</td><td>
	0x01: Self-Modifying Code detected
 <br />
	0x04: Execution pipeline restart due to memory ordering conflict or memory disambiguation misprediction
 <br />
</td>

</tr>

<tr><td>BR_INST_RETIRED</td><td>	number of branch instructions retired </td><td> 0, 1</td><td>
	0x01: predicted not-taken
 <br />
	0x02: mispredicted not-taken
 <br />
	0x04: predicted taken
 <br />
	0x08: mispredicted taken
 <br />
</td>

</tr>

<tr><td>BR_MISS_PRED_RETIRED</td><td>	number of mispredicted branches retired (precise) </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>CYCLES_INT_MASKED</td><td>	cycles interrupts are disabled </td><td> 0, 1</td><td>
	0x01: Interrupts disabled
 <br />
	0x02: Interrupts pending and disabled
 <br />
</td>

</tr>

<tr><td>SIMD_INST_RETIRED</td><td>	SSE/SSE2 instructions retired </td><td> 0, 1</td><td>
	0x01: Retired SSE packed-single instructions
 <br />
	0x02: Retired SSE scalar-single instructions
 <br />
	0x04: Retired SSE2 packed-double instructions
 <br />
	0x08: Retired SSE2 scalar-double instructions
 <br />
	0x10: Retired SSE2 vector integer instructions
 <br />
	0x1f: Retired Streaming SIMD instructions (precise event)
 <br />
</td>

</tr>

<tr><td>HW_INT_RCV</td><td>	number of hardware interrupts received </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>ITLB_MISS_RETIRED</td><td>	Retired instructions that missed the ITLB </td><td> 0</td><td>
</td>

</tr>

<tr><td>SIMD_COMP_INST_RETIRED</td><td>	Retired computational SSE/SSE2 instructions </td><td> 0, 1</td><td>
	0x01: Retired computational SSE packed-single instructions
 <br />
	0x02: Retired computational SSE scalar-single instructions
 <br />
	0x04: Retired computational SSE2 packed-double instructions
 <br />
	0x08: Retired computational SSE2 scalar-double instructions
 <br />
</td>

</tr>

<tr><td>MEM_LOAD_RETIRED</td><td>	Retired loads </td><td> 0</td><td>
	0x01: Retired loads that miss the L1 data cache (precise event)
 <br />
	0x02: L1 data cache line missed by retired loads (precise event)
 <br />
	0x04: Retired loads that miss the L2 cache (precise event)
 <br />
	0x08: L2 cache line missed by retired loads (precise event)
 <br />
	0x10: Retired loads that miss the DTLB (precise event)
 <br />
</td>

</tr>

<tr><td>FP_MMX_TRANS</td><td>	MMX-floating point transitions </td><td> 0, 1</td><td>
	0x01: float->MMX transitions
 <br />
	0x02: MMX->float transitions
 <br />
</td>

</tr>

<tr><td>MMX_ASSIST</td><td>	number of EMMS instructions executed </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>SIMD_INSTR_RET</td><td>	number of SIMD instructions retired </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>SIMD_SAT_INSTR_RET</td><td>	number of saturated arithmetic instructions retired </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>RAT_STALLS</td><td>	Partial register stall cycles </td><td> 0, 1</td><td>
	0x01: ROB read port
 <br />
	0x02: Partial register
 <br />
	0x04: Flag
 <br />
	0x08: FPU status word
 <br />
	0x0f: All RAT
 <br />
</td>

</tr>

<tr><td>SEG_RENAME_STALLS</td><td>	Segment rename stalls </td><td> 0, 1</td><td>
	0x01: (name=ES) ES
 <br />
	0x02: (name=DS) DS
 <br />
	0x04: (name=FS) FS
 <br />
	0x08: (name=GS) GS
 <br />
</td>

</tr>

<tr><td>SEG_RENAMES</td><td>	Segment renames </td><td> 0, 1</td><td>
	0x01: (name=ES) ES
 <br />
	0x02: (name=DS) DS
 <br />
	0x04: (name=FS) FS
 <br />
	0x08: (name=GS) GS
 <br />
</td>

</tr>

<tr><td>RESOURCE_STALLS</td><td>	Cycles during which resource stalls occur </td><td> 0, 1</td><td>
	0x01: when the ROB is full
 <br />
	0x02: during which the RS is full
 <br />
	0x04: during which the pipeline has exceeded the load or store limit or is waiting to commit all stores
 <br />
	0x08: due to FPU control word write
 <br />
	0x10: due to branch misprediction
 <br />
</td>

</tr>

<tr><td>BR_INST_DECODED</td><td>	number of branch instructions decoded </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>BR_BOGUS</td><td>	number of bogus branches </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>BACLEARS</td><td>	number of times BACLEAR is asserted </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>PREF_RQSTS_UP</td><td>	Number of upward prefetches issued </td><td> 0, 1</td><td>
</td>

</tr>

<tr><td>PREF_RQSTS_DN</td><td>	Number of downward prefetches issued </td><td> 0, 1</td><td>
</td>

</tr>

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