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+++ b/docs/intel-atom-events
@@ -1,52 +1,52 @@
-<tr><td>CPU_CLK_UNHALTED</td><td>	Clock cycles when not halted </td><td> all</td><td>
-	0x00: core_p Core cycles when core is not halted
- <br />
-	0x01: bus Bus cycles when core is not halted
- <br />
-	0x02: no_other Bus cycles when core is active and the other is halted
- <br />
-</td>
-
-</tr>
-
-<tr><td>UNHALTED_REFERENCE_CYCLES</td><td>	Unhalted reference cycles </td><td> all</td><td>
+<tr><td>CPU_CLK_UNHALTED</td><td>	Clock cycles when not halted </td><td> 0, 1</td><td>
+	0x00: (name=core_p) Core cycles when core is not halted
+ <br />
+	0x01: (name=bus) Bus cycles when core is not halted
+ <br />
+	0x02: (name=no_other) Bus cycles when core is active and the other is halted
+ <br />
+</td>
+
+</tr>
+
+<tr><td>UNHALTED_REFERENCE_CYCLES</td><td>	Unhalted reference cycles </td><td> 0, 1</td><td>
 	0x01: No unit mask
  <br />
 </td>
 
 </tr>
 
-<tr><td>INST_RETIRED</td><td>	number of instructions retired </td><td> all</td><td>
+<tr><td>INST_RETIRED</td><td>	number of instructions retired </td><td> 0, 1</td><td>
 	0x01: No unit mask
  <br />
 </td>
 
 </tr>
 
-<tr><td>LLC_MISSES</td><td>	Last level cache demand requests from this core that missed the LLC </td><td> all</td><td>
+<tr><td>LLC_MISSES</td><td>	Last level cache demand requests from this core that missed the LLC </td><td> 0, 1</td><td>
 	0x41: No unit mask
  <br />
 </td>
 
 </tr>
 
-<tr><td>LLC_REFS</td><td>	Last level cache demand requests from this core </td><td> all</td><td>
+<tr><td>LLC_REFS</td><td>	Last level cache demand requests from this core </td><td> 0, 1</td><td>
 	0x4f: No unit mask
  <br />
 </td>
 
 </tr>
 
-<tr><td>BR_INST_RETIRED</td><td>	number of branch instructions retired </td><td> all</td><td>
-	0x00: any Retired branch instructions
- <br />
-	0x01: pred_not_taken Retired branch instructions that were predicted not-taken
- <br />
-	0x02: mispred_not_taken Retired branch instructions that were mispredicted not-taken
- <br />
-	0x04: pred_taken Retired branch instructions that were predicted taken
- <br />
-	0x08: mispred_taken Retired branch instructions that were mispredicted taken
+<tr><td>BR_INST_RETIRED</td><td>	number of branch instructions retired </td><td> 0, 1</td><td>
+	0x00: (name=any) Retired branch instructions
+ <br />
+	0x01: (name=pred_not_taken) Retired branch instructions that were predicted not-taken
+ <br />
+	0x02: (name=mispred_not_taken) Retired branch instructions that were mispredicted not-taken
+ <br />
+	0x04: (name=pred_taken) Retired branch instructions that were predicted taken
+ <br />
+	0x08: (name=mispred_taken) Retired branch instructions that were mispredicted taken
  <br />
 	0x0a: mispred Retired mispredicted branch instructions (precise event)
  <br />
@@ -58,667 +58,667 @@
 
 </tr>
 
-<tr><td>BR_MISS_PRED_RETIRED</td><td>	number of mispredicted branches retired (precise) </td><td> all</td><td>
-</td>
-
-</tr>
-
-<tr><td>STORE_FORWARDS</td><td>	Good store forwards </td><td> all</td><td>
-	0x81: good Good store forwards
- <br />
-</td>
-
-</tr>
-
-<tr><td>SEGMENT_REG_LOADS</td><td>	Number of segment register loads </td><td> all</td><td>
-	0x00: any Number of segment register loads
- <br />
-</td>
-
-</tr>
-
-<tr><td>PREFETCH</td><td>	Streaming SIMD Extensions (SSE) Prefetch instructions executed </td><td> all</td><td>
-	0x01: prefetcht0 Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed
- <br />
-	0x06: sw_l2 Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed
- <br />
-	0x08: prefetchnta Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed
- <br />
-</td>
-
-</tr>
-
-<tr><td>DATA_TLB_MISSES</td><td>	Memory accesses that missed the DTLB </td><td> all</td><td>
-	0x07: dtlb_miss Memory accesses that missed the DTLB
- <br />
-	0x05: dtlb_miss_ld DTLB misses due to load operations
- <br />
-	0x09: l0_dtlb_miss_ld L0_DTLB misses due to load operations
- <br />
-	0x06: dtlb_miss_st DTLB misses due to store operations
- <br />
-</td>
-
-</tr>
-
-<tr><td>PAGE_WALKS</td><td>	Page walks </td><td> all</td><td>
-	0x03: walks Number of page-walks executed
- <br />
-	0x03: cycles Duration of page-walks in core cycles
- <br />
-</td>
-
-</tr>
-
-<tr><td>X87_COMP_OPS_EXE</td><td>	Floating point computational micro-ops </td><td> all</td><td>
-	0x01: s Floating point computational micro-ops executed
- <br />
-	0x81: ar Floating point computational micro-ops retired
- <br />
-</td>
-
-</tr>
-
-<tr><td>FP_ASSIST</td><td>	Floating point assists </td><td> all</td><td>
-	0x81: ar Floating point assists
- <br />
-</td>
-
-</tr>
-
-<tr><td>MUL</td><td>	Multiply operations </td><td> all</td><td>
-	0x01: s Multiply operations executed
- <br />
-	0x81: ar Multiply operations retired
- <br />
-</td>
-
-</tr>
-
-<tr><td>DIV</td><td>	Divide operations </td><td> all</td><td>
-	0x01: s Divide operations executed
- <br />
-	0x81: ar Divide operations retired
- <br />
-</td>
-
-</tr>
-
-<tr><td>CYCLES_DIV_BUSY</td><td>	Cycles the driver is busy </td><td> all</td><td>
+<tr><td>BR_MISS_PRED_RETIRED</td><td>	number of mispredicted branches retired (precise) </td><td> 0, 1</td><td>
+</td>
+
+</tr>
+
+<tr><td>STORE_FORWARDS</td><td>	Good store forwards </td><td> 0, 1</td><td>
+	0x81: (name=good) Good store forwards
+ <br />
+</td>
+
+</tr>
+
+<tr><td>SEGMENT_REG_LOADS</td><td>	Number of segment register loads </td><td> 0, 1</td><td>
+	0x00: (name=any) Number of segment register loads
+ <br />
+</td>
+
+</tr>
+
+<tr><td>PREFETCH</td><td>	Streaming SIMD Extensions (SSE) Prefetch instructions executed </td><td> 0, 1</td><td>
+	0x01: (name=prefetcht0) Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed
+ <br />
+	0x06: (name=sw_l2) Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed
+ <br />
+	0x08: (name=prefetchnta) Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed
+ <br />
+</td>
+
+</tr>
+
+<tr><td>DATA_TLB_MISSES</td><td>	Memory accesses that missed the DTLB </td><td> 0, 1</td><td>
+	0x07: (name=dtlb_miss) Memory accesses that missed the DTLB
+ <br />
+	0x05: (name=dtlb_miss_ld) DTLB misses due to load operations
+ <br />
+	0x09: (name=l0_dtlb_miss_ld) L0_DTLB misses due to load operations
+ <br />
+	0x06: (name=dtlb_miss_st) DTLB misses due to store operations
+ <br />
+</td>
+
+</tr>
+
+<tr><td>PAGE_WALKS</td><td>	Page walks </td><td> 0, 1</td><td>
+	0x03: (name=walks) Number of page-walks executed
+ <br />
+	0x03: (name=cycles) Duration of page-walks in core cycles
+ <br />
+</td>
+
+</tr>
+
+<tr><td>X87_COMP_OPS_EXE</td><td>	Floating point computational micro-ops </td><td> 0, 1</td><td>
+	0x01: (name=s) Floating point computational micro-ops executed
+ <br />
+	0x81: (name=ar) Floating point computational micro-ops retired
+ <br />
+</td>
+
+</tr>
+
+<tr><td>FP_ASSIST</td><td>	Floating point assists </td><td> 0, 1</td><td>
+	0x81: (name=ar) Floating point assists
+ <br />
+</td>
+
+</tr>
+
+<tr><td>MUL</td><td>	Multiply operations </td><td> 0, 1</td><td>
+	0x01: (name=s) Multiply operations executed
+ <br />
+	0x81: (name=ar) Multiply operations retired
+ <br />
+</td>
+
+</tr>
+
+<tr><td>DIV</td><td>	Divide operations </td><td> 0, 1</td><td>
+	0x01: (name=s) Divide operations executed
+ <br />
+	0x81: (name=ar) Divide operations retired
+ <br />
+</td>
+
+</tr>
+
+<tr><td>CYCLES_DIV_BUSY</td><td>	Cycles the driver is busy </td><td> 0, 1</td><td>
 	0x01: No unit mask
  <br />
 </td>
 
 </tr>
 
-<tr><td>CORE</td><td>	Cycles L2 address bus is in use </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-</td>
-
-</tr>
-
-<tr><td>L2_DBUS_BUSY</td><td>	Cycles the L2 cache data bus is busy </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-</td>
-
-</tr>
-
-<tr><td>L2_LINES_IN</td><td>	L2 cache misses </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x60: all All inclusive
- <br />
-	0x20: hw Hardware prefetch only
- <br />
-	0x00: exclude_hw Exclude hardware prefetch
- <br />
-</td>
-
-</tr>
-
-<tr><td>L2_M_LINES_IN</td><td>	L2 cache line modifications </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-</td>
-
-</tr>
-
-<tr><td>L2_LINES_OUT</td><td>	L2 cache lines evicted </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x60: all All inclusive
- <br />
-	0x20: hw Hardware prefetch only
- <br />
-	0x00: exclude_hw Exclude hardware prefetch
- <br />
-</td>
-
-</tr>
-
-<tr><td>L2_M_LINES_OUT</td><td>	Modified lines evicted from the L2 cache </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x60: all All inclusive
- <br />
-	0x20: hw Hardware prefetch only
- <br />
-	0x00: exclude_hw Exclude hardware prefetch
- <br />
-</td>
-
-</tr>
-
-<tr><td>L2_IFETCH</td><td>	L2 cacheable instruction fetch requests </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x08: modified Counts modified state
- <br />
-	0x04: exclusive Counts exclusive state
- <br />
-	0x02: shared Counts shared state
- <br />
-	0x01: invalid Counts invalid state
- <br />
-</td>
-
-</tr>
-
-<tr><td>L2_LD</td><td>	L2 cache reads </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x60: all All inclusive
- <br />
-	0x20: hw Hardware prefetch only
- <br />
-	0x00: exclude_hw Exclude hardware prefetch
- <br />
-	0x08: modified Counts modified state
- <br />
-	0x04: exclusive Counts exclusive state
- <br />
-	0x02: shared Counts shared state
- <br />
-	0x01: invalid Counts invalid state
- <br />
-</td>
-
-</tr>
-
-<tr><td>L2_ST</td><td>	L2 store requests </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x08: modified Counts modified state
- <br />
-	0x04: exclusive Counts exclusive state
- <br />
-	0x02: shared Counts shared state
- <br />
-	0x01: invalid Counts invalid state
- <br />
-</td>
-
-</tr>
-
-<tr><td>L2_LOCK</td><td>	L2 locked accesses </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x08: modified Counts modified state
- <br />
-	0x04: exclusive Counts exclusive state
- <br />
-	0x02: shared Counts shared state
- <br />
-	0x01: invalid Counts invalid state
- <br />
-</td>
-
-</tr>
-
-<tr><td>L2_RQSTS</td><td>	L2 cache requests </td><td> all</td><td>
-	0x41: i_state L2 cache demand requests from this core that missed the L2
+<tr><td>CORE</td><td>	Cycles L2 address bus is in use </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+</td>
+
+</tr>
+
+<tr><td>L2_DBUS_BUSY</td><td>	Cycles the L2 cache data bus is busy </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+</td>
+
+</tr>
+
+<tr><td>L2_LINES_IN</td><td>	L2 cache misses </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x60: (name=all) All inclusive
+ <br />
+	0x20: (name=hw) Hardware prefetch only
+ <br />
+	0x00: (name=exclude_hw) Exclude hardware prefetch
+ <br />
+</td>
+
+</tr>
+
+<tr><td>L2_M_LINES_IN</td><td>	L2 cache line modifications </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+</td>
+
+</tr>
+
+<tr><td>L2_LINES_OUT</td><td>	L2 cache lines evicted </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x60: (name=all) All inclusive
+ <br />
+	0x20: (name=hw) Hardware prefetch only
+ <br />
+	0x00: (name=exclude_hw) Exclude hardware prefetch
+ <br />
+</td>
+
+</tr>
+
+<tr><td>L2_M_LINES_OUT</td><td>	Modified lines evicted from the L2 cache </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x60: (name=all) All inclusive
+ <br />
+	0x20: (name=hw) Hardware prefetch only
+ <br />
+	0x00: (name=exclude_hw) Exclude hardware prefetch
+ <br />
+</td>
+
+</tr>
+
+<tr><td>L2_IFETCH</td><td>	L2 cacheable instruction fetch requests </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x08: (name=modified) Counts modified state
+ <br />
+	0x04: (name=exclusive) Counts exclusive state
+ <br />
+	0x02: (name=shared) Counts shared state
+ <br />
+	0x01: (name=invalid) Counts invalid state
+ <br />
+</td>
+
+</tr>
+
+<tr><td>L2_LD</td><td>	L2 cache reads </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x60: (name=all) All inclusive
+ <br />
+	0x20: (name=hw) Hardware prefetch only
+ <br />
+	0x00: (name=exclude_hw) Exclude hardware prefetch
+ <br />
+	0x08: (name=modified) Counts modified state
+ <br />
+	0x04: (name=exclusive) Counts exclusive state
+ <br />
+	0x02: (name=shared) Counts shared state
+ <br />
+	0x01: (name=invalid) Counts invalid state
+ <br />
+</td>
+
+</tr>
+
+<tr><td>L2_ST</td><td>	L2 store requests </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x08: (name=modified) Counts modified state
+ <br />
+	0x04: (name=exclusive) Counts exclusive state
+ <br />
+	0x02: (name=shared) Counts shared state
+ <br />
+	0x01: (name=invalid) Counts invalid state
+ <br />
+</td>
+
+</tr>
+
+<tr><td>L2_LOCK</td><td>	L2 locked accesses </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x08: (name=modified) Counts modified state
+ <br />
+	0x04: (name=exclusive) Counts exclusive state
+ <br />
+	0x02: (name=shared) Counts shared state
+ <br />
+	0x01: (name=invalid) Counts invalid state
+ <br />
+</td>
+
+</tr>
+
+<tr><td>L2_RQSTS</td><td>	L2 cache requests </td><td> 0, 1</td><td>
+	0x41: (name=i_state) L2 cache demand requests from this core that missed the L2
  <br />
 	0x4f: mesi L2 cache demand requests from this core
  <br />
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x60: all All inclusive
- <br />
-	0x20: hw Hardware prefetch only
- <br />
-	0x00: exclude_hw Exclude hardware prefetch
- <br />
-	0x08: modified Counts modified state
- <br />
-	0x04: exclusive Counts exclusive state
- <br />
-	0x02: shared Counts shared state
- <br />
-	0x01: invalid Counts invalid state
- <br />
-</td>
-
-</tr>
-
-<tr><td>L2_REJECT_BUSQ</td><td>	Rejected L2 cache requests </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x60: all All inclusive
- <br />
-	0x20: hw Hardware prefetch only
- <br />
-	0x00: exclude_hw Exclude hardware prefetch
- <br />
-	0x08: modified Counts modified state
- <br />
-	0x04: exclusive Counts exclusive state
- <br />
-	0x02: shared Counts shared state
- <br />
-	0x01: invalid Counts invalid state
- <br />
-</td>
-
-</tr>
-
-<tr><td>L2_NO_REQ</td><td>	Cycles no L2 cache requests are pending </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-</td>
-
-</tr>
-
-<tr><td>EIST_TRANS</td><td>	Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions </td><td> all</td><td>
-</td>
-
-</tr>
-
-<tr><td>THERMAL_TRIP</td><td>	Number of thermal trips </td><td> all</td><td>
-	0xc0: thermal_trip Number of thermal trips.
- <br />
-</td>
-
-</tr>
-
-<tr><td>L1D_CACHE</td><td>	L1d Cache accesses </td><td> all</td><td>
-	0x21: ld L1 Cacheable Data Reads
- <br />
-	0x22: st L1 Cacheable Data Writes
- <br />
-</td>
-
-</tr>
-
-<tr><td>BUS_REQUEST_OUTSTANDING</td><td>	Outstanding cacheable data read bus requests duration </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x00: this This agent
- <br />
-	0x40: any Include any agents
- <br />
-</td>
-
-</tr>
-
-<tr><td>BUS_BNR_DRV</td><td>	Number of Bus Not Ready signals asserted </td><td> all</td><td>
-	0x00: this This agent
- <br />
-	0x40: any Include any agents
- <br />
-</td>
-
-</tr>
-
-<tr><td>BUS_DRDY_CLOCKS</td><td>	Bus cycles when data is sent on the bus </td><td> all</td><td>
-	0x00: this This agent
- <br />
-	0x40: any Include any agents
- <br />
-</td>
-
-</tr>
-
-<tr><td>BUS_LOCK_CLOCKS</td><td>	Bus cycles when a LOCK signal is asserted. </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x00: this This agent
- <br />
-	0x40: any Include any agents
- <br />
-</td>
-
-</tr>
-
-<tr><td>BUS_DATA_RCV</td><td>	Bus cycles while processor receives data </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-</td>
-
-</tr>
-
-<tr><td>BUS_TRANS_BRD</td><td>	Burst read bus transactions </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x00: this This agent
- <br />
-	0x40: any Include any agents
- <br />
-</td>
-
-</tr>
-
-<tr><td>BUS_TRANS_RFO</td><td>	RFO bus transactions </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x00: this This agent
- <br />
-	0x40: any Include any agents
- <br />
-</td>
-
-</tr>
-
-<tr><td>BUS_TRANS_WB</td><td>	Explicit writeback bus transactions </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x00: this This agent
- <br />
-	0x40: any Include any agents
- <br />
-</td>
-
-</tr>
-
-<tr><td>BUS_TRANS_IFETCH</td><td>	Instruction-fetch bus transactions. </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x00: this This agent
- <br />
-	0x40: any Include any agents
- <br />
-</td>
-
-</tr>
-
-<tr><td>BUS_TRANS_INVAL</td><td>	Invalidate bus transactions </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x00: this This agent
- <br />
-	0x40: any Include any agents
- <br />
-</td>
-
-</tr>
-
-<tr><td>BUS_TRANS_PWR</td><td>	Partial write bus transaction. </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x00: this This agent
- <br />
-	0x40: any Include any agents
- <br />
-</td>
-
-</tr>
-
-<tr><td>BUS_TRANS_P</td><td>	Partial bus transactions </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x00: this This agent
- <br />
-	0x40: any Include any agents
- <br />
-</td>
-
-</tr>
-
-<tr><td>BUS_TRANS_IO</td><td>	IO bus transactions </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x00: this This agent
- <br />
-	0x40: any Include any agents
- <br />
-</td>
-
-</tr>
-
-<tr><td>BUS_TRANS_DEF</td><td>	Deferred bus transactions </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x00: this This agent
- <br />
-	0x40: any Include any agents
- <br />
-</td>
-
-</tr>
-
-<tr><td>BUS_TRANS_BURST</td><td>	Burst (full cache-line) bus transactions. </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x00: this This agent
- <br />
-	0x40: any Include any agents
- <br />
-</td>
-
-</tr>
-
-<tr><td>BUS_TRANS_MEM</td><td>	Memory bus transactions </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x00: this This agent
- <br />
-	0x40: any Include any agents
- <br />
-</td>
-
-</tr>
-
-<tr><td>BUS_TRANS_ANY</td><td>	All bus transactions </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x00: this This agent
- <br />
-	0x40: any Include any agents
- <br />
-</td>
-
-</tr>
-
-<tr><td>EXT_SNOOP</td><td>	External snoops </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x08: modified Counts modified state
- <br />
-	0x04: exclusive Counts exclusive state
- <br />
-	0x02: shared Counts shared state
- <br />
-	0x01: invalid Counts invalid state
- <br />
-</td>
-
-</tr>
-
-<tr><td>BUS_HIT_DRV</td><td>	HIT signal asserted </td><td> all</td><td>
-	0x00: this This agent
- <br />
-	0x40: any Include any agents
- <br />
-</td>
-
-</tr>
-
-<tr><td>BUS_HITM_DRV</td><td>	HITM signal asserted </td><td> all</td><td>
-	0x00: this This agent
- <br />
-	0x40: any Include any agents
- <br />
-</td>
-
-</tr>
-
-<tr><td>BUSQ_EMPTY</td><td>	Bus queue is empty </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-</td>
-
-</tr>
-
-<tr><td>SNOOP_STALL_DRV</td><td>	Bus stalled for snoops </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-	0x00: this This agent
- <br />
-	0x40: any Include any agents
- <br />
-</td>
-
-</tr>
-
-<tr><td>BUS_IO_WAIT</td><td>	IO requests waiting in the bus queue </td><td> all</td><td>
-	0x180: all All cores.
- <br />
-	0x80: this This Core.
- <br />
-</td>
-
-</tr>
-
-<tr><td>ICACHE</td><td>	Instruction cache accesses </td><td> all</td><td>
-	0x03: accesses Instruction fetches
- <br />
-	0x02: misses Icache miss
- <br />
-</td>
-
-</tr>
-
-<tr><td>ITLB</td><td>	ITLB events </td><td> all</td><td>
-	0x04: flush ITLB flushes
- <br />
-	0x02: misses ITLB misses
- <br />
-</td>
-
-</tr>
-
-<tr><td>MACRO_INSTS</td><td>	instructions decoded </td><td> all</td><td>
-	0x02: cisc_decoded CISC macro instructions decoded
- <br />
-	0x03: all_decoded All Instructions decoded
- <br />
-</td>
-
-</tr>
-
-<tr><td>SIMD_UOPS_EXEC</td><td>	SIMD micro-ops executed </td><td> all</td><td>
-	0x00: s SIMD micro-ops executed (excluding stores)
- <br />
-	0x80: ar SIMD micro-ops retired (excluding stores)
- <br />
-</td>
-
-</tr>
-
-<tr><td>SIMD_SAT_UOP_EXEC</td><td>	SIMD saturated arithmetic micro-ops executed </td><td> all</td><td>
-	0x00: s SIMD saturated arithmetic micro-ops executed
- <br />
-	0x80: ar SIMD saturated arithmetic micro-ops retired
- <br />
-</td>
-
-</tr>
-
-<tr><td>SIMD_UOP_TYPE_EXEC</td><td>	SIMD packed microops executed </td><td> all</td><td>
-	0x01: s SIMD packed multiply microops executed
- <br />
-	0x81: ar SIMD packed multiply microops retired
- <br />
-	0x02: s SIMD packed shift micro-ops executed
- <br />
-	0x82: ar SIMD packed shift micro-ops retired
- <br />
-	0x04: s SIMD pack micro-ops executed
- <br />
-	0x84: ar SIMD pack micro-ops retired
- <br />
-	0x08: s SIMD unpack micro-ops executed
- <br />
-	0x88: ar SIMD unpack micro-ops retired
- <br />
-	0x10: s SIMD packed logical microops executed
- <br />
-	0x90: ar SIMD packed logical microops retired
- <br />
-	0x20: s SIMD packed arithmetic micro-ops executed
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x60: (name=all) All inclusive
+ <br />
+	0x20: (name=hw) Hardware prefetch only
+ <br />
+	0x00: (name=exclude_hw) Exclude hardware prefetch
+ <br />
+	0x08: (name=modified) Counts modified state
+ <br />
+	0x04: (name=exclusive) Counts exclusive state
+ <br />
+	0x02: (name=shared) Counts shared state
+ <br />
+	0x01: (name=invalid) Counts invalid state
+ <br />
+</td>
+
+</tr>
+
+<tr><td>L2_REJECT_BUSQ</td><td>	Rejected L2 cache requests </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x60: (name=all) All inclusive
+ <br />
+	0x20: (name=hw) Hardware prefetch only
+ <br />
+	0x00: (name=exclude_hw) Exclude hardware prefetch
+ <br />
+	0x08: (name=modified) Counts modified state
+ <br />
+	0x04: (name=exclusive) Counts exclusive state
+ <br />
+	0x02: (name=shared) Counts shared state
+ <br />
+	0x01: (name=invalid) Counts invalid state
+ <br />
+</td>
+
+</tr>
+
+<tr><td>L2_NO_REQ</td><td>	Cycles no L2 cache requests are pending </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+</td>
+
+</tr>
+
+<tr><td>EIST_TRANS</td><td>	Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions </td><td> 0, 1</td><td>
+</td>
+
+</tr>
+
+<tr><td>THERMAL_TRIP</td><td>	Number of thermal trips </td><td> 0, 1</td><td>
+	0xc0: (name=thermal_trip) Number of thermal trips.
+ <br />
+</td>
+
+</tr>
+
+<tr><td>L1D_CACHE</td><td>	L1d Cache accesses </td><td> 0, 1</td><td>
+	0x21: (name=ld) L1 Cacheable Data Reads
+ <br />
+	0x22: (name=st) L1 Cacheable Data Writes
+ <br />
+</td>
+
+</tr>
+
+<tr><td>BUS_REQUEST_OUTSTANDING</td><td>	Outstanding cacheable data read bus requests duration </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x00: (name=this) This agent
+ <br />
+	0x40: (name=any) Include any agents
+ <br />
+</td>
+
+</tr>
+
+<tr><td>BUS_BNR_DRV</td><td>	Number of Bus Not Ready signals asserted </td><td> 0, 1</td><td>
+	0x00: (name=this) This agent
+ <br />
+	0x40: (name=any) Include any agents
+ <br />
+</td>
+
+</tr>
+
+<tr><td>BUS_DRDY_CLOCKS</td><td>	Bus cycles when data is sent on the bus </td><td> 0, 1</td><td>
+	0x00: (name=this) This agent
+ <br />
+	0x40: (name=any) Include any agents
+ <br />
+</td>
+
+</tr>
+
+<tr><td>BUS_LOCK_CLOCKS</td><td>	Bus cycles when a LOCK signal is asserted. </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x00: (name=this) This agent
+ <br />
+	0x40: (name=any) Include any agents
+ <br />
+</td>
+
+</tr>
+
+<tr><td>BUS_DATA_RCV</td><td>	Bus cycles while processor receives data </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+</td>
+
+</tr>
+
+<tr><td>BUS_TRANS_BRD</td><td>	Burst read bus transactions </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x00: (name=this) This agent
+ <br />
+	0x40: (name=any) Include any agents
+ <br />
+</td>
+
+</tr>
+
+<tr><td>BUS_TRANS_RFO</td><td>	RFO bus transactions </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x00: (name=this) This agent
+ <br />
+	0x40: (name=any) Include any agents
+ <br />
+</td>
+
+</tr>
+
+<tr><td>BUS_TRANS_WB</td><td>	Explicit writeback bus transactions </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x00: (name=this) This agent
+ <br />
+	0x40: (name=any) Include any agents
+ <br />
+</td>
+
+</tr>
+
+<tr><td>BUS_TRANS_IFETCH</td><td>	Instruction-fetch bus transactions. </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x00: (name=this) This agent
+ <br />
+	0x40: (name=any) Include any agents
+ <br />
+</td>
+
+</tr>
+
+<tr><td>BUS_TRANS_INVAL</td><td>	Invalidate bus transactions </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x00: (name=this) This agent
+ <br />
+	0x40: (name=any) Include any agents
+ <br />
+</td>
+
+</tr>
+
+<tr><td>BUS_TRANS_PWR</td><td>	Partial write bus transaction. </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x00: (name=this) This agent
+ <br />
+	0x40: (name=any) Include any agents
+ <br />
+</td>
+
+</tr>
+
+<tr><td>BUS_TRANS_P</td><td>	Partial bus transactions </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x00: (name=this) This agent
+ <br />
+	0x40: (name=any) Include any agents
+ <br />
+</td>
+
+</tr>
+
+<tr><td>BUS_TRANS_IO</td><td>	IO bus transactions </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x00: (name=this) This agent
+ <br />
+	0x40: (name=any) Include any agents
+ <br />
+</td>
+
+</tr>
+
+<tr><td>BUS_TRANS_DEF</td><td>	Deferred bus transactions </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x00: (name=this) This agent
+ <br />
+	0x40: (name=any) Include any agents
+ <br />
+</td>
+
+</tr>
+
+<tr><td>BUS_TRANS_BURST</td><td>	Burst (full cache-line) bus transactions. </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x00: (name=this) This agent
+ <br />
+	0x40: (name=any) Include any agents
+ <br />
+</td>
+
+</tr>
+
+<tr><td>BUS_TRANS_MEM</td><td>	Memory bus transactions </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x00: (name=this) This agent
+ <br />
+	0x40: (name=any) Include any agents
+ <br />
+</td>
+
+</tr>
+
+<tr><td>BUS_TRANS_ANY</td><td>	All bus transactions </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x00: (name=this) This agent
+ <br />
+	0x40: (name=any) Include any agents
+ <br />
+</td>
+
+</tr>
+
+<tr><td>EXT_SNOOP</td><td>	External snoops </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x08: (name=modified) Counts modified state
+ <br />
+	0x04: (name=exclusive) Counts exclusive state
+ <br />
+	0x02: (name=shared) Counts shared state
+ <br />
+	0x01: (name=invalid) Counts invalid state
+ <br />
+</td>
+
+</tr>
+
+<tr><td>BUS_HIT_DRV</td><td>	HIT signal asserted </td><td> 0, 1</td><td>
+	0x00: (name=this) This agent
+ <br />
+	0x40: (name=any) Include any agents
+ <br />
+</td>
+
+</tr>
+
+<tr><td>BUS_HITM_DRV</td><td>	HITM signal asserted </td><td> 0, 1</td><td>
+	0x00: (name=this) This agent
+ <br />
+	0x40: (name=any) Include any agents
+ <br />
+</td>
+
+</tr>
+
+<tr><td>BUSQ_EMPTY</td><td>	Bus queue is empty </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+</td>
+
+</tr>
+
+<tr><td>SNOOP_STALL_DRV</td><td>	Bus stalled for snoops </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+	0x00: (name=this) This agent
+ <br />
+	0x40: (name=any) Include any agents
+ <br />
+</td>
+
+</tr>
+
+<tr><td>BUS_IO_WAIT</td><td>	IO requests waiting in the bus queue </td><td> 0, 1</td><td>
+	0x180: (name=all) All cores.
+ <br />
+	0x80: (name=this) This Core.
+ <br />
+</td>
+
+</tr>
+
+<tr><td>ICACHE</td><td>	Instruction cache accesses </td><td> 0, 1</td><td>
+	0x03: (name=accesses) Instruction fetches
+ <br />
+	0x02: (name=misses) Icache miss
+ <br />
+</td>
+
+</tr>
+
+<tr><td>ITLB</td><td>	ITLB events </td><td> 0, 1</td><td>
+	0x04: (name=flush) ITLB flushes
+ <br />
+	0x02: (name=misses) ITLB misses
+ <br />
+</td>
+
+</tr>
+
+<tr><td>MACRO_INSTS</td><td>	instructions decoded </td><td> 0, 1</td><td>
+	0x02: (name=cisc_decoded) CISC macro instructions decoded
+ <br />
+	0x03: (name=all_decoded) All Instructions decoded
+ <br />
+</td>
+
+</tr>
+
+<tr><td>SIMD_UOPS_EXEC</td><td>	SIMD micro-ops executed </td><td> 0, 1</td><td>
+	0x00: (name=s) SIMD micro-ops executed (excluding stores)
+ <br />
+	0x80: (name=ar) SIMD micro-ops retired (excluding stores)
+ <br />
+</td>
+
+</tr>
+
+<tr><td>SIMD_SAT_UOP_EXEC</td><td>	SIMD saturated arithmetic micro-ops executed </td><td> 0, 1</td><td>
+	0x00: (name=s) SIMD saturated arithmetic micro-ops executed
+ <br />
+	0x80: (name=ar) SIMD saturated arithmetic micro-ops retired
+ <br />
+</td>
+
+</tr>
+
+<tr><td>SIMD_UOP_TYPE_EXEC</td><td>	SIMD packed microops executed </td><td> 0, 1</td><td>
+	0x01: (name=s) SIMD packed multiply microops executed
+ <br />
+	0x81: (name=ar) SIMD packed multiply microops retired
+ <br />
+	0x02: (name=s) SIMD packed shift micro-ops executed
+ <br />
+	0x82: (name=ar) SIMD packed shift micro-ops retired
+ <br />
+	0x04: (name=s) SIMD pack micro-ops executed
+ <br />
+	0x84: (name=ar) SIMD pack micro-ops retired
+ <br />
+	0x08: (name=s) SIMD unpack micro-ops executed
+ <br />
+	0x88: (name=ar) SIMD unpack micro-ops retired
+ <br />
+	0x10: (name=s) SIMD packed logical microops executed
+ <br />
+	0x90: (name=ar) SIMD packed logical microops retired
+ <br />
+	0x20: (name=s) SIMD packed arithmetic micro-ops executed
  <br />
 	0xa0: ar SIMD packed arithmetic micro-ops retired
  <br />
@@ -726,39 +726,39 @@
 
 </tr>
 
-<tr><td>UOPS_RETIRED</td><td>	Micro-ops retired </td><td> all</td><td>
-	0x10: any Micro-ops retired
- <br />
-</td>
-
-</tr>
-
-<tr><td>MACHINE_CLEARS</td><td>	Self-Modifying Code detected </td><td> all</td><td>
+<tr><td>UOPS_RETIRED</td><td>	Micro-ops retired </td><td> 0, 1</td><td>
+	0x10: (name=any) Micro-ops retired
+ <br />
+</td>
+
+</tr>
+
+<tr><td>MACHINE_CLEARS</td><td>	Self-Modifying Code detected </td><td> 0, 1</td><td>
 	0x01: No unit mask
  <br />
 </td>
 
 </tr>
 
-<tr><td>CYCLES_INT_MASKED</td><td>	Cycles during which interrupts are disabled </td><td> all</td><td>
-	0x01: cycles_int_masked Cycles during which interrupts are disabled
- <br />
-	0x02: cycles_int_pending_and_masked Cycles during which interrupts are pending and disabled
- <br />
-</td>
-
-</tr>
-
-<tr><td>SIMD_INST_RETIRED</td><td>	Retired Streaming SIMD Extensions (SSE) instructions </td><td> all</td><td>
-	0x01: packed_single Retired Streaming SIMD Extensions (SSE) packed-single instructions
- <br />
-	0x02: scalar_single Retired Streaming SIMD Extensions (SSE) scalar-single instructions
- <br />
-	0x04: packed_double Retired Streaming SIMD Extensions 2 (SSE2) packed-double instructions
- <br />
-	0x08: scalar_double Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions
- <br />
-	0x10: vector Retired Streaming SIMD Extensions 2 (SSE2) vector instructions
+<tr><td>CYCLES_INT_MASKED</td><td>	Cycles during which interrupts are disabled </td><td> 0, 1</td><td>
+	0x01: (name=cycles_int_masked) Cycles during which interrupts are disabled
+ <br />
+	0x02: (name=cycles_int_pending_and_masked) Cycles during which interrupts are pending and disabled
+ <br />
+</td>
+
+</tr>
+
+<tr><td>SIMD_INST_RETIRED</td><td>	Retired Streaming SIMD Extensions (SSE) instructions </td><td> 0, 1</td><td>
+	0x01: (name=packed_single) Retired Streaming SIMD Extensions (SSE) packed-single instructions
+ <br />
+	0x02: (name=scalar_single) Retired Streaming SIMD Extensions (SSE) scalar-single instructions
+ <br />
+	0x04: (name=packed_double) Retired Streaming SIMD Extensions 2 (SSE2) packed-double instructions
+ <br />
+	0x08: (name=scalar_double) Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions
+ <br />
+	0x10: (name=vector) Retired Streaming SIMD Extensions 2 (SSE2) vector instructions
  <br />
 	0x1f: any Retired Streaming SIMD instructions
  <br />
@@ -766,61 +766,61 @@
 
 </tr>
 
-<tr><td>HW_INT_RCV</td><td>	Hardware interrupts received </td><td> all</td><td>
-</td>
-
-</tr>
-
-<tr><td>SIMD_COMP_INST_RETIRED</td><td>	Retired computational Streaming SIMD Extensions (SSE) instructions. </td><td> all</td><td>
-	0x01: packed_single Retired computational Streaming SIMD Extensions (SSE) packed-single instructions
- <br />
-	0x02: scalar_single Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions
- <br />
-	0x04: packed_double Retired computational Streaming SIMD Extensions 2 (SSE2) packed-double instructions
- <br />
-	0x08: scalar_double Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions
- <br />
-</td>
-
-</tr>
-
-<tr><td>MEM_LOAD_RETIRED</td><td>	Retired loads </td><td> all</td><td>
-	0x01: l2_hit Retired loads that hit the L2 cache (precise event)
- <br />
-	0x02: l2_miss Retired loads that miss the L2 cache (precise event)
- <br />
-	0x04: dtlb_miss Retired loads that miss the DTLB (precise event)
- <br />
-</td>
-
-</tr>
-
-<tr><td>SIMD_ASSIST</td><td>	SIMD assists invoked </td><td> all</td><td>
-</td>
-
-</tr>
-
-<tr><td>SIMD_INSTR_RETIRED</td><td>	SIMD Instructions retired </td><td> all</td><td>
-</td>
-
-</tr>
-
-<tr><td>SIMD_SAT_INSTR_RETIRED</td><td>	Saturated arithmetic instructions retired </td><td> all</td><td>
-</td>
-
-</tr>
-
-<tr><td>BR_INST_DECODED</td><td>	Branch instructions decoded </td><td> all</td><td>
-</td>
-
-</tr>
-
-<tr><td>BOGUS_BR</td><td>	Bogus branches </td><td> all</td><td>
-</td>
-
-</tr>
-
-<tr><td>BACLEARS</td><td>	BACLEARS asserted </td><td> all</td><td>
+<tr><td>HW_INT_RCV</td><td>	Hardware interrupts received </td><td> 0, 1</td><td>
+</td>
+
+</tr>
+
+<tr><td>SIMD_COMP_INST_RETIRED</td><td>	Retired computational Streaming SIMD Extensions (SSE) instructions. </td><td> 0, 1</td><td>
+	0x01: (name=packed_single) Retired computational Streaming SIMD Extensions (SSE) packed-single instructions
+ <br />
+	0x02: (name=scalar_single) Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions
+ <br />
+	0x04: (name=packed_double) Retired computational Streaming SIMD Extensions 2 (SSE2) packed-double instructions
+ <br />
+	0x08: (name=scalar_double) Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions
+ <br />
+</td>
+
+</tr>
+
+<tr><td>MEM_LOAD_RETIRED</td><td>	Retired loads </td><td> 0, 1</td><td>
+	0x01: (name=l2_hit) Retired loads that hit the L2 cache (precise event)
+ <br />
+	0x02: (name=l2_miss) Retired loads that miss the L2 cache (precise event)
+ <br />
+	0x04: (name=dtlb_miss) Retired loads that miss the DTLB (precise event)
+ <br />
+</td>
+
+</tr>
+
+<tr><td>SIMD_ASSIST</td><td>	SIMD assists invoked </td><td> 0, 1</td><td>
+</td>
+
+</tr>
+
+<tr><td>SIMD_INSTR_RETIRED</td><td>	SIMD Instructions retired </td><td> 0, 1</td><td>
+</td>
+
+</tr>
+
+<tr><td>SIMD_SAT_INSTR_RETIRED</td><td>	Saturated arithmetic instructions retired </td><td> 0, 1</td><td>
+</td>
+
+</tr>
+
+<tr><td>BR_INST_DECODED</td><td>	Branch instructions decoded </td><td> 0, 1</td><td>
+</td>
+
+</tr>
+
+<tr><td>BOGUS_BR</td><td>	Bogus branches </td><td> 0, 1</td><td>
+</td>
+
+</tr>
+
+<tr><td>BACLEARS</td><td>	BACLEARS asserted </td><td> 0, 1</td><td>
 	0x01: No unit mask
  <br />
 </td>