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81
<tr><td>PM_INST_DISP</td><td>   Number of PPC Dispatched </td><td> 1</td><td>
81
<tr><td>PM_INST_DISP</td><td>   Number of PPC Dispatched </td><td> 1</td><td>
82
</td>
82
</td>
83
83
84
</tr>
84
</tr>
85
85
86
<tr><td>PM_INST_FROM_L3MISS</td><td>  A Instruction cacheline request resolved from a location that was beyond the local L3 cache </td><td> 2</td><td>
86
<tr><td>PM_INST_FROM_L3MISS</td><td>         </td><td> 2</td><td>
87
</td>
87
</td>
88
88
89
</tr>
89
</tr>
90
90
91
<tr><td>PM_ITLB_MISS</td><td>   ITLB Reloaded (always zero on POWER6) </td><td> 3</td><td>
91
<tr><td>PM_ITLB_MISS</td><td>   ITLB Reloaded (always zero on POWER6) </td><td> 3</td><td>
...
...
156
<tr><td>PM_MRK_INST_DISP</td><td>   The thread has dispatched a randomly sampled marked instruction </td><td> 0</td><td>
156
<tr><td>PM_MRK_INST_DISP</td><td>   The thread has dispatched a randomly sampled marked instruction </td><td> 0</td><td>
157
</td>
157
</td>
158
158
159
</tr>
159
</tr>
160
160
161
<tr><td>PM_MRK_INST_FROM_L3MISS</td><td>  sampled instruction missed icache and came from beyond L3 A Instruction cacheline request for a marked/sampled instruction resolved from a location that was beyond the local L3 cache </td><td> 3</td><td>
161
<tr><td>PM_MRK_INST_FROM_L3MISS</td><td>        cache </td><td> 3</td><td>
162
</td>
162
</td>
163
163
164
</tr>
164
</tr>
165
165
166
<tr><td>PM_MRK_L1_ICACHE_MISS</td><td>  sampled Instruction suffered an icache Miss </td><td> 0</td><td>
166
<tr><td>PM_MRK_L1_ICACHE_MISS</td><td>  sampled Instruction suffered an icache Miss </td><td> 0</td><td>
...
...
216
<tr><td>PM_THRD_CONC_RUN_INST</td><td>  PPC Instructions Finished when both threads in run_cycles </td><td> 2</td><td>
216
<tr><td>PM_THRD_CONC_RUN_INST</td><td>  PPC Instructions Finished when both threads in run_cycles </td><td> 2</td><td>
217
</td>
217
</td>
218
218
219
</tr>
219
</tr>
220
220
221
<tr><td>PM_THRESH_EXC_1024</td><td>   Threshold counter exceeded a value of 1024 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 1024 </td><td> 2</td><td>
221
<tr><td>PM_THRESH_EXC_1024</td><td>        increments when the threshold exceeded a count of 1024 </td><td> 2</td><td>
222
</td>
223
224
</tr>
222
</td>
225
223
226
<tr><td>PM_THRESH_EXC_128</td><td>    Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 128 </td><td> 3</td><td>
227
</td>
224
</tr>
228
225
226
<tr><td>PM_THRESH_EXC_128</td><td>        count of 128 </td><td> 3</td><td>
229
</tr>
227
</td>
230
228
231
<tr><td>PM_THRESH_EXC_2048</td><td>   Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 2048 </td><td> 3</td><td>
232
</td>
229
</tr>
233
230
231
<tr><td>PM_THRESH_EXC_2048</td><td>        count of 2048 </td><td> 3</td><td>
234
</tr>
232
</td>
235
233
236
<tr><td>PM_THRESH_EXC_256</td><td>    Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 256 </td><td> 0</td><td>
237
</td>
234
</tr>
238
235
236
<tr><td>PM_THRESH_EXC_256</td><td>        count of 256 </td><td> 0</td><td>
239
</tr>
237
</td>
240
238
241
<tr><td>PM_THRESH_EXC_32</td><td> Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 32 </td><td> 1</td><td>
242
</td>
239
</tr>
243
240
241
<tr><td>PM_THRESH_EXC_32</td><td>        count of 32 </td><td> 1</td><td>
244
</tr>
242
</td>
245
243
246
<tr><td>PM_THRESH_EXC_4096</td><td>   Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 4096 </td><td> 0</td><td>
247
</td>
244
</tr>
248
245
246
<tr><td>PM_THRESH_EXC_4096</td><td>        count of 4096 </td><td> 0</td><td>
249
</tr>
247
</td>
250
248
251
<tr><td>PM_THRESH_EXC_512</td><td>    Threshold counter exceeded a value of 512 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 512 </td><td> 1</td><td>
252
</td>
249
</tr>
253
250
251
<tr><td>PM_THRESH_EXC_512</td><td>        increments when the threshold exceeded a count of 512 </td><td> 1</td><td>
254
</tr>
252
</td>
255
253
256
<tr><td>PM_THRESH_EXC_64</td><td> Threshold counter exceeded a value of 64 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 64 </td><td> 2</td><td>
254
</tr>
255
256
<tr><td>PM_THRESH_EXC_64</td><td>        increments when the threshold exceeded a count of 64 </td><td> 2</td><td>
257
</td>
257
</td>
258
258
259
</tr>
259
</tr>
260
260
261
<tr><td>PM_THRESH_MET</td><td>  Threshold exceeded </td><td> 0</td><td>
261
<tr><td>PM_THRESH_MET</td><td>  Threshold exceeded </td><td> 0</td><td>
...
...
301
<tr><td>PM_CMPLU_STALL_DCACHE_MISS</td><td> Completion stall by Dcache miss. </td><td> 1</td><td>
301
<tr><td>PM_CMPLU_STALL_DCACHE_MISS</td><td> Completion stall by Dcache miss. </td><td> 1</td><td>
302
</td>
302
</td>
303
303
304
</tr>
304
</tr>
305
305
306
<tr><td>PM_CMPLU_STALL_DMISS_L21_L31</td><td>   Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3). </td><td> 1</td><td>
306
<tr><td>PM_CMPLU_STALL_DMISS_L21_L31</td><td>   Completion stall by Dcache miss. </td><td> 1</td><td>
307
</td>
307
</td>
308
308
309
</tr>
309
</tr>
310
310
311
<tr><td>PM_CMPLU_STALL_DMISS_L2L3</td><td>  Completion stall by Dcache miss which resolved in L2/L3. </td><td> 1</td><td>
311
<tr><td>PM_CMPLU_STALL_DMISS_L2L3</td><td>  Completion stall by Dcache miss which resolved in L2/L3. </td><td> 1</td><td>
312
</td>
312
</td>
313
313
314
</tr>
314
</tr>
315
315
316
<tr><td>PM_CMPLU_STALL_DMISS_L2L3_CONFLICT</td><td>   Completion stall due to cache miss resolving in core's L2/L3 with a conflict. </td><td> 3</td><td>
316
<tr><td>PM_CMPLU_STALL_DMISS_L2L3_CONFLICT</td><td></td><td> 3</td><td>
317
</td>
317
</td>
318
318
319
</tr>
319
</tr>
320
320
321
<tr><td>PM_CMPLU_STALL_DMISS_L3MISS</td><td>    Completion stall due to cache miss resolving missed the L3. </td><td> 3</td><td>
321
<tr><td>PM_CMPLU_STALL_DMISS_L3MISS</td><td>    Completion stall due to cache miss resolving missed the L3. </td><td> 3</td><td>
...
...
326
<tr><td>PM_CMPLU_STALL_DMISS_LMEM</td><td>  Completion stall due to cache miss resolving in core's Local Memory. </td><td> 3</td><td>
326
<tr><td>PM_CMPLU_STALL_DMISS_LMEM</td><td>  Completion stall due to cache miss resolving in core's Local Memory. </td><td> 3</td><td>
327
</td>
327
</td>
328
328
329
</tr>
329
</tr>
330
330
331
<tr><td>PM_CMPLU_STALL_DMISS_REMOTE</td><td>    Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3). </td><td> 1</td><td>
331
<tr><td>PM_CMPLU_STALL_DMISS_REMOTE</td><td>    Completion stall due to cache miss resolving in core's Local Memory. </td><td> 1</td><td>
332
</td>
332
</td>
333
333
334
</tr>
334
</tr>
335
335
336
<tr><td>PM_CMPLU_STALL_ERAT_MISS</td><td>   Completion stall due to LSU reject ERAT miss. </td><td> 3</td><td>
336
<tr><td>PM_CMPLU_STALL_ERAT_MISS</td><td>   Completion stall due to LSU reject ERAT miss. </td><td> 3</td><td>
...
...
441
<tr><td>PM_CMPLU_STALL_VSU</td><td> Completion stall due to VSU instruction. </td><td> 1</td><td>
441
<tr><td>PM_CMPLU_STALL_VSU</td><td> Completion stall due to VSU instruction. </td><td> 1</td><td>
442
</td>
442
</td>
443
443
444
</tr>
444
</tr>
445
445
446
<tr><td>PM_DATA_FROM_L2</td><td>  The processor's data cache was reloaded from local core's L2 due to a demand load or demand load plus prefetch controlled by MMCR1[20]. </td><td> 0</td><td>
446
<tr><td>PM_DATA_FROM_L2</td><td>        load plus prefetch controlled by MMCR1[20]. </td><td> 0</td><td>
447
</td>
448
449
</tr>
447
</td>
450
448
451
<tr><td>PM_DATA_FROM_L2_NO_CONFLICT</td><td>  The processor's data cache was reloaded from local core's L2 without conflict due to a demand load or demand load plus prefetch controlled by MMCR1[20] . </td><td> 0</td><td>
452
</td>
449
</tr>
453
450
451
<tr><td>PM_DATA_FROM_L2_NO_CONFLICT</td><td>        demand load or demand load plus prefetch controlled by MMCR1[20] . </td><td> 0</td><td>
454
</tr>
452
</td>
455
453
456
<tr><td>PM_DATA_FROM_L3</td><td>  The processor's data cache was reloaded from local core's L3 due to a demand load. </td><td> 3</td><td>
457
</td>
454
</tr>
458
455
456
<tr><td>PM_DATA_FROM_L3</td><td>        demand load or demand load plus prefetch controlled by MMCR1[20] . </td><td> 3</td><td>
459
</tr>
457
</td>
460
458
461
<tr><td>PM_DATA_FROM_L3MISS_MOD</td><td>  The processor's data cache was reloaded from a localtion other than the local core's L3 due to a demand load. </td><td> 3</td><td>
462
</td>
459
</tr>
463
460
461
<tr><td>PM_DATA_FROM_L3MISS_MOD</td><td>        to a demand load. </td><td> 3</td><td>
464
</tr>
462
</td>
465
463
466
<tr><td>PM_DATA_FROM_L3_NO_CONFLICT</td><td>  The processor's data cache was reloaded from local core's L3 without conflict due to a demand load or demand load plus prefetch controlled by MMCR1[20]. </td><td> 0</td><td>
467
</td>
464
</tr>
468
465
466
<tr><td>PM_DATA_FROM_L3_NO_CONFLICT</td><td>        demand load or demand load plus prefetch controlled by MMCR1[20]. </td><td> 0</td><td>
469
</tr>
467
</td>
470
468
471
<tr><td>PM_DATA_FROM_LMEM</td><td>    The processor's data cache was reloaded from the local chip's Memory due to a demand load. </td><td> 1</td><td>
472
</td>
469
</tr>
473
470
471
<tr><td>PM_DATA_FROM_LMEM</td><td>        </td><td> 1</td><td>
474
</tr>
472
</td>
475
473
476
<tr><td>PM_DATA_FROM_MEMORY</td><td>  The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load. </td><td> 1</td><td>
477
</td>
474
</tr>
478
475
476
<tr><td>PM_DATA_FROM_MEMORY</td><td>        remote or distant due to a demand load. </td><td> 1</td><td>
479
</tr>
477
</td>
480
478
481
<tr><td>PM_DC_PREF_STREAM_STRIDED_CONF</td><td>   A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.. </td><td> 2</td><td>
479
</tr>
480
481
<tr><td>PM_DC_PREF_STREAM_STRIDED_CONF</td><td></td><td> 2</td><td>
482
</td>
482
</td>
483
483
484
</tr>
484
</tr>
485
485
486
<tr><td>PM_GCT_NOSLOT_BR_MPRED</td><td> Gct empty fo this thread due to branch mispred. </td><td> 3</td><td>
486
<tr><td>PM_GCT_NOSLOT_BR_MPRED</td><td> Gct empty fo this thread due to branch mispred. </td><td> 3</td><td>
...
...
491
<tr><td>PM_GCT_NOSLOT_BR_MPRED_ICMISS</td><td>  Gct empty fo this thread due to Icache Miss and branch mispred. </td><td> 3</td><td>
491
<tr><td>PM_GCT_NOSLOT_BR_MPRED_ICMISS</td><td>  Gct empty fo this thread due to Icache Miss and branch mispred. </td><td> 3</td><td>
492
</td>
492
</td>
493
493
494
</tr>
494
</tr>
495
495
496
<tr><td>PM_GCT_NOSLOT_DISP_HELD_ISSQ</td><td>   Gct empty fo this thread due to dispatch hold on this thread due to Issue q full. </td><td> 1</td><td>
496
<tr><td>PM_GCT_NOSLOT_DISP_HELD_ISSQ</td><td>   Gct empty fo this thread due to Icache Miss and branch mispred. </td><td> 1</td><td>
497
</td>
498
499
</tr>
497
</td>
500
498
501
<tr><td>PM_GCT_NOSLOT_DISP_HELD_OTHER</td><td>    Gct empty fo this thread due to dispatch hold on this thread due to sync. </td><td> 1</td><td>
502
</td>
499
</tr>
503
500
501
<tr><td>PM_GCT_NOSLOT_DISP_HELD_OTHER</td><td></td><td> 1</td><td>
504
</tr>
502
</td>
505
503
506
<tr><td>PM_GCT_NOSLOT_DISP_HELD_SRQ</td><td>  Gct empty fo this thread due to dispatch hold on this thread due to SRQ full. </td><td> 1</td><td>
504
</tr>
505
506
<tr><td>PM_GCT_NOSLOT_DISP_HELD_SRQ</td><td></td><td> 1</td><td>
507
</td>
507
</td>
508
508
509
</tr>
509
</tr>
510
510
511
<tr><td>PM_GCT_NOSLOT_IC_L3MISS</td><td>    Gct empty fo this thread due to icach l3 miss. </td><td> 3</td><td>
511
<tr><td>PM_GCT_NOSLOT_IC_L3MISS</td><td>    Gct empty fo this thread due to icach l3 miss. </td><td> 3</td><td>
...
...
550
<tr><td>PM_LD_L3MISS_PEND_CYC</td><td>  Cycles L3 miss was pending for this thread. </td><td> 0</td><td>
550
<tr><td>PM_LD_L3MISS_PEND_CYC</td><td>  Cycles L3 miss was pending for this thread. </td><td> 0</td><td>
551
</td>
551
</td>
552
552
553
</tr>
553
</tr>
554
554
555
<tr><td>PM_MRK_DATA_FROM_L2</td><td>  The processor's data cache was reloaded from local core's L2 due to a marked load. </td><td> 0</td><td>
555
<tr><td>PM_MRK_DATA_FROM_L2</td><td>  Cycles L3 miss was pending for this thread. </td><td> 0</td><td>
556
</td>
557
558
</tr>
556
</td>
559
557
560
<tr><td>PM_MRK_DATA_FROM_L2MISS_CYC</td><td>  Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load. </td><td> 3</td><td>
558
</tr>
559
560
<tr><td>PM_MRK_DATA_FROM_L2MISS_CYC</td><td>        marked load. </td><td> 3</td><td>
561
</td>
561
</td>
562
562
563
</tr>
563
</tr>
564
564
565
<tr><td>PM_MRK_DATA_FROM_L2_CYC</td><td>    Duration in cycles to reload from local core's L2 due to a marked load. </td><td> 3</td><td>
565
<tr><td>PM_MRK_DATA_FROM_L2_CYC</td><td>    Duration in cycles to reload from local core's L2 due to a marked load. </td><td> 3</td><td>
566
</td>
566
</td>
567
567
568
</tr>
568
</tr>
569
569
570
<tr><td>PM_MRK_DATA_FROM_L2_NO_CONFLICT</td><td>  The processor's data cache was reloaded from local core's L2 without conflict due to a marked load. </td><td> 0</td><td>
570
<tr><td>PM_MRK_DATA_FROM_L2_NO_CONFLICT</td><td>        marked load. </td><td> 0</td><td>
571
</td>
572
573
</tr>
571
</td>
574
572
575
<tr><td>PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC</td><td>  Duration in cycles to reload from local core's L2 without conflict due to a marked load. </td><td> 3</td><td>
576
</td>
573
</tr>
577
574
575
<tr><td>PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC</td><td>        </td><td> 3</td><td>
578
</tr>
576
</td>
579
577
580
<tr><td>PM_MRK_DATA_FROM_L3</td><td>  The processor's data cache was reloaded from local core's L3 due to a marked load. </td><td> 3</td><td>
581
</td>
578
</tr>
582
579
580
<tr><td>PM_MRK_DATA_FROM_L3</td><td>        </td><td> 3</td><td>
583
</tr>
581
</td>
584
582
585
<tr><td>PM_MRK_DATA_FROM_L3MISS_CYC</td><td>  Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load. </td><td> 1</td><td>
583
</tr>
584
585
<tr><td>PM_MRK_DATA_FROM_L3MISS_CYC</td><td>        marked load. </td><td> 1</td><td>
586
</td>
586
</td>
587
587
588
</tr>
588
</tr>
589
589
590
<tr><td>PM_MRK_DATA_FROM_L3_CYC</td><td>    Duration in cycles to reload from local core's L3 due to a marked load. </td><td> 1</td><td>
590
<tr><td>PM_MRK_DATA_FROM_L3_CYC</td><td>    Duration in cycles to reload from local core's L3 due to a marked load. </td><td> 1</td><td>
591
</td>
591
</td>
592
592
593
</tr>
593
</tr>
594
594
595
<tr><td>PM_MRK_DATA_FROM_L3_NO_CONFLICT</td><td>  The processor's data cache was reloaded from local core's L3 without conflict due to a marked load. </td><td> 0</td><td>
595
<tr><td>PM_MRK_DATA_FROM_L3_NO_CONFLICT</td><td>        marked load. </td><td> 0</td><td>
596
</td>
597
598
</tr>
596
</td>
599
597
600
<tr><td>PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC</td><td>  Duration in cycles to reload from local core's L3 without conflict due to a marked load. </td><td> 3</td><td>
601
</td>
598
</tr>
602
599
600
<tr><td>PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC</td><td>        </td><td> 3</td><td>
603
</tr>
601
</td>
604
602
605
<tr><td>PM_MRK_DATA_FROM_LL4</td><td> The processor's data cache was reloaded from the local chip's L4 cache due to a marked load. </td><td> 0</td><td>
606
</td>
603
</tr>
607
604
605
<tr><td>PM_MRK_DATA_FROM_LL4</td><td>        load. </td><td> 0</td><td>
608
</tr>
606
</td>
609
607
610
<tr><td>PM_MRK_DATA_FROM_LL4_CYC</td><td> Duration in cycles to reload from the local chip's L4 cache due to a marked load. </td><td> 3</td><td>
611
</td>
608
</tr>
612
609
610
<tr><td>PM_MRK_DATA_FROM_LL4_CYC</td><td>        load. </td><td> 3</td><td>
613
</tr>
611
</td>
614
612
615
<tr><td>PM_MRK_DATA_FROM_LMEM</td><td>    The processor's data cache was reloaded from the local chip's Memory due to a marked load. </td><td> 1</td><td>
616
</td>
613
</tr>
617
614
615
<tr><td>PM_MRK_DATA_FROM_LMEM</td><td>        </td><td> 1</td><td>
618
</tr>
616
</td>
619
617
620
<tr><td>PM_MRK_DATA_FROM_LMEM_CYC</td><td>    Duration in cycles to reload from the local chip's Memory due to a marked load. </td><td> 3</td><td>
621
</td>
618
</tr>
622
619
620
<tr><td>PM_MRK_DATA_FROM_LMEM_CYC</td><td>        </td><td> 3</td><td>
623
</tr>
621
</td>
624
622
625
<tr><td>PM_MRK_DATA_FROM_MEMORY</td><td>  The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load. </td><td> 1</td><td>
626
</td>
623
</tr>
627
624
625
<tr><td>PM_MRK_DATA_FROM_MEMORY</td><td>        remote or distant due to a marked load. </td><td> 1</td><td>
628
</tr>
626
</td>
629
627
630
<tr><td>PM_MRK_DATA_FROM_MEMORY_CYC</td><td>  Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load. </td><td> 3</td><td>
628
</tr>
629
630
<tr><td>PM_MRK_DATA_FROM_MEMORY_CYC</td><td>        distant due to a marked load. </td><td> 3</td><td>
631
</td>
631
</td>
632
632
633
</tr>
633
</tr>
634
634
635
<tr><td>PM_MRK_GRP_CMPL</td><td>    marked instruction finished (completed). </td><td> 3</td><td>
635
<tr><td>PM_MRK_GRP_CMPL</td><td>    marked instruction finished (completed). </td><td> 3</td><td>

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