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# op_events.exp
#   Copyright (C) 2006 Red Hat, Inc.
#
# This file is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
#


# the "comprehensive" tables are not presently very much used, but were
# used in previous incarnations of the testsuite and may be used again.
#
# they describe quite a lot, though not necesarily *all* events, their
# unit masks, counts, and counters they run on.  these are used for
# "breadth" tests. FP events have been left out since our cycle-soaking
# routine doesn't necessarily use the FPU much.
#
# the form of the table rows is:
#
#  { COUNTER   EVENT    UNIT_MASK   COUNT }
#
# where each entry may include a sub-list of choices in braces, which
# will be expanded (cartesian-product wise) to describe all variations,
# so for example {a {b c} {d e} f} is equivalent to the set:
#
# {a b d f}
# {a b e f}
# {a c d f}
# {a b e f}
#

if {! [array exists op_event_table]} {
    array set op_event_table {}
}

if {! [array exists op_comprehensive_event_table]} {
    array set op_comprehensive_event_table {}
}


set op_comprehensive_event_table(ppro)                     \
    {                                                      \
	 {{0 1} {                                          \
		     INST_RETIRED         UOPS_RETIRED     \
		     INST_DECODED         CPU_CLK_UNHALTED \
		 }                      0            7000} \
	 {{0 1} {                                          \
		     DATA_MEM_REFS        DCU_LINES_IN     \
		     DCU_M_LINES_IN       DCU_M_LINES_OUT  \
		     DCU_MISS_OUTSTANDING IFU_IFETCH       \
		     IFU_IFETCH_MISS      ITLB_MISS        \
		     IFU_MEM_STALL        ILD_STALL        \
		     L2_LINES_IN          L2_LINES_OUT     \
		     L2_M_LINES_INM       L2_LINES_OUTM    \
		     L2_DBUS_BUSY         L2_DBUS_BUSY_RD  \
		     BUS_DATA_RCV         BUS_BNR_DRV      \
		     BUS_HIT_DRV          BUS_HITM_DRV     \
		     BUS_SNOOP_STALL      LD_BLOCKS        \
		     SB_DRAINS            MISALIGN_MEM_REF \
		     BR_INST_RETIRED      BR_TAKEN_RETIRED \
		     BR_MISS_PRED_RETIRED                  \
		     BR_MISS_PRED_TAKEN_RET                \
		     BR_INST_DECODED      BTB_MISSES       \
		     BR_BOGUS             RESOURCE_STALLS  \
		     PARTIAL_RAT_STALLS                    \
		 }                      0            7000} \
	 {{0 1} {\
		     L2_IFETCH            L2_LD            \
		     L2_ST                L2_RQSTS         \
		 }                      {8 4 2 1 f}  7000} \
	 {{0 1} {\
		     BUS_DRDY_CLOCKS      BUS_LOCK_CLOCKS  \
		     BUS_TRAN_BRD         BUS_TRAN_RFO     \
		     BUS_TRANS_WB         BUS_TRAN_IFETCH  \
		     BUS_TRAN_INVAL       BUS_TRAN_PWR     \
		     BUS_TRAN_BRD         BUS_TRANS_P      \
		     BUS_TRANS_IO         BUS_TRANS_DEF    \
		     BUS_TRAN_BURST       BUS_TRAN_ANY     \
		     BUS_TRAN_MEM                          \
		 }                      {0 2}        7000} \
     }


set op_comprehensive_event_table(athlon) \
    {\
	 {{0 1 2 3} {                                       \
		     RETIRED_BRANCHES             RETIRED_BRANCHES_MISPREDICTED        \
		     RETIRED_TAKEN_BRANCHES       RETIRED_TAKEN_BRANCHES_MISPREDICTED  \
		     L1_DTLB_MISSES_L2_DTLD_HITS  L1_AND_L2_DTLB_MISSES                \
		     MISALIGNED_DATA_REFS         L1_ITLB_MISSES_L2_ITLB_HITS          \
		     L1_AND_L2_ITLB_MISSES        RETIRED_FAR_CONTROL_TRANSFERS        \
		     RETIRED_RESYNC_BRANCHES      RETIRED_OPS                          \
		     ICACHE_FETCHES               ICACHE_MISSES                        \
		     DATA_CACHE_ACCESSES          DATA_CACHE_MISSES                    \
		     }                  0                    7000} \
	 {{0 1 2 3} {\
		     DATA_CACHE_REFILLS_FROM_L2   DATA_CACHE_REFILLS_FROM_SYSTEM       \
		     }                  {1 2 4 8 10 1f}      7000} \
     }


set op_comprehensive_event_table(p4) \
    {\
	 {{3 7} BRANCH_RETIRED         {1 2 4 8}             7000} \
	 {{3 7} MISPRED_BRANCH_RETIRED 1                     7000} \
	 {{0 4} BPU_FETCH_REQUEST      1                     7000} \
	 {{0 4} ITLB_REFERENCE         {1 2}                 7000} \
	 {{2 6} MEMORY_CANCEL          {4 8}                 7000} \
	 {{2 6} LOAD_PORT_REPLAY       2                     7000} \
	 {{0 4} MOB_LOAD_REPLAY        {2 8 10 20}           7000} \
	 {{0 4} BSQ_CACHE_REFERENCE    {1 2 4 100}           7000} \
	 {{0 4} GLOBAL_POWER_EVENTS    1                   100000} \
	 {{1 5} TC_MS_XFER             1                     7000} \
	 {{1 5} UOP_QUEUE_WRITES       {1 2 4}             100000} \
	 {{3 7} INSTR_RETIRED          {1 4}               100000} \
	 {{1 5} RETIRED_MISPRED_BRANCH_TYPE {2 8 10}         7000} \
	 {{1 5} RETIRED_BRANCH_TYPE    {2 4 8 10}            7000} \
     }

# the normal event table is just for smoke tests, and contains un-factored
# specifications of testcases. each innermost group of event lines
# represents a single testcase. so in these CPUs there's 2 testcases per
# CPU. it's not much, but then, that makes it somewhat easier to run and
# less likely to fail.
#
# The symbol check test only uses the first event group when collecting data
# to check for a symbol.  It is best that the first event group contain an
# event such as CYCLES or count instructions which will reliably collect
# a significant number of samples.

set op_event_table(ppro)                            \
    {                                               \
	{                                           \
	     {0 INST_RETIRED      0 500000}         \
	     {1 CPU_CLK_UNHALTED  0 500000}         \
	}                                           \
	{                                           \
	     {0 L2_RQSTS          0xf 500000}       \
	     {1 DATA_MEM_REFS     0 500000}         \
	}                                           \
    }

set op_event_table(core2)                           \
    {                                               \
	{                                           \
	     {0 INST_RETIRED      0 500000}         \
	     {1 CPU_CLK_UNHALTED  0 500000}         \
	}                                           \
	{                                           \
	     {0 L2_LINES_IN       0 500}            \
	     {1 L2_LINES_OUT      0 500}            \
	}                                           \
    }

set op_event_table(arch_perf)                       \
    {                                               \
	{                                           \
	     {0 INST_RETIRED      0 500000}         \
	     {1 CPU_CLK_UNHALTED  0 500000}         \
	}                                           \
	{                                           \
	     {0 LLC_MISSES        0x41 10000}       \
	     {1 LLC_REFS          0x4f 10000}       \
	}                                           \
	{                                           \
	     {0 BR_INST_RETIRED   0 500000}         \
	     {1 BR_MISS_PRED_RETIRED 0 50000}       \
	}                                           \
    }

set op_event_table(sandybridge)                     \
    {                                               \
	{                                           \
	     {0 INST_RETIRED      0 500000}         \
	     {1 CPU_CLK_UNHALTED  0 500000}         \
	}                                           \
	{                                           \
	     {0 LLC_MISSES        0x41 10000}       \
	     {1 LLC_REFS          0x4f 10000}       \
	}                                           \
	{                                           \
	     {0 BR_INST_RETIRED   0 500000}         \
	     {1 BR_MISS_PRED_RETIRED 0 50000}       \
	}                                           \
	{                                           \
	     {0 uops_issued stall_cycles 2000003}   \
	     {1 uops_retired stall_cycles 2000003}  \
	}                                           \
    }

set op_event_table(athlon)                          \
    {                                               \
	{                                           \
	     {0 CPU_CLK_UNHALTED  0 500000}         \
	     {1 DATA_CACHE_ACCESSES 0 500000}       \
	}                                           \
	{                                           \
	     {0 DATA_CACHE_ACCESSES   0 500000}     \
	     {1 DATA_CACHE_MISSES     0 500000}     \
	}                                           \
    }

set op_event_table(p4)                              \
    {                                               \
	{                                           \
	    {0 GLOBAL_POWER_EVENTS  1 500000}       \
	    {3 INSTR_RETIRED        1 500000}       \
	}                                           \
	{                                           \
	    {0 BSQ_CACHE_REFERENCE  1 500000}       \
	    {4 BRANCH_RETIRED       0xc 500000}     \
	}                                           \
    }

set op_event_table(ia64)                            \
    {                                               \
	{                                           \
	    {0 CPU_CYCLES           0 500000}       \
	    {1 IA64_INST_RETIRED    0 500000}       \
	}                                           \
	{                                           \
	    {2 CPU_CYCLES           0 500000}       \
	    {3 IA64_INST_RETIRED    0 500000}       \
	}                                           \
    }

#Nothing for the Alpha right now
set op_event_table(alpha)                           \
    {                                               \
    }

set op_event_table(gen_arm)                         \
    {                                               \
	{                                           \
	     {1 INSN_EXECUTED     0 500000}         \
	     {0 CPU_CYCLES        0 500000}         \
	}                                           \
	{                                           \
	     {0 DCACHE_MISS       0 500000}         \
	     {1 DCACHE_ACCESS     0 500000}         \
	}                                           \
    }

set op_event_table(arm7)                            \
    {                                               \
	{                                           \
	     {1 INST_RETIRED      0 500000}         \
	     {0 CPU_CYCLES        0 500000}         \
	}                                           \
	{                                           \
	     {0 L1D_CACHE_REFILL  0 500000}         \
	     {1 L1D_CACHE         0 500000}         \
	}                                           \
    }

set op_event_table(power4)                          \
    {                                               \
	{                                           \
	    {1 CYCLES 0 500000}                     \
	}                                           \
	{                                           \
	    {0 PM_RUN_CYC_GRP1 0 500000}            \
	    {1 PM_CYC_GRP1 0 500000}                \
	    {3 PM_INST_CMPL_GRP1 0 500000}          \
	}                                           \
	{                                           \
	    {0 PM_INST_CMPL_GRP4 0 500000}          \
	    {1 PM_BIQ_IDU_FULL_CYC_GRP4 0 500000}   \
	    {2 PM_BR_ISSUED_GRP4 0 500000}          \
	    {3 PM_BR_MPRED_CR_GRP4 0 500000}        \
	    {4 PM_INST_FETCH_CYC_GRP4 0 500000}     \
	    {5 PM_CYC_GRP4 0 500000}                \
	    {6 PM_BR_MPRED_TA_GRP4 0 500000}        \
	    {7 PM_L1_WRITE_CYC_GRP4 0 500000}       \
	}                                           \
    }

set op_event_table(power5)                          \
    {                                               \
	{                                           \
	    {3 CYCLES 0 500000}                     \
	}                                           \
	{                                           \
	    {0 PM_BR_UNCOND_GRP42 0 500000}         \
	    {1 PM_BR_PRED_TA_GRP42 0 500000}        \
	    {2 PM_BR_PRED_CR_GRP42 0 500000}        \
	    {3 PM_BR_PRED_CR_TA_GRP42 0 500000}     \
	    {4 PM_INST_CMPL_GRP42 0 500000}         \
	    {5 PM_RUN_CYC_GRP42 0 500000}           \
	}                                           \
    }

set op_event_table(power5p)                         \
    {                                               \
	{                                           \
	    {3 CYCLES 0 500000}                     \
	}                                           \
	{                                           \
	    {0 PM_BR_UNCOND_GRP43 0 500000}         \
	    {1 PM_BR_PRED_TA_GRP43 0 500000}        \
	    {2 PM_BR_PRED_CR_GRP43 0 500000}        \
	    {3 PM_BR_PRED_CR_TA_GRP43 0 500000}     \
	    {4 PM_RUN_INST_CMPL_GRP43 0 500000}     \
	    {5 PM_RUN_CYC_GRP43 0 500000}           \
	}                                           \
    }

set op_event_table(power5pp)                        \
    {                                               \
	{                                           \
	    {1 CYCLES 0 500000}                     \
	}                                           \
	{                                           \
	    {0 PM_BR_UNCOND_GRP43 0 500000}         \
	    {1 PM_BR_PRED_TA_GRP43 0 500000}        \
	    {2 PM_BR_PRED_CR_GRP43 0 500000}        \
	    {3 PM_BR_PRED_CR_TA_GRP43 0 500000}     \
	}                                           \
    }

set op_event_table(ppc970)                          \
    {                                               \
	{                                           \
	    {1 CYCLES 0 500000}                     \
	}                                           \
	{                                           \
	    {0 PM_RUN_CYC_GRP1 0 500000}            \
	    {1 PM_CYC_GRP1 0 500000}                \
	    {3 PM_INST_CMPL_GRP1 0 500000}          \
	}                                           \
	{                                           \
	    {0 PM_INST_CMPL_GRP25 0 500000}         \
	    {1 PM_CYC_GRP25 0 500000}               \
	    {2 PM_LD_MISS_L1_GRP25 0 500000}        \
	    {3 PM_BR_ISSUED_GRP25 0 500000}         \
	    {4 PM_LSU0_BUSY_GRP25 0 500000}         \
	    {5 PM_CYC_GRP25 0 500000}               \
	    {6 PM_BR_MPRED_CR_GRP25 0 500000}       \
	    {7 PM_BR_MPRED_TA_GRP25 0 500000}       \
	}                                           \
    }

set op_event_table(power6)                          \
    {                                               \
	{                                           \
	    {3 CYCLES 0 500000}                     \
	}                                           \
	{                                           \
	    {0 PM_RUN_CYC_GRP1 0 500000}            \
	    {1 PM_INST_CMPL_GRP1 0 500000}          \
	    {3 PM_CYC_GRP1 0 500000}                \
	}                                           \
	{                                           \
	    {0 PM_BR_PRED_CR_GRP3 0 500000}         \
	    {1 PM_BR_MPRED_CR_GRP3 0 500000}        \
	    {2 PM_BR_PRED_GRP3  0 500000}           \
	    {3 PM_BR_MPRED_COUNT_GRP3 0 500000}     \
	}                                           \
    }

set op_event_table(power7)                          \
    {                                               \
	{                                           \
	    {0 CYCLES 0 500000}                     \
	}                                           \
	{                                           \
	    {0 PM_BR_PRED_GRP3 0 500000}            \
	    {1 PM_BR_PRED_CR_GRP3 0 50000}         \
	    {3 PM_BR_PRED_LSTACK_GRP3 0 50000}     \
	    {4 PM_RUN_INST_CMPL_GRP3 0 500000}      \
	    {5 PM_RUN_CYC_GRP3  0 500000}           \
	}                                           \
    }

set op_event_table(power8)                          \
    {                                               \
	{                                           \
	    {0 CYCLES 0 500000}                     \
	}                                           \
	{                                           \
	    {0 PM_BR_CMPL 0 100000}            \
	    {1 PM_BR_TAKEN_CMPL 0 100000}         \
	    {3 PM_GRP_DISP 0 100000}     \
	    {4 PM_RUN_INST_CMPL 0 500000}      \
	    {5 PM_RUN_CYC  0 500000}           \
	}                                           \
    }

set op_event_table(ibm_compat_v1)                   \
    {                                               \
	{                                           \
	    {2 CYCLES 0 500000}                     \
	}                                           \
	{                                           \
	    {0 PM_DATA_FROM_L1-5_GRP3 0 500000}     \
	    {1 PM_DATA_FROM_L2MISS_GRP3 0 500000}   \
	    {2 PM_DATA_FROM_L3MISS_GRP3 0 500000}   \
	    {3 PM_RUN_INST_CMPL_GRP3 0 500000}      \
	}                                           \
    }

set op_event_table(cell_be)                         \
    {                                               \
	{                                           \
	    {0 CYCLES 0 500000}                     \
	}                                           \
	{                                           \
	    {0 CYCLES 0 500000}                     \
	    {1 SPU_CYCLES 0 500000}                 \
	}                                           \
	{                                           \
	    {0 Branch_Commit 0 500000}              \
	    {1 Branch_Flush 0 500000}               \
	    {2 IL1_Miss_Cycles 0 500000}            \
	    {3 PPC_Commit 0 500000}                 \
	}                                           \
    }

set op_event_table(pa6t)                            \
    {                                               \
	{                                           \
	    {0 CYCLES 0 500000}                     \
	}                                           \
	    {0 CYCLES 0 500000}                     \
	    {3 ISS_CYCLES 0 500000}                 \
	    {4 RET_UOP 0 500000}                    \
	{                                           \
	    {0 GRP3_CYCLES 0 500000}                \
	    {1 GRP3_INST_RETIRED 0 500000}          \
	    {2 GRP3_NXT_LINE_MISPRED__NS 0 500000}  \
	    {3 GRP3_DIRN_MISPRED__NS 0 500000}      \
	    {4 GRP3_TGT_ADDR_MISPRED__NS 0 500000}  \
	    {5 GRP3_BRA_TAKEN__NS 0 500000}         \
	}                                           \
    }

#Placeholder for rtc (shouldn't be used in tests)
set op_event_table(rtc)                             \
    {                                               \
	{                                           \
	}                                           \
    }

#Placeholder for timer
set op_event_table(timer)                           \
    {                                               \
	{                                           \
	}                                           \
    }

#Placeholder for mips based
set op_event_table(mips)                            \
    {                                               \
	{                                           \
	}                                           \
    }

#Placeholder for ppc e500 based
set op_event_table(e500)                            \
    {                                               \
	{                                           \
	}                                           \
    }

#Placeholder for ppc 7450 based
set op_event_table(ppc7450)                         \
    {                                               \
	{                                           \
	}                                           \
    }

#Placeholder for avr32 based
set op_event_table(avr32)                           \
    {                                               \
	{                                           \
	}                                           \
    }

proc select_cpu_events {cpu_name} {


    verbose "cpu name string is $cpu_name"

    set type bogus

    switch -exact "$cpu_name" {
	0 {set type ppro}
	i386/ppro {set type ppro}
	Pentium_Pro {set type ppro}
	1 {set type ppro}
	i386/pii {set type ppro}
	PII {set type ppro}
	2 {set type ppro}
	i386/piii {set type ppro}
	PIII {set type ppro}
	3 {set type athlon}
	i386/athlon {set type athlon}
	Athlon {set type athlon}
	4 {set type timer}
	timer {set type timer}
	5 {set type rtc}
	rtc {set type rtc}
	6 {set type p4}
	i386/p4 {set type p4}
	P4_/_Xeon {set type p4}
	7 {set type ia64}
	ia64/ia64 {set type ia64}
	IA64 {set type ia64}
	8 {set type ia64}
	ia64/itanium {set type ia64}
	Itanium {set type ia64}
	9 {set type ia64}
	ia64/itanium2 {set type ia64}
	Itanium_2 {set type ia64}
	10 {set type athlon}
	x86-64/hammer {set type athlon}
	AMD64_processors {set type athlon}
	11 {set type p4}
	i386/p4-ht {set type p4}
	P4_/_Xeon_with_2_hyper-threads {set type p4}
	12 {set type alpha}
	alpha/ev4 {set type alpha}
	Alpha_EV4 {set type alpha}
	13 {set type alpha}
	alpha/ev5 {set type alpha}
	Alpha_EV5 {set type alpha}
	14 {set type alpha}
	alpha/pca56 {set type alpha}
	Alpha_PCA56 {set type alpha}
	15 {set type alpha}
	alpha/ev6 {set type alpha}
	Alpha_EV6 {set type alpha}
	16 {set type alpha7}
	alpha/ev67 {set type alpha}
	AlphaEV_67 {set type alpha}
	17 {set type ppro}
	i386/p6_mobile {set type ppro}
	Pentium_M_(P6_core) {set type ppro}
	18 {set type gen_arm}
	arm/xscale1 {set type gen_arm}
	ARM/XScale_PMU1 {set type gen_arm}
	19 {set type gen_arm}
	arm/xscale2 {set type gen_arm}
	ARM/XScale_PMU2 {set type gen_arm}
	20 {set type power4}
	ppc64/power4 {set type power4}
	ppc64_POWER4 {set type power4}
	21 {set type power5}
	ppc64/power5 {set type power5}
	ppc64_POWER5 {set type power5}
	22 {set type power5p}
	ppc64/power5+ {set type power5p}
	ppc64_POWER5+ {set type power5p}
	23 {set type power970}
	ppc64/970 {set type ppc970}
	ppc64_970 {set type ppc970}
	24 {set type mips}
	mips/20K {set type mips}
	MIPS_20K {set type mips}
	25 {set type mips}
	mips/24K {set type mips}
	MIPS_24K {set type mips}
	26 {set type mips}
	mips/25K {set type mips}
	MIPS_25K {set type mips}
	27 {set type mips}
	mips/34K {set type mips}
	MIPS_34K {set type mips}
	28 {set type mips}
	mips/5K {set type mips}
	MIPS_5K {set type mips}
	29 {set type mips}
	mips/r10000 {set type mips}
	MIPS_R10000 {set type mips}
	30 {set type mips}
	mips/r12000 {set type mips}
	MIPS_R12000 {set type mips}
	31 {set type mips}
	mips/rm7000 {set type mips}
	QED_RM7000 {set type mips}
	32 {set type mips}
	mips/rm9000 {set type mips}
	PMC-Sierra_RM9000 {set type mips}
	33 {set type mips}
	mips/sb1 {set type mips}
	Sibyte_SB1 {set type mips}
	34 {set type mips}
	mips/vr5432 {set type mips}
	NEC_VR5432 {set type mips}
	35 {set type mips}
	mips/vr5500 {set type mips}
	NEC_VR5500 {set type mips}
	36 {set type e500}
	ppc/e500 {set type e500}
	e500 {set type e500}
	37 {set type e500}
	ppc/e500v2 {set type e500}
	e500v2 {set type e500}
	38 {set type ppro}
	i386/core {set type ppro}
	Core_Solo_/_Duo {set type ppro}
	39 {set type ppc7450}
	ppc/7450 {set type ppc7450}
	PowerPC_G4 {set type ppc7450}
	40 {set type core2}
	i386/core_2 {set type core2}
	Core_2 {set type core2}
	41 {set type power6}
	ppc64/power6 {set type power6}
	ppc64_POWER6 {set type power6}
	42 {set type power970}
	ppc64/970MP {set type power970}
	ppc64_970MP {set type power970}
	43 {set type cell_be}
	ppc64/cell-be {set type cell_be}
	ppc64_Cell_Broadband_Engine {set type cell_be}
	44 {set type athlon}
	x86-64/family10 {set type athlon}
	AMD64_family10 {set type athlon}
	45 {set type pa6t}
	ppc64/pa6t {set type pa6t}
	ppc64_PA6T {set type pa6t}
	46 {set type gen_arm}
	arm/mpcore {set type gen_arm}
	ARM_11MPcore {set type gen_arm}
	47 {set type gen_arm}
	arm/armv6 {set type gen_arm}
	ARM_V6_PMU {set type gen_arm}
	48 {set type power5pp}
	ppc64/power5++ {set type power5pp}
	ppc64_POWER5++ {set type power5pp}
	49 {set type e500}
	ppc/e300 {set type e500}
	e300 {set type e500}
	50 {set type avr32}
	avr32 {set type avr32}
	AVR32 {set type avr32}
	51 {set type arm7}
	arm/armv7 {set type arm7}
	ARM_Cortex-A8 {set type arm7}
	52 {set type arch_perf}
	i386/arch_perfmon {set type arch_perf}
	Intel_Architectural_Perfmon {set type arch_perf}
	53  {set type athlon}
	x86-64/family11h {set type athlon}
	AMD64_family11h {set type athlon}
	54 {set type power7}
	ppc64/power7 {set type power7}
	ppc64_POWER7 {set type power7}
	55 {set type ibm_compat_v1}
	ppc64/ibm-compat-v1 {set type ibm_compat_v1}
	ppc64_compat_version_1 {set type ibm_compat_v1}
	56 {set type arch_perf}
	i386/core_i7 {set type arch_perf}
	Intel_Core/i7 {set type arch_perf}
	57 {set type arch_perf}
	i386/atom {set type arch_perf}
	Intel_Atom {set type arch_perf}
	58 {set type mips}
	mips/loongson2 {set type mips}
	Loongson2 {set type mips}
	59 {set type arch_perf}
	i386/nehalem {set type arch_perf}
	Intel_Nehalem_microarchitecture {set type arch_perf}
	60 {set type arm7}
	arm/armv7-ca9 {set type arm7}
	ARM_Cortex-A9 {set type arm7}
	61 {set type mips}
	mips/74K {set type mips}
	MIPS_74K {set type mips}
	62 {set type mips}
	mips/1004K {set type mips}
	MIPS_1004K {set type mips}
	63 {set type athlon}
	x86-64/family14h {set type athlon}
	AMD64_family12h {set type athlon}
	64 {set type athlon}
	x86-64/family14h {set type athlon}
	AMD64_family14h {set type athlon}
	65 {set type athlon}
	x86-64/family15h {set type athlon}
	AMD64_family15h {set type athlon}
	66 {set type arch_perf}
	i386/westmere  {set type arch_perf}
	Intel_Westmere_microarchitecture  {set type arch_perf}
	67 {set type arm7}
	arm/armv7-scorpion {set type arm7}
	ARMv7_Scorpion {set type arm7}
	68 {set type arm7}
	arm/armv7-scorpionmp {set type arm7}
	ARMv7_ScorpionMP {set type arm7}
	69 {set type arch_perf}
	i386/sandybridge {set type sandybridge}
	Intel_Sandy_Bridge_microarchitecture {set type sandybridge}
	70 {set type title64}
	tile/tile64 {set type title64}
	TILE64 {set type title64}
	71 {set type titlepro}
	tile/tilepro {set type titlepro}
	TILEPro {set type titlepro}
	72 {set type titlegx}
	tile/tilegx {set type titlegx}
	TILE-GX {set type titlegx}
	73 {set type z10}
	s390/z10 {set type z10}
	IBM_System_z10 {set type z10}
	74 {set type z196}
	s390/z196 {set type z196}
	IBM_zEnterprize_z196 {set type z196}
	75 {set type ivybridge}
	i386/ivybridge {set type sandybridge}
	Intel_Ivy_Bridge_microarchitecture {set type sandybridge}
	76 {set type arm_arm7}
	arm/armv7-ca5 {set type arm7}
	ARM_Cortex-A5 {set type arm7}
	77 {set type arm7}
	arm/armv7-ca7 {set type arm7}
	ARM_Cortex-A7 {set type arm7}
	78 {set type arm7}
	arm/armv7-ca15 {set type arm7}
	ARM_Cortex-A15 {set type arm7}
	i386/haswell {set type sandybridge}
	Intel_Haswell_microarchitecture {set type sandybridge}
	ppc64/power8 {set type power8}
	ppc64_POWER8 {set type power8}
    }

    verbose "cpu type is $type"
    return $type
}

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