From: Will D. <wil...@ar...> - 2011-01-13 10:30:53
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Cortex-A9 defines event 0x62 as `Main TLB miss stall cycles' but this is missing from the events file. This patch adds the missing event. Reported-by: Ken Werner <ken...@li...> Signed-off-by: Will Deacon <wil...@ar...> --- ChangeLog | 4 ++++ events/arm/armv7-ca9/events | 1 + 2 files changed, 5 insertions(+), 0 deletions(-) diff --git a/ChangeLog b/ChangeLog index 6a399ea..e0ed853 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,7 @@ +2011-01-13 Will Deacon <wil...@ar...> + + * events/arm/armv7-ca9/events: Add missing TLB event + 2011-01-05 William Cohen <wc...@re...> * utils/opcontrol: Add argument checking for numerical arguments diff --git a/events/arm/armv7-ca9/events b/events/arm/armv7-ca9/events index c1e4084..50094b5 100644 --- a/events/arm/armv7-ca9/events +++ b/events/arm/armv7-ca9/events @@ -11,6 +11,7 @@ event:0x51 counters:1,2,3,4,5,6 um:zero minimum:500 name:CO_LF_HIT : Number of c event:0x60 counters:1,2,3,4,5,6 um:zero minimum:500 name:IC_DEP_STALL : Number of cycles where CPU is ready to accept new instructions but does not receive any because of the instruction side not being able to provide any and the instruction cache is currently performing at least one linefill event:0x61 counters:1,2,3,4,5,6 um:zero minimum:500 name:DC_DEP_STALL : Number of cycles where CPU has some instructions that it cannot issue to any pipeline and the LSU has at least one pending linefill request but no pending TLB requests +event:0x62 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_MAIN_TLB : Number of cycles where CPU is stalled waiting for completion of translation table walk from the main TLB event:0x63 counters:1,2,3,4,5,6 um:zero minimum:500 name:STREX_PASS : Number of STREX instructions architecturally executed and passed event:0x64 counters:1,2,3,4,5,6 um:zero minimum:500 name:STREX_FAILS : Number of STREX instructions architecturally executed and failed event:0x65 counters:1,2,3,4,5,6 um:zero minimum:500 name:DATA_EVICT : Number of eviction requests due to a linefill in the data cache -- 1.7.0.4 |
From: Maynard J. <may...@us...> - 2011-01-17 17:16:34
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Will Deacon wrote: > Cortex-A9 defines event 0x62 as `Main TLB miss stall cycles' but > this is missing from the events file. > > This patch adds the missing event. > > Reported-by: Ken Werner <ken...@li...> > Signed-off-by: Will Deacon <wil...@ar...> > --- > ChangeLog | 4 ++++ > events/arm/armv7-ca9/events | 1 + > 2 files changed, 5 insertions(+), 0 deletions(-) > > diff --git a/ChangeLog b/ChangeLog > index 6a399ea..e0ed853 100644 > --- a/ChangeLog > +++ b/ChangeLog > @@ -1,3 +1,7 @@ > +2011-01-13 Will Deacon <wil...@ar...> > + > + * events/arm/armv7-ca9/events: Add missing TLB event > + > 2011-01-05 William Cohen <wc...@re...> > > * utils/opcontrol: Add argument checking for numerical arguments > diff --git a/events/arm/armv7-ca9/events b/events/arm/armv7-ca9/events > index c1e4084..50094b5 100644 > --- a/events/arm/armv7-ca9/events > +++ b/events/arm/armv7-ca9/events > @@ -11,6 +11,7 @@ event:0x51 counters:1,2,3,4,5,6 um:zero minimum:500 name:CO_LF_HIT : Number of c > > event:0x60 counters:1,2,3,4,5,6 um:zero minimum:500 name:IC_DEP_STALL : Number of cycles where CPU is ready to accept new instructions but does not receive any because of the instruction side not being able to provide any and the instruction cache is currently performing at least one linefill > event:0x61 counters:1,2,3,4,5,6 um:zero minimum:500 name:DC_DEP_STALL : Number of cycles where CPU has some instructions that it cannot issue to any pipeline and the LSU has at least one pending linefill request but no pending TLB requests > +event:0x62 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_MAIN_TLB : Number of cycles where CPU is stalled waiting for completion of translation table walk from the main TLB > event:0x63 counters:1,2,3,4,5,6 um:zero minimum:500 name:STREX_PASS : Number of STREX instructions architecturally executed and passed > event:0x64 counters:1,2,3,4,5,6 um:zero minimum:500 name:STREX_FAILS : Number of STREX instructions architecturally executed and failed > event:0x65 counters:1,2,3,4,5,6 um:zero minimum:500 name:DATA_EVICT : Number of eviction requests due to a linefill in the data cache Patch committed. Thanks. -Maynard |