From: Philippe E. <ph...@us...> - 2007-10-19 15:08:41
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Update of /cvsroot/oprofile/oprofile/events/mips/25K In directory sc8-pr-cvs3.sourceforge.net:/tmp/cvs-serv6366/events/mips/25K Modified Files: events Log Message: fix bug #1717298, many mips event number was in decimal but parsed as hexadecimal. Change the code so make check no longer accept decimal notation for field intended to be in hexadecimal. Comment out a bunch of events for mips/34K, they overlap and they does not make sense Index: events =================================================================== RCS file: /cvsroot/oprofile/oprofile/events/mips/25K/events,v retrieving revision 1.1 retrieving revision 1.2 diff -u -p -d -r1.1 -r1.2 --- events 15 Jul 2006 00:24:43 -0000 1.1 +++ events 19 Oct 2007 15:08:38 -0000 1.2 @@ -3,79 +3,79 @@ # # The 25Kf has two performance counters # -event:0 counters:0,1 um:zero minimum:500 name:CYCLES : CPU cycles -event:1 counters:0,1 um:zero minimum:500 name:INSN_ISSUED : Dispatched/issued instructions -event:2 counters:0,1 um:zero minimum:500 name:FP_INSNS_ISSUED : FPU instructions issued -event:3 counters:0,1 um:zero minimum:500 name:INT_INSNS_ISSUED : Integer instructions issued -event:4 counters:0,1 um:zero minimum:500 name:LOAD_INSNS_ISSUED : Load instructions issued -event:5 counters:0,1 um:zero minimum:500 name:STORE_INSNS_ISSUED : Store instructions issued -event:6 counters:0,1 um:zero minimum:500 name:BRANCHES_JUMPS_ISSUED : Branch/Jump instructions issued -event:7 counters:0,1 um:zero minimum:500 name:DUAL_ISSUED_PAIRS : Dual-issued pairs -event:8 counters:0,1 um:zero minimum:500 name:INSNS_COMPLETE : Instruction that completed execution (with or without exception) -event:9 counters:0,1 um:zero minimum:500 name:FETCH_GROUPS_IN_PIPE : Fetch groups entering CPU execution pipes +event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : CPU cycles +event:0x1 counters:0,1 um:zero minimum:500 name:INSN_ISSUED : Dispatched/issued instructions +event:0x2 counters:0,1 um:zero minimum:500 name:FP_INSNS_ISSUED : FPU instructions issued +event:0x3 counters:0,1 um:zero minimum:500 name:INT_INSNS_ISSUED : Integer instructions issued +event:0x4 counters:0,1 um:zero minimum:500 name:LOAD_INSNS_ISSUED : Load instructions issued +event:0x5 counters:0,1 um:zero minimum:500 name:STORE_INSNS_ISSUED : Store instructions issued +event:0x6 counters:0,1 um:zero minimum:500 name:BRANCHES_JUMPS_ISSUED : Branch/Jump instructions issued +event:0x7 counters:0,1 um:zero minimum:500 name:DUAL_ISSUED_PAIRS : Dual-issued pairs +event:0x8 counters:0,1 um:zero minimum:500 name:INSNS_COMPLETE : Instruction that completed execution (with or without exception) +event:0x9 counters:0,1 um:zero minimum:500 name:FETCH_GROUPS_IN_PIPE : Fetch groups entering CPU execution pipes # # FPU: # -event:10 counters:0,1 um:zero minimum:500 name:INSN_FP_DATAPATH_COMPLETED : Instructions completed in FPU datapath (computational instructions only) -event:11 counters:0,1 um:zero minimum:500 name:FP_EXCEPTIONS_TAKEN : Taken FPU exceptions -event:12 counters:0,1 um:zero minimum:500 name:FP_EXCEPTION_PREDICTED : Predicted FPU exceptions +event:0xa counters:0,1 um:zero minimum:500 name:INSN_FP_DATAPATH_COMPLETED : Instructions completed in FPU datapath (computational instructions only) +event:0xb counters:0,1 um:zero minimum:500 name:FP_EXCEPTIONS_TAKEN : Taken FPU exceptions +event:0xc counters:0,1 um:zero minimum:500 name:FP_EXCEPTION_PREDICTED : Predicted FPU exceptions # # Branch/Jump Prediction: # -event:13 counters:0,1 um:zero minimum:500 name:BRANCHES_MISSPREDICTED : Branches that mispredicted before completing execution -event:14 counters:0,1 um:zero minimum:500 name:BRANCHES_COMPLETED : Branches that completed execution -event:15 counters:0,1 um:zero minimum:500 name:JR_RPD_MISSPREDICTED : JR instructions that mispredicted using the Return Prediction Stack -event:16 counters:0,1 um:zero minimum:500 name:JR_COMPLETED : JR instruction that completed execution +event:0xd counters:0,1 um:zero minimum:500 name:BRANCHES_MISSPREDICTED : Branches that mispredicted before completing execution +event:0xe counters:0,1 um:zero minimum:500 name:BRANCHES_COMPLETED : Branches that completed execution +event:0xf counters:0,1 um:zero minimum:500 name:JR_RPD_MISSPREDICTED : JR instructions that mispredicted using the Return Prediction Stack +event:0x10 counters:0,1 um:zero minimum:500 name:JR_COMPLETED : JR instruction that completed execution # # Memory Management: # -event:17 counters:0,1 um:zero minimum:500 name:UTLB_MISSES : U-TLB misses -event:18 counters:0,1 um:zero minimum:500 name:JTLB_MISSES_IFETCH : Raw count of Joint-TLB misses for instruction fetch -event:19 counters:0,1 um:zero minimum:500 name:JTLB_MISSES_LOADS_STORES : Raw count of Joint-TLB misses for loads/stores -event:20 counters:0,1 um:zero minimum:500 name:JTLB_EXCEPTIONS : Refill, Invalid and Modified TLB exceptions +event:0x11 counters:0,1 um:zero minimum:500 name:UTLB_MISSES : U-TLB misses +event:0x12 counters:0,1 um:zero minimum:500 name:JTLB_MISSES_IFETCH : Raw count of Joint-TLB misses for instruction fetch +event:0x13 counters:0,1 um:zero minimum:500 name:JTLB_MISSES_LOADS_STORES : Raw count of Joint-TLB misses for loads/stores +event:0x14 counters:0,1 um:zero minimum:500 name:JTLB_EXCEPTIONS : Refill, Invalid and Modified TLB exceptions # # Machine Check # -event:21 counters:0,1 um:zero minimum:500 name:JTLB_IFETCH_REFILL_EXCEPTIONS : Joint-TLB refill exceptions due to instruction fetch -event:22 counters:0,1 um:zero minimum:500 name:JTLB_DATA_ACCESS_REFILL_EXCEPTIONS : Joint-TLB refill exceptions due to data access -event:23 counters:0,1 um:zero minimum:500 name:JTLB_REFILL_EXCEPTIONS : total Joint-TLB Instruction exceptions (refill) +event:0x15 counters:0,1 um:zero minimum:500 name:JTLB_IFETCH_REFILL_EXCEPTIONS : Joint-TLB refill exceptions due to instruction fetch +event:0x16 counters:0,1 um:zero minimum:500 name:JTLB_DATA_ACCESS_REFILL_EXCEPTIONS : Joint-TLB refill exceptions due to data access +event:0x17 counters:0,1 um:zero minimum:500 name:JTLB_REFILL_EXCEPTIONS : total Joint-TLB Instruction exceptions (refill) # # I-Cache Efficiency: # -event:24 counters:0,1 um:zero minimum:500 name:INSNS_FETCHED_FROM_ICACHE : Total number of instructions fetched from the I-Cache -event:25 counters:0,1 um:zero minimum:500 name:INSN_REQ_FROM_IFU_BIU : instruction requests from the IFU to the BIU -event:26 counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : I-Cache miss +event:0x18 counters:0,1 um:zero minimum:500 name:INSNS_FETCHED_FROM_ICACHE : Total number of instructions fetched from the I-Cache +event:0x19 counters:0,1 um:zero minimum:500 name:INSN_REQ_FROM_IFU_BIU : instruction requests from the IFU to the BIU +event:0x1a counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : I-Cache miss # # D-Cache Efficiency: # -event:27 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : D-Cache miss -event:28 counters:0,1 um:zero minimum:500 name:DCACHE_WRITEBACKS : D-Cache number of write-backs -event:29 counters:0,1 um:zero minimum:500 name:CACHEABLE_DCACHE_REQUEST : number of cacheable requests to D-Cache +event:0x1b counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : D-Cache miss +event:0x1c counters:0,1 um:zero minimum:500 name:DCACHE_WRITEBACKS : D-Cache number of write-backs +event:0x1d counters:0,1 um:zero minimum:500 name:CACHEABLE_DCACHE_REQUEST : number of cacheable requests to D-Cache # # Level 2 Cache Efficiency: # -event:30 counters:0,1 um:zero minimum:500 name:L2_MISSES : L2 Cache miss -event:31 counters:0,1 um:zero minimum:500 name:L2_WBACKS : L2 Cache number of write-backs -event:32 counters:0,1 um:zero minimum:500 name:CACHEABLE_L2_REQS : Number of cacheable requests to L2 +event:0x1e counters:0,1 um:zero minimum:500 name:L2_MISSES : L2 Cache miss +event:0x1f counters:0,1 um:zero minimum:500 name:L2_WBACKS : L2 Cache number of write-backs +event:0x20 counters:0,1 um:zero minimum:500 name:CACHEABLE_L2_REQS : Number of cacheable requests to L2 # # Replays: # -event:33 counters:0,1 um:zero minimum:500 name:REPLAYS_LSU_LOAD_DEP_FPU : LSU requested replays, load-dependent speculative dispatch, FPU exception prediction -event:34 counters:0,1 um:zero minimum:500 name:LSU_REQ_REPLAYS : LSU requested replays -event:35 counters:0,1 um:zero minimum:500 name:REPLAYS_LOAD_DEP_DISPATCH : replays due to load-dependent speculative dispatch -event:36 counters:0,1 um:zero minimum:500 name:REPLAYS_WBB_FULL : replays due to WBB full -event:37 counters:0,1 um:zero minimum:500 name:FSB_FULL_REPLAYS : replays due to FSB full +event:0x21 counters:0,1 um:zero minimum:500 name:REPLAYS_LSU_LOAD_DEP_FPU : LSU requested replays, load-dependent speculative dispatch, FPU exception prediction +event:0x22 counters:0,1 um:zero minimum:500 name:LSU_REQ_REPLAYS : LSU requested replays +event:0x23 counters:0,1 um:zero minimum:500 name:REPLAYS_LOAD_DEP_DISPATCH : replays due to load-dependent speculative dispatch +event:0x24 counters:0,1 um:zero minimum:500 name:REPLAYS_WBB_FULL : replays due to WBB full +event:0x25 counters:0,1 um:zero minimum:500 name:FSB_FULL_REPLAYS : replays due to FSB full # # Misc: # -event:38 counters:0,1 um:zero minimum:500 name:ICACHE_PSEUDO_HITS : I-Cache pseudo-hits -event:39 counters:0,1 um:zero minimum:500 name:LOAD_STORE_ISSUED : Load/store instructions issued +event:0x26 counters:0,1 um:zero minimum:500 name:ICACHE_PSEUDO_HITS : I-Cache pseudo-hits +event:0x27 counters:0,1 um:zero minimum:500 name:LOAD_STORE_ISSUED : Load/store instructions issued |