[oprof-cvs] CVS: oprofile ChangeLog,1.92,1.93 oprofile.c,1.76,1.77

[John L. <mov...@us...>]

Update of /cvsroot/oprofile/oprofile
In directory usw-pr-cvs1:/tmp/cvs-serv14034

Modified Files:
	ChangeLog oprofile.c 
Log Message:
philippe's patch



Index: ChangeLog
===================================================================
RCS file: /cvsroot/oprofile/oprofile/ChangeLog,v
retrieving revision 1.92
retrieving revision 1.93
diff -u -d -r1.92 -r1.93
--- ChangeLog	2001/09/01 02:03:34	1.92
+++ ChangeLog	2001/09/02 00:32:28	1.93
@@ -1,3 +1,10 @@
+2001-09-01  Philippe Elie  <ph...@cl...>
+
+	* oprofile.c: fix pmc_setup()
+
+	* pp/Makefile.in:
+	* dae/Makefile.in: fix uninstall problem
+
 2001-08-31  Philippe Elie  <ph...@cl...>
 
 	* oprofile.h:

Index: oprofile.c
===================================================================
RCS file: /cvsroot/oprofile/oprofile/oprofile.c,v
retrieving revision 1.76
retrieving revision 1.77
diff -u -d -r1.76 -r1.77
--- oprofile.c	2001/09/01 02:03:34	1.76
+++ oprofile.c	2001/09/02 00:32:28	1.77
@@ -441,10 +441,13 @@
 
 	/* Stop and clear all counter: IA32 use bit 22 of eventsel_msr0 to
 	 * enable/disable all counter, AMD use separate bit 22 in each msr,
-	 * all other bits are cleared except the reserved bits 21 */
+	 * all bits are cleared except the reserved bits 21 */
 	for (i = 0 ; i < op_nr_counters ; ++i) {
 		rdmsr(eventsel_msr[i], low, high);
-		wrmsr(eventsel_msr[i], low & ~(3 << 22), high);
+		wrmsr(eventsel_msr[i], low & (1 << 22), high);
+
+		/* avoid a false detection of ctr overflow in NMI handler */
+		wrmsr(perfctr_msr[i], -1, -1);
 	}
 
 	/* setup each counter */
@@ -501,7 +504,8 @@
 	/* this is pretty bogus really. especially as we don't re-enable it.
 	 * Instead, save state set up, and restore with pmc_unsetup or similar */
 #if !defined(CONFIG_X86_UP_APIC) || !defined(OP_EXPORTED_DO_NMI)
-	wrmsr(eventsel_msr[1], low, high);
+	/* PHE FIXME: on my config this start counter 1 with the new code */
+//	wrmsr(eventsel_msr[1], low, high);
 #endif
 }