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From: Philippe Elie <phil_e@us...> - 2007-10-19 15:08:42
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Update of /cvsroot/oprofile/oprofile/events/mips/24K In directory sc8-pr-cvs3.sourceforge.net:/tmp/cvs-serv6366/events/mips/24K Modified Files: events Log Message: fix bug #1717298, many mips event number was in decimal but parsed as hexadecimal. Change the code so make check no longer accept decimal notation for field intended to be in hexadecimal. Comment out a bunch of events for mips/34K, they overlap and they does not make sense Index: events =================================================================== RCS file: /cvsroot/oprofile/oprofile/events/mips/24K/events,v retrieving revision 1.1 retrieving revision 1.2 diff -u -p -d -r1.1 -r1.2 --- events 11 Jul 2005 20:53:55 -0000 1.1 +++ events 19 Oct 2007 15:08:38 -0000 1.2 @@ -5,50 +5,50 @@ # are available on both counters; events 12, 13, 24 - 63 are reserved; # the remaining are counter-specific. # -event:0 counters:0,1 um:zero minimum:500 name:CYCLES : Cycles -event:1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : Instructions completed -event:11 counters:0,1 um:zero minimum:500 name:DCACHE_MISS : Data cache misses -event:22 counters:0,1 um:zero minimum:500 name:L2_MISSES : L2 cache misses +event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Cycles +event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : Instructions completed +event:0x11 counters:0,1 um:zero minimum:500 name:DCACHE_MISS : Data cache misses +event:0x22 counters:0,1 um:zero minimum:500 name:L2_MISSES : L2 cache misses # # Events specific to counter 0 # -event:2 counters:0 um:zero minimum:500 name:BRANCHES_LAUNCHED : Branch instructions launched (whether completed or mispredicted) -event:3 counters:0 um:zero minimum:500 name:JR_31_LAUNCHED : jr r31 (return) instructions launched (whether completed or mispredicted) -event:4 counters:0 um:zero minimum:500 name:JR_NON_31_LAUNCHED : jr (not r31) issues, which cost the same as a mispredict. -event:5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : Instruction micro-TLB accesses -event:6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : Data micro-TLB accesses -event:7 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : Joint TLB instruction accesses -event:8 counters:0 um:zero minimum:500 name:JTLB_INSTRUCTION_ACCESSES : Joint TLB data (non-instruction) accesses -event:9 counters:0 um:zero minimum:500 name:INSTRUCTION_CACHE_ACCESSES : Instruction cache accesses -event:10 counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : Data cache accesses -event:14 counters:0 um:zero minimum:500 name:INTEGER_INSNS_COMPLETED : Integer instructions completed -event:15 counters:0 um:zero minimum:500 name:LOADS_COMPLETED : Loads completed (including FP) -event:16 counters:0 um:zero minimum:500 name:J_JAL_INSNS_COMPLETED : j/jal instructions completed -event:17 counters:0 um:zero minimum:500 name:NOPS_COMPLETED : no-ops completed, ie instructions writing $0 -event:18 counters:0 um:zero minimum:500 name:STALLS : Stalls -event:19 counters:0 um:zero minimum:500 name:SC_COMPLETED : sc instructions completed -event:20 counters:0 um:zero minimum:500 name:PREFETCH_COMPLETED : Prefetch instructions completed -event:21 counters:0 um:zero minimum:500 name:SCACHE_WRITEBACKS : L2 cache writebacks -event:23 counters:0 um:zero minimum:500 name:EXCEPTIONS_TAKEN : Exceptions taken -event:24 counters:0 um:zero minimum:500 name:CACHE_FIXUPS : ``cache fixup'' events (specific to the 24K family microarchitecture). +event:0x2 counters:0 um:zero minimum:500 name:BRANCHES_LAUNCHED : Branch instructions launched (whether completed or mispredicted) +event:0x3 counters:0 um:zero minimum:500 name:JR_31_LAUNCHED : jr r31 (return) instructions launched (whether completed or mispredicted) +event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_LAUNCHED : jr (not r31) issues, which cost the same as a mispredict. +event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : Instruction micro-TLB accesses +event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : Data micro-TLB accesses +event:0x7 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : Joint TLB instruction accesses +event:0x8 counters:0 um:zero minimum:500 name:JTLB_INSTRUCTION_ACCESSES : Joint TLB data (non-instruction) accesses +event:0x9 counters:0 um:zero minimum:500 name:INSTRUCTION_CACHE_ACCESSES : Instruction cache accesses +event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : Data cache accesses +event:0xe counters:0 um:zero minimum:500 name:INTEGER_INSNS_COMPLETED : Integer instructions completed +event:0xf counters:0 um:zero minimum:500 name:LOADS_COMPLETED : Loads completed (including FP) +event:0x10 counters:0 um:zero minimum:500 name:J_JAL_INSNS_COMPLETED : j/jal instructions completed +event:0x11 counters:0 um:zero minimum:500 name:NOPS_COMPLETED : no-ops completed, ie instructions writing $0 +event:0x12 counters:0 um:zero minimum:500 name:STALLS : Stalls +event:0x13 counters:0 um:zero minimum:500 name:SC_COMPLETED : sc instructions completed +event:0x14 counters:0 um:zero minimum:500 name:PREFETCH_COMPLETED : Prefetch instructions completed +event:0x15 counters:0 um:zero minimum:500 name:SCACHE_WRITEBACKS : L2 cache writebacks +event:0x17 counters:0 um:zero minimum:500 name:EXCEPTIONS_TAKEN : Exceptions taken +event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUPS : ``cache fixup'' events (specific to the 24K family microarchitecture). # # Events specific to counter 1 # -event:2 counters:1 um:zero minimum:500 name:BRANCH_MISSPREDICTS : Branch mispredictions -event:3 counters:1 um:zero minimum:500 name:JR_31_MISSPREDICTS : jr r31 (return) mispredictions -event:5 counters:1 um:zero minimum:500 name:ITLB_MISSES : Instruction micro-TLB misses -event:6 counters:1 um:zero minimum:500 name:DTLB_MISSES : Data micro-TLB misses -event:7 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : Joint TLB instruction misses -event:8 counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : Joint TLB data (non-instruction) misses -event:9 counters:1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses -event:10 counters:1 um:zero minimum:500 name:DCACHE_WRITEBACKS : Data cache writebacks -event:14 counters:1 um:zero minimum:500 name:FPU_INSNS_NON_LOAD_STORE_COMPLETED : FPU instructions completed (not including loads/stores) -event:15 counters:1 um:zero minimum:500 name:STORES_COMPLETED : Stores completed (including FP) -event:16 counters:1 um:zero minimum:500 name:MIPS16_INSTRUCTIONS_COMPLETED : MIPS16 instructions completed -event:17 counters:1 um:zero minimum:500 name:INTEGER_MUL_DIV_COMPLETED : integer multiply/divide unit instructions completed -event:18 counters:1 um:zero minimum:500 name:REPLAY_TRAPS_NOT_UTLB : ``replay traps'' (other than micro-TLB related) -event:19 counters:1 um:zero minimum:500 name:SC_COMPLETE_BUT_FAILED : sc instructions completed, but store failed (because the link bit had been cleared). -event:20 counters:1 um:zero minimum:500 name:SUPERFLUOUS_INSTRUCTIONS : ``superfluous'' prefetch instructions (data was already in cache). -event:21 counters:1 um:zero minimum:500 name:SCACHE_ACCESSES : L2 cache accesses +event:0x2 counters:1 um:zero minimum:500 name:BRANCH_MISSPREDICTS : Branch mispredictions +event:0x3 counters:1 um:zero minimum:500 name:JR_31_MISSPREDICTS : jr r31 (return) mispredictions +event:0x5 counters:1 um:zero minimum:500 name:ITLB_MISSES : Instruction micro-TLB misses +event:0x6 counters:1 um:zero minimum:500 name:DTLB_MISSES : Data micro-TLB misses +event:0x7 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : Joint TLB instruction misses +event:0x8 counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : Joint TLB data (non-instruction) misses +event:0x9 counters:1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses +event:0xa counters:1 um:zero minimum:500 name:DCACHE_WRITEBACKS : Data cache writebacks +event:0xe counters:1 um:zero minimum:500 name:FPU_INSNS_NON_LOAD_STORE_COMPLETED : FPU instructions completed (not including loads/stores) +event:0xf counters:1 um:zero minimum:500 name:STORES_COMPLETED : Stores completed (including FP) +event:0x10 counters:1 um:zero minimum:500 name:MIPS16_INSTRUCTIONS_COMPLETED : MIPS16 instructions completed +event:0x11 counters:1 um:zero minimum:500 name:INTEGER_MUL_DIV_COMPLETED : integer multiply/divide unit instructions completed +event:0x12 counters:1 um:zero minimum:500 name:REPLAY_TRAPS_NOT_UTLB : ``replay traps'' (other than micro-TLB related) +event:0x13 counters:1 um:zero minimum:500 name:SC_COMPLETE_BUT_FAILED : sc instructions completed, but store failed (because the link bit had been cleared). +event:0x14 counters:1 um:zero minimum:500 name:SUPERFLUOUS_INSTRUCTIONS : ``superfluous'' prefetch instructions (data was already in cache). +event:0x15 counters:1 um:zero minimum:500 name:SCACHE_ACCESSES : L2 cache accesses |