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[PATCH 2/2] Tweak ARM XScale events
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From: Richard P. <ri...@op...> - 2007-05-24 16:55:16
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Add some extra Xscale PMU event definitions --- ChangeLog | 5 +++++ events/arm/xscale1/events | 8 ++++++-- events/arm/xscale2/events | 8 ++++++-- 3 files changed, 17 insertions(+), 4 deletions(-) Index: oprofile1/events/arm/xscale1/events =================================================================== --- oprofile1.orig/events/arm/xscale1/events 2007-05-24 15:26:26.000000000 +0100 +++ oprofile1/events/arm/xscale1/events 2007-05-24 15:28:44.000000000 +0100 @@ -14,6 +14,10 @@ event:0x0a counters:1,2 um:zero minimum: event:0x0b counters:1,2 um:zero minimum:500 name:DCACHE_MISS : data cache miss event:0x0c counters:1,2 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline event:0x0d counters:1,2 um:zero minimum:500 name:PC_CHANGE : number of times the program counter was changed without a mode switch +event:0x10 counters:1,2 um:zero minimum:500 name:BCU_REQUEST : number of time the BCU received a new memory request from the core +event:0x11 counters:1,2 um:zero minimum:500 name:BCU_FULL : number of cycles the BCUs request queue is full +event:0x12 counters:1,2 um:zero minimum:500 name:BCU_DRAIN : number of times the BCU queues were drained due to a Drain Write Buffer command or an I/O transaction on a non-cacheable and non-bufferable page +event:0x14 counters:1,2 um:zero minimum:500 name:BCU_ECC_NO_ELOG : number of times the BCU detected an ECC error, but no ELOG register was available in which to log the error +event:0x15 counters:1,2 um:zero minimum:500 name:BCU_1_BIT_ERR : number of times the BCU detected a 1-bit error while reading data from the bus +event:0x16 counters:1,2 um:zero minimum:500 name:RMW : number of times an RMW cycle occurred due to narrow write on ECC-protected memory event:0xfe counters:0 um:zero minimum:500 name:CPU_CYCLES : clock cycles counter -#0x10 through 0x17 Defined by ASSP. See the Intel® XScale" core implementation option section of the ASSP -#architecture specification for more details. Index: oprofile1/events/arm/xscale2/events =================================================================== --- oprofile1.orig/events/arm/xscale2/events 2007-05-24 15:26:26.000000000 +0100 +++ oprofile1/events/arm/xscale2/events 2007-05-24 15:28:44.000000000 +0100 @@ -14,6 +14,10 @@ event:0x0a counters:1,2,3,4 um:zero mini event:0x0b counters:1,2,3,4 um:zero minimum:500 name:DCACHE_MISS : data cache miss event:0x0c counters:1,2,3,4 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline event:0x0d counters:1,2,3,4 um:zero minimum:500 name:PC_CHANGE : number of times the program counter was changed without a mode switch +event:0x10 counters:1,2,3,4 um:zero minimum:500 name:BCU_REQUEST : number of time the BCU received a new memory request from the core +event:0x11 counters:1,2,3,4 um:zero minimum:500 name:BCU_FULL : number of cycles the BCUs request queue is full +event:0x12 counters:1,2,3,4 um:zero minimum:500 name:BCU_DRAIN : number of times the BCU queues were drained due to a Drain Write Buffer command or an I/O transaction on a non-cacheable and non-bufferable page +event:0x14 counters:1,2,3,4 um:zero minimum:500 name:BCU_ECC_NO_ELOG : number of times the BCU detected an ECC error, but no ELOG register was available in which to log the error +event:0x15 counters:1,2,3,4 um:zero minimum:500 name:BCU_1_BIT_ERR : number of times the BCU detected a 1-bit error while reading data from the bus +event:0x16 counters:1,2,3,4 um:zero minimum:500 name:RMW : number of times an RMW cycle occurred due to narrow write on ECC-protected memory event:0xfe counters:0 um:zero minimum:500 name:CPU_CYCLES : clock cycles counter -#0x10 through 0x17 Defined by ASSP. See the Intel® XScale" core implementation option section of the ASSP -#architecture specification for more details. Index: oprofile1/ChangeLog =================================================================== --- oprofile1.orig/ChangeLog 2007-05-24 15:28:35.000000000 +0100 +++ oprofile1/ChangeLog 2007-05-24 15:32:20.000000000 +0100 @@ -1,5 +1,10 @@ 2007-05-24 Richard Purdie <rp...@op...> + * events/arm/xscale1/events: + * events/arm/xscale2/events: Add extra Xscale PMU event definitions + +2007-05-24 Richard Purdie <rp...@op...> + * events/arm/armv6/events: * events/arm/armv6/unit_masks: * libop/op_cpu_type.c: |