[oprof-cvs] CVS: oprofile/events/i386/p4-ht unit_masks,1.3,1.4

[Philippe E. <ph...@us...>]

Update of /cvsroot/oprofile/oprofile/events/i386/p4-ht
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv30207/events/i386/p4-ht

Modified Files:
	unit_masks 
Log Message:

P4 support: fix some unit mask
opcontrol: fix default unit mask before trying to validate event
user specified event parsing: don't accept silently invalid input
event file description: warn for unused unit mask (it remains one warning for Itanium2, added to TODO)

Index: unit_masks
===================================================================
RCS file: /cvsroot/oprofile/oprofile/events/i386/p4-ht/unit_masks,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -p -d -r1.3 -r1.4
--- unit_masks	7 Feb 2004 19:26:07 -0000	1.3
+++ unit_masks	10 Feb 2004 03:03:54 -0000	1.4
@@ -1,8 +1,5 @@
 # Pentium IV HyperThreading possible unit masks
 #
-# FIXME: should most of these be mandatory, or have 0x0 listed ?
-name:zero type:mandatory default:0x0
-	0x0 No unit mask
 name:branch_retired type:bitmask default:0x0c
 	0x01 branch not-taken predicted
 	0x02 branch not-taken mispredicted
@@ -16,23 +13,22 @@ name:itlb_reference type:bitmask default
 	0x01 ITLB hit
 	0x02 ITLB miss
 	0x04 uncacheable ITLB hit
-# FIXME: 0x4 | 0x08 != 0x06  ...
-name:memory_cancel type:bitmask default:0x06
+name:memory_cancel type:bitmask default:0x08
 	0x04 replayed because no store request buffer available
 	0x08 conflicts due to 64k aliasing
 name:memory_complete type:bitmask default:0x03
 	0x01 load split completed, excluding UC/WC loads
 	0x02 any split stores completed
-name:load_port_replay type:bitmask default:0x02
+name:load_port_replay type:mandatory default:0x02
 	0x02 split load
-name:store_port_replay type:bitmask default:0x02
+name:store_port_replay type:mandatory default:0x02
 	0x02 split store
 name:mob_load_replay type:bitmask default:0x3a
 	0x02 replay cause: unknown store address
 	0x08 replay cause: unknown store data
 	0x10 replay cause: partial overlap between load and store
 	0x20 replay cause: mismatched low 4 bits between load and store addr
-name:bsq_cache_reference type:bitmask default:0x07ff
+name:bsq_cache_reference type:bitmask default:0x073f
 	0x01 read 2nd level cache hit shared
 	0x02 read 2nd level cache hit exclusive
 	0x04 read 2nd level cache hit modified
@@ -42,37 +38,6 @@ name:bsq_cache_reference type:bitmask de
 	0x100 read 2nd level cache miss
 	0x200 read 3rd level cache miss
 	0x400 writeback lookup from DAC misses 2nd level cache
-name:ioq type:bitmask default:0xefe1
-	0x01 bus request type bit 0
-	0x02 bus request type bit 1
-	0x04 bus request type bit 2
-	0x08 bus request type bit 3
-	0x10 bus request type bit 4
-	0x20 count read entries
-	0x40 count write entries
-	0x80 count UC memory access entries
-	0x100 count WC memory access entries
-	0x200 count write-through memory access entries
-	0x400 count write-protected memory access entries
-	0x800 count WB memory access entries
-# FIXME: 0x1000 ??
-	0x2000 count own store requests
-	0x4000 count other / DMA store requests
-	0x8000 count HW/SW prefetch requests
-name:bsq type:bitmask default:0x21
-	0x01 (r)eq (t)ype (e)ncoding, bit 0: see next event
-	0x02 rte bit 1: 00=read, 01=read invalidate, 10=write, 11=writeback
-	0x04 req len bit 0
-	0x08 req len bit 1
-	0x20 request type is input (0=output)
-	0x40 request type is bus lock
-	0x80 request type is cacheable
-	0x100 request type is 8-byte chunk split across 8-byte boundary
-	0x200 request type is demand (0=prefetch)
-	0x400 request type is ordered
-	0x800 (m)emory (t)ype (e)ncoding, bit 0: see next events
-	0x1000 mte bit 1: see next event
-	0x2000 mte bit 2: 000=UC, 001=USWC, 100=WT, 101=WP, 110=WB
 name:x87_assist type:bitmask default:0x1f
 	0x01 handle FP stack underflow
 	0x02 handle FP stack overflow
@@ -85,7 +50,7 @@ name:machine_clear type:bitmask default:
 	0x80 count cycles machine is cleared due to self modifying code
 name:global_power_events type:mandatory default:0x01
 	0x01 mandatory
-name:tc_ms_xfer type:bitmask default:0x01
+name:tc_ms_xfer type:mandatory default:0x01
 	0x01 count TC to MS transfers
 name:uop_queue_writes type:bitmask default:0x07
 	0x01 count uops written to queue from TC build mode