Hi Jeff,
I access the L2 performance counters on my Cortex-A9 system. however, not with oprofile. 

On my ARM A9 MPCore  system , I run oprofile with a separate driver which I have developed myself in parallel. 

The driver is responsible for configuring the PL310 L2 Cache Controller Performance Monitoring unit and 
enabling required events and reading back their values. 

As of the tests I performed, there is no event (in the list of events that oprofile shows "opcontrol --list-events") 
to count accesses to L2.

Regards.


> From: jeastlac@altera.com
> To: will.deacon@arm.com; maynardj@us.ibm.com
> Date: Mon, 8 Apr 2013 12:08:01 -0700
> Subject: RE: Oprofile - ARM Cortex-A9 Woes
> CC: oprofile-list@lists.sourceforge.net
>
> Hi Will,
>
> Do you know if anyone has ever accessed the L2 performance counters on a Cortex-A9? The events that are counted by the PMU are CA9 specific and the L2 are not considered to be a part of the CA9 core. I think most CA9 vendors use ARM's "Corelink L2 Cache controller L2C-310" on the CA9 which as the following events available in an internal monitoring unit.
>
> Thanks,
>
> Jeff
>
>
> CO Eviction, CastOUT, of a line from the L2 cache.
> DRHIT Data read hit in the L2 cache.
> DRREQ Data read lookup to the L2 cache. Subsequently results in a hit or miss.
> DWHIT Data write hit in the L2 cache.
> DWREQ Data write lookup to the L2 cache. Subsequently results in a hit or miss.
> DWTREQ Data write lookup to the L2 cache with Write-Through attribute. Subsequently results in a hit or miss.
> EPFALLOC Prefetch hint allocated into the L2 cache.
> EPFHIT Prefetch hint hits in the L2 cache.
> EPFRCVDS0 Prefetch hint received by slave port S0.
> EPFRCVDS1 Prefetch hint received by slave port S1.
> IPFALLOC Allocation of a prefetch generated by L2C-310 into the L2 cache.
> IRHIT Instruction read hit in the L2 cache.
> IRREQ Instruction read lookup to the L2 cache. Subsequently results in a hit or miss.
> SPNIDEN Secure privileged non-invasive debug enable.
> SRCONFS0 Speculative read confirmed in slave port S0.
> SRCONFS1 Speculative read confirmed in slave port S1.
> SRRCVDS0 Speculative read received by slave port S0.
> SRRCVDS1 Speculative read received by slave port S1.
> WA Allocation into the L2 cache caused by a write, with Write-Allocate attribute, miss.
>
>