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[openwince-cvs-commit] include/h8/h83048 adc.h,NONE,1.1 dac.h,NONE,1.1 dmac.h,NONE,1.1 flash.h,NONE,1.1 ic.h,NONE,1.1 itu.h,NONE,1.1 other.h,NONE,1.1 ports.h,NONE,1.1 sci.h,NONE,1.1
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From: Branislav P. <bra...@us...> - 2005-06-01 14:15:52
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Update of /cvsroot/openwince/include/h8/h83048 In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv25222/h8/h83048 Added Files: adc.h dac.h dmac.h flash.h ic.h itu.h other.h ports.h sci.h Log Message: 2005-06-01 Branislav Petrovsky <bra...@sz...> * h8/h83048/adc.h: New file. * h8/h83048/dac.h: Ditto. * h8/h83048/dmac.h: Ditto. * h8/h83048/flash.h: Ditto. * h8/h83048/ic.h: Ditto. * h8/h83048/itu.h: Ditto. * h8/h83048/other.h: Ditto. * h8/h83048/ports.h: Ditto. * h8/h83048/sci.h: Ditto. * Makefile.am (nobase_openwinceinc_HEADERS): Added new files. --- NEW FILE: dac.h --- /* * $Id: dac.h,v 1.1 2005/06/01 14:15:40 brano111 Exp $ * * H8/3048 DAC Registers * Copyright (C) 2005 Elcom s.r.o. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the copyright holders nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Written by Branislav Petrovsky <bra...@sz...>, 2005. * * Documentation: * [1] Renesas Technology Corp., "Hitachi Single-Chip Microcomputer * H8/3048 Series, H8/3048F-ZTAT Hardware Manual", * Rev. 6.0, 9/3/2002, Order Number: ADE-602-073E * */ #ifndef H83048_DAC_H #define H83048_DAC_H #include <common.h> #if LANGUAGE == C #include <stdint.h> #endif /* DAC registers */ #define DAC_BASE 0xffffdc #if LANGUAGE == C typedef struct DAC_registers { uint8_t dadr0; uint8_t dadr1; uint8_t dacr; } DAC_registers_t; #define DAC_pointer ((DAC_registers_t*) DAC_BASE) #define DADR0 DAC_pointer->dadr0 #define DADR1 DAC_pointer->dadr1 #define DACR DAC_pointer->dacr #endif /* LANGUAGE == C */ #define DADR0_OFFSET 0x00 #define DADR1_OFFSET 0x01 #define DACR_OFFSET 0x02 /* DACR bits */ #define DACR_DAOE1 bit(7) #define DACR_DAOE0 bit(6) #define DACR_DAE bit(5) #endif /* H83048_DAC_H */ --- NEW FILE: flash.h --- /* * $Id: flash.h,v 1.1 2005/06/01 14:15:40 brano111 Exp $ * * H8/3048 Flash Registers * Copyright (C) 2005 Elcom s.r.o. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the copyright holders nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Written by Branislav Petrovsky <bra...@sz...>, 2005. * * Documentation: * [1] Renesas Technology Corp., "Hitachi Single-Chip Microcomputer * H8/3048 Series, H8/3048F-ZTAT Hardware Manual", * Rev. 6.0, 9/3/2002, Order Number: ADE-602-073E * */ #ifndef H83048_FLASH_H #define H83048_FLASH_H #include <common.h> #if LANGUAGE == C #include <stdint.h> #endif /* FLASH registers */ #define FLASH_BASE 0xffff40 #if LANGUAGE == C typedef struct FLASH_registers { uint8_t flmcr; uint8_t __reserved1; uint8_t ebr1; uint8_t ebr2; uint8_t __reserved2[4]; uint8_t ramcr; } FLASH_registers_t; #define FLASH_pointer ((FLASH_registers_t*) FLASH_BASE) #define FLMCR FLASH_pointer->flmcr #define EBR1 FLASH_pointer->ebr1 #define EBR2 FLASH_pointer->ebr2 #define RAMCR FLASH_pointer->ramcr #endif /* LANGUAGE == C */ #define FLMCR_OFFSET 0x00 #define EBR1_OFFSET 0x02 #define EBR2_OFFSET 0x03 #define RAMCR_OFFSET 0x08 /* FLMCR bits */ #define FLMCR_VPP bit(7) #define FLMCR_VPPE bit(6) #define FLMCR_EV bit(3) #define FLMCR_PV bit(2) #define FLMCR_E bit(1) #define FLMCR_P bit(0) /* EBR1 bits */ #define EBR1_LB7 bit(7) #define EBR1_LB6 bit(6) #define EBR1_LB5 bit(5) #define EBR1_LB4 bit(4) #define EBR1_LB3 bit(3) #define EBR1_LB2 bit(2) #define EBR1_LB1 bit(1) #define EBR1_LB0 bit(0) /* EBR2 bits */ #define EBR2_SB7 bit(7) #define EBR2_SB6 bit(6) #define EBR2_SB5 bit(5) #define EBR2_SB4 bit(4) #define EBR2_SB3 bit(3) #define EBR2_SB2 bit(2) #define EBR2_SB1 bit(1) #define EBR2_SB0 bit(0) /* RAMCR bits */ #define RAMCR_FLER bit(7) #define RAMCR_RAMS bit(3) #define RAMCR_RAM_MASK bits(2,0) #define RAMCR_RAM(x) bits_val(2,0,x) #define get_RAMCR_RAM(x) bits_get(2,0,x) #endif /* H83048_FLASH_H */ --- NEW FILE: dmac.h --- /* * $Id: dmac.h,v 1.1 2005/06/01 14:15:40 brano111 Exp $ * * H8/3048 DMAC Registers * Copyright (C) 2005 Elcom s.r.o. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the copyright holders nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Written by Branislav Petrovsky <bra...@sz...>, 2005. * * Documentation: * [1] Renesas Technology Corp., "Hitachi Single-Chip Microcomputer * H8/3048 Series, H8/3048F-ZTAT Hardware Manual", * Rev. 6.0, 9/3/2002, Order Number: ADE-602-073E * */ #ifndef H83048_DMAC_H #define H83048_DMAC_H #include <common.h> #if LANGUAGE == C #include <stdint.h> #endif /* DMAC registers */ #define DMAC_BASE 0xffff20 #if LANGUAGE == C typedef struct DMAC_registers { uint32_t mar0a; uint16_t etcr0a; uint8_t ioar0a; uint8_t dtcr0a; uint32_t mar0b; uint16_t etcr0b; uint8_t ioar0b; uint8_t dtcr0b; uint32_t mar1a; uint16_t etcr1a; uint8_t ioar1a; uint8_t dtcr1a; uint32_t mar1b; uint16_t etcr1b; uint8_t ioar1b; uint8_t dtcr1b; } DMAC_registers_t; #define DMAC_pointer ((DMAC_registers_t*) DMAC_BASE) #define MAR0A DMAC_pointer->mar0a #define ETCR0A DMAC_pointer->etcr0a #define IOAR0A DMAC_pointer->ioar0a #define DTCR0A DMAC_pointer->dtcr0a #define MAR0B DMAC_pointer->mar0b #define ETCR0B DMAC_pointer->etcr0b #define IOAR0B DMAC_pointer->ioar0b #define DTCR0B DMAC_pointer->dtcr0b #define MAR1A DMAC_pointer->mar1a #define ETCR1A DMAC_pointer->etcr1a #define IOAR1A DMAC_pointer->ioar1a #define DTCR1A DMAC_pointer->dtcr1a #define MAR1B DMAC_pointer->mar1b #define ETCR1B DMAC_pointer->etcr1b #define IOAR1B DMAC_pointer->ioar1b #define DTCR1B DMAC_pointer->dtcr1b #endif /* LANGUAGE == C */ #define MAR0A_OFFSET 0x00 #define ETCR0A_OFFSET 0x04 #define IOAR0A_OFFSET 0x06 #define DTCR0A_OFFSET 0x07 #define MAR0B_OFFSET 0x08 #define ETCR0B_OFFSET 0x0c #define IOAR0B_OFFSET 0x0e #define DTCR0B_OFFSET 0x0f #define MAR1A_OFFSET 0x10 #define ETCR1A_OFFSET 0x14 #define IOAR1A_OFFSET 0x16 #define DTCR1A_OFFSET 0x17 #define MAR1B_OFFSET 0x18 #define ETCR1B_OFFSET 0x1c #define IOAR1B_OFFSET 0x1e #define DTCR1B_OFFSET 0x1f /* DTCRA bits - short address mode */ #define DTCRA_DTE bit(7) #define DTCRA_DTSZ bit(6) #define DTCRA_DTID bit(5) #define DTCRA_RPE bit(4) #define DTCRA_DTIE bit(3) #define DTCRA_DTS_MASK bits(2,0) #define DTCRA_DTS(x) bits_val(2,0,x) #define get_DTCRA_DTS(x) bits_get(2,0,x) /* DTCRA bits - full address mode */ #define DTCRA_SAID bit(5) #define DTCRA_SAIDE bit(4) #define DTCRA_DTSA_MASK bits(2,0) #define DTCRA_DTSA(x) bits_val(2,0,x) #define get_DTCRA_DTSA(x) bits_get(2,0,x) /* DTCRB bits - short address mode */ #define DTCRB_DTE bit(7) #define DTCRB_DTSZ bit(6) #define DTCRB_DTID bit(5) #define DTCRB_RPE bit(4) #define DTCRB_DTIE bit(3) #define DTCRB_DTS_MASK bits(2,0) #define DTCRB_DTS(x) bits_val(2,0,x) #define get_DTCRB_DTS(x) bits_get(2,0,x) /* DTCRB bits - full address mode */ #define DTCRB_DAID bit(5) #define DTCRB_DAIDE bit(4) #define DTCRB_TMS bit(3) #define DTCRB_DTSB_MASK bits(2,0) #define DTCRB_DTSB(x) bits_val(2,0,x) #define get_DTCRB_DTSB(x) bits_get(2,0,x) #endif /* H83048_DMAC_H */ --- NEW FILE: adc.h --- /* * $Id: adc.h,v 1.1 2005/06/01 14:15:40 brano111 Exp $ * * H8/3048 ADC Registers * Copyright (C) 2005 Elcom s.r.o. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the copyright holders nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Written by Branislav Petrovsky <bra...@sz...>, 2005. * * Documentation: * [1] Renesas Technology Corp., "Hitachi Single-Chip Microcomputer * H8/3048 Series, H8/3048F-ZTAT Hardware Manual", * Rev. 6.0, 9/3/2002, Order Number: ADE-602-073E * */ #ifndef H83048_ADC_H #define H83048_ADC_H #include <common.h> #if LANGUAGE == C #include <stdint.h> #endif /* ADC registers */ #define ADC_BASE 0xffffe0 #if LANGUAGE == C typedef struct ADC_registers { uint8_t addrah; uint8_t addral; uint8_t addrbh; uint8_t addrbl; uint8_t addrch; uint8_t addrcl; uint8_t addrdh; uint8_t addrdl; uint8_t adcsr; uint8_t adcr; } ADC_registers_t; #define ADC_pointer ((ADC_registers_t*) ADC_BASE) #define ADDRAH ADC_pointer->addrah #define ADDRAL ADC_pointer->addral #define ADDRBH ADC_pointer->addrbh #define ADDRBL ADC_pointer->addrbl #define ADDRCH ADC_pointer->addrch #define ADDRCL ADC_pointer->addrcl #define ADDRDH ADC_pointer->addrdh #define ADDRDL ADC_pointer->addrdl #define ADCSR ADC_pointer->adcsr #define ADCR ADC_pointer->adcr #endif /* LANGUAGE == C */ #define ADDRAH_OFFSET 0x00 #define ADDRAL_OFFSET 0x01 #define ADDRBH_OFFSET 0x02 #define ADDRBL_OFFSET 0x03 #define ADDRCH_OFFSET 0x04 #define ADDRCL_OFFSET 0x05 #define ADDRDH_OFFSET 0x06 #define ADDRDL_OFFSET 0x07 #define ADCSR_OFFSET 0x08 #define ADCR_OFFSET 0x09 /* ADDR bits */ #define ADDR_AD9 bit(7) #define ADDR_AD8 bit(6) #define ADDR_AD7 bit(5) #define ADDR_AD6 bit(4) #define ADDR_AD5 bit(3) #define ADDR_AD4 bit(2) #define ADDR_AD3 bit(1) #define ADDR_AD2 bit(0) #define ADDR_AD1 bit(7) #define ADDR_AD0 bit(6) /* ADCSR bits */ #define ADCSR_ADF bit(7) #define ADCSR_ADIE bit(6) #define ADCSR_ADST bit(5) #define ADCSR_SCAN bit(4) #define ADCSR_CKS bit(3) #define ADCSR_CH_MASK bits(2,0) #define ADCSR_CH(x) bits_val(2,0,x) #define get_ADCSR_CH(x) bits_get(2,0,x) /* ADCR bits */ #define ADCR_TRGE bit(7) #endif /* H83048_ADC_H */ --- NEW FILE: other.h --- /* * $Id: other.h,v 1.1 2005/06/01 14:15:40 brano111 Exp $ * * H8/3048 Other Registers (bus, system, ...) * Copyright (C) 2005 Elcom s.r.o. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the copyright holders nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Written by Branislav Petrovsky <bra...@sz...>, 2005. * * Documentation: * [1] Renesas Technology Corp., "Hitachi Single-Chip Microcomputer * H8/3048 Series, H8/3048F-ZTAT Hardware Manual", * Rev. 6.0, 9/3/2002, Order Number: ADE-602-073E * */ #ifndef H83048_OTHER_H #define H83048_OTHER_H #include <common.h> #if LANGUAGE == C #include <stdint.h> #endif /* OTHER registers */ #define OTHER1_BASE 0xffff5c #define OTHER2_BASE 0xffffec #if LANGUAGE == C typedef struct OTHER1_registers { uint8_t dastcr; uint8_t divcr; uint8_t mstcr; uint8_t cscr; } OTHER1_registers_t; typedef struct OTHER2_registers { uint8_t abwcr; uint8_t astcr; uint8_t wcr; uint8_t wcer; uint8_t __reserved; uint8_t mdcr; uint8_t syscr; uint8_t brcr; } OTHER2_registers_t; #define OTHER1_pointer ((OTHER1_registers_t*) OTHER1_BASE) #define OTHER2_pointer ((OTHER2_registers_t*) OTHER2_BASE) #define DASTCR OTHER1_pointer->dastcr #define DIVCR OTHER1_pointer->divcr #define MSTCR OTHER1_pointer->mstcr #define CSCR OTHER1_pointer->cscr #define ABWCR OTHER2_pointer->abwcr #define ASTCR OTHER2_pointer->astcr #define WCR OTHER2_pointer->wcr #define WCER OTHER2_pointer->wcer #define MDCR OTHER2_pointer->mdcr #define SYSCR OTHER2_pointer->syscr #define BRCR OTHER2_pointer->brcr #endif /* LANGUAGE == C */ #define DASTCR_OFFSET 0x00 #define DIVCR_OFFSET 0x01 #define MSTCR_OFFSET 0x02 #define CSCR_OFFSET 0x03 #define ABWCR_OFFSET 0x00 #define ASTCR_OFFSET 0x01 #define WCR_OFFSET 0x02 #define WCER_OFFSET 0x03 #define MDCR_OFFSET 0x05 #define SYSCR_OFFSET 0x06 #define BRCR_OFFSET 0x07 /* DASTCR bits */ #define DASTCR_DASTE bit(0) /* DIVCR bits */ #define DIVCR_DIV_MASK bits(1,0) #define DIVCR_DIV(x) bits_val(1,0,x) #define get_DIVCR_DIV(x) bits_get(1,0,x) /* MSTCR bits */ #define MSTCR_PSTOP bit(7) #define MSTCR_MSTOP5 bit(5) #define MSTCR_MSTOP4 bit(4) #define MSTCR_MSTOP3 bit(3) #define MSTCR_MSTOP2 bit(2) #define MSTCR_MSTOP1 bit(1) #define MSTCR_MSTOP0 bit(0) /* CSCR bits */ #define CSCR_CS7E bit(7) #define CSCR_CS6E bit(6) #define CSCR_CS5E bit(5) #define CSCR_CS4E bit(4) /* ABWCR bits */ #define ABWCR_ABW7 bit(7) #define ABWCR_ABW6 bit(6) #define ABWCR_ABW5 bit(5) #define ABWCR_ABW4 bit(4) #define ABWCR_ABW3 bit(3) #define ABWCR_ABW2 bit(2) #define ABWCR_ABW1 bit(1) #define ABWCR_ABW0 bit(0) /* ASTCR bits */ #define ASTCR_AST7 bit(7) #define ASTCR_AST6 bit(6) #define ASTCR_AST5 bit(5) #define ASTCR_AST4 bit(4) #define ASTCR_AST3 bit(3) #define ASTCR_AST2 bit(2) #define ASTCR_AST1 bit(1) #define ASTCR_AST0 bit(0) /* WCR bits */ #define WCR_WMS_MASK bits(3,2) #define WCR_WMS(x) bits_val(3,2,x) #define get_WCR_WMS(x) bits_get(3,2,x) #define WCR_WC_MASK bits(1,0) #define WCR_WC(x) bits_val(1,0,x) #define get_WCR_WC(x) bits_get(1,0,x) /* WCER bits */ #define WCER_WCE7 bit(7) #define WCER_WCE6 bit(6) #define WCER_WCE5 bit(5) #define WCER_WCE4 bit(4) #define WCER_WCE3 bit(3) #define WCER_WCE2 bit(2) #define WCER_WCE1 bit(1) #define WCER_WCE0 bit(0) /* MDCR bits */ #define MDCR_MDS_MASK bits(2,0) #define MDCR_MDS(x) bits_val(2,0,x) #define get_MDCR_MDS(x) bits_get(2,0,x) /* SYSCR bits */ #define SYSCR_SSBY bit(7) #define SYSCR_STS_MASK bits(6,4) #define SYSCR_STS(x) bits_val(6,4,x) #define get_SYSCR_STS(x) bits_get(6,4,x) #define SYSCR_UE bit(3) #define SYSCR_NMIEG bit(2) #define SYSCR_RAME bit(0) /* BRCR bits */ #define BRCR_A23E bit(7) #define BRCR_A22E bit(6) #define BRCR_A21E bit(5) #define BRCR_BRLE bit(0) #endif /* H83048_OTHER_H */ --- NEW FILE: sci.h --- /* * $Id: sci.h,v 1.1 2005/06/01 14:15:40 brano111 Exp $ * * H8/3048 SCI Registers * Copyright (C) 2005 Elcom s.r.o. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the copyright holders nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Written by Branislav Petrovsky <bra...@sz...>, 2005. * * Documentation: * [1] Renesas Technology Corp., "Hitachi Single-Chip Microcomputer * H8/3048 Series, H8/3048F-ZTAT Hardware Manual", * Rev. 6.0, 9/3/2002, Order Number: ADE-602-073E * */ #ifndef H83048_SCI_H #define H83048_SCI_H #include <common.h> #if LANGUAGE == C #include <stdint.h> #endif /* SCI registers */ #define SCI0_BASE 0xffffb0 #define SCI1_BASE 0xffffb8 #if LANGUAGE == C typedef struct SCI_registers { uint8_t smr; uint8_t brr; uint8_t scr; uint8_t tdr; uint8_t ssr; uint8_t rdr; uint8_t scmr; } SCI_registers_t; #define SCI0_pointer ((SCI_registers_t*) SCI0_BASE) #define SCI1_pointer ((SCI_registers_t*) SCI1_BASE) #define SMR0 SCI0_pointer->smr #define BRR0 SCI0_pointer->brr #define SCR0 SCI0_pointer->scr #define TDR0 SCI0_pointer->tdr #define SSR0 SCI0_pointer->ssr #define RDR0 SCI0_pointer->rdr #define SCMR0 SCI0_pointer->scmr #define SMR1 SCI1_pointer->smr #define BRR1 SCI1_pointer->brr #define SCR1 SCI1_pointer->scr #define TDR1 SCI1_pointer->tdr #define SSR1 SCI1_pointer->ssr #define RDR1 SCI1_pointer->rdr #define SCMR1 SCI1_pointer->scmr #endif /* LANGUAGE == C */ #define SMR_OFFSET 0x00 #define BRR_OFFSET 0x01 #define SCR_OFFSET 0x02 #define TDR_OFFSET 0x03 #define SSR_OFFSET 0x04 #define RDR_OFFSET 0x05 #define SCMR_OFFSET 0x06 /* SMR bits */ #define SMR_CA bit(7) #define SMR_GM bit(7) #define SMR_CHR bit(6) #define SMR_PE bit(5) #define SMR_OE bit(4) #define SMR_STOP bit(3) #define SMR_MP bit(2) #define SMR_CKS_MASK bits(1,0) #define SMR_CKS(x) bits_val(1,0,x) #define get_SMR_CKS(x) bits_get(1,0,x) /* SCR bits */ #define SCR_TIE bit(7) #define SCR_RIE bit(6) #define SCR_TE bit(5) #define SCR_RE bit(4) #define SCR_MPIE bit(3) #define SCR_TEIE bit(2) #define SCR_CKE_MASK bits(1,0) #define SCR_CKE(x) bits_val(1,0,x) #define get_SCR_CKE(x) bits_get(1,0,x) /* SSR bits */ #define SSR_TDRE bit(7) #define SSR_RDFR bit(6) #define SSR_ORER bit(5) #define SSR_FER bit(4) #define SSR_ERS bit(4) #define SSR_PER bit(3) #define SSR_TEND bit(2) #define SSR_MPB bit(1) #define SSR_MPBT bit(0) /* SCMR bits */ #define SCMR_SDIR bit(3) #define SCMR_SINV bit(2) #define SCMR_SMIF bit(0) #endif /* H83048_SCI_H */ --- NEW FILE: ports.h --- /* * $Id: ports.h,v 1.1 2005/06/01 14:15:40 brano111 Exp $ * * H8/3048 PORTS Registers * Copyright (C) 2005 Elcom s.r.o. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the copyright holders nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Written by Branislav Petrovsky <bra...@sz...>, 2005. * * Documentation: * [1] Renesas Technology Corp., "Hitachi Single-Chip Microcomputer * H8/3048 Series, H8/3048F-ZTAT Hardware Manual", * Rev. 6.0, 9/3/2002, Order Number: ADE-602-073E * */ #ifndef H83048_PORTS_H #define H83048_PORTS_H #include <common.h> #if LANGUAGE == C #include <stdint.h> #endif /* PORTS registers */ #define PORT_BASE 0xffffc0 #if LANGUAGE == C typedef struct PORT_registers { uint8_t p1ddr; uint8_t p2ddr; uint8_t p1dr; uint8_t p2dr; uint8_t p3ddr; uint8_t p4ddr; uint8_t p3dr; uint8_t p4dr; uint8_t p5ddr; uint8_t p6ddr; uint8_t p5dr; uint8_t p6dr; uint8_t __reserved1; uint8_t p8ddr; uint8_t p7dr; uint8_t p8dr; uint8_t p9ddr; uint8_t paddr; uint8_t p9dr; uint8_t padr; uint8_t pbddr; uint8_t __reserved2; uint8_t pbdr; uint8_t __reserved3; uint8_t p2pcr; uint8_t __reserved4; uint8_t p4pcr; uint8_t p5pcr; } PORT_registers_t; #define PORT_pointer ((PORT_registers_t*) PORT_BASE) #define P1DDR PORT_pointer->p1ddr #define P2DDR PORT_pointer->p2ddr #define P1DR PORT_pointer->p1dr #define P2DR PORT_pointer->p2dr #define P3DDR PORT_pointer->p3ddr #define P4DDR PORT_pointer->p4ddr #define P3DR PORT_pointer->p3dr #define P4DR PORT_pointer->p4dr #define P5DDR PORT_pointer->p5ddr #define P6DDR PORT_pointer->p6ddr #define P5DR PORT_pointer->p5dr #define P6DR PORT_pointer->p6dr #define P8DDR PORT_pointer->p8ddr #define P7DR PORT_pointer->p7dr #define P8DR PORT_pointer->p8dr #define P9DDR PORT_pointer->p9ddr #define PADDR PORT_pointer->paddr #define P9DR PORT_pointer->p9dr #define PADR PORT_pointer->padr #define PBDDR PORT_pointer->pbddr #define PBDR PORT_pointer->pbdr #define P2PCR PORT_pointer->p2pcr #define P4PCR PORT_pointer->p4pcr #define P5PCR PORT_pointer->p5pcr #endif /* LANGUAGE == C */ #define P1DDR_OFFSET 0x00 #define P2DDR_OFFSET 0x01 #define P1DR_OFFSET 0x02 #define P2DR_OFFSET 0x03 #define P3DDR_OFFSET 0x04 #define P4DDR_OFFSET 0x05 #define P3DR_OFFSET 0x06 #define P4DR_OFFSET 0x07 #define P5DDR_OFFSET 0x08 #define P6DDR_OFFSET 0x09 #define P5DR_OFFSET 0x0a #define P6DR_OFFSET 0x0b #define P8DDR_OFFSET 0x0d #define P7DR_OFFSET 0x0e #define P8DR_OFFSET 0x0f #define P9DDR_OFFSET 0x10 #define PADDR_OFFSET 0x11 #define P9DR_OFFSET 0x12 #define PADR_OFFSET 0x13 #define PBDDR_OFFSET 0x14 #define PBDR_OFFSET 0x16 #define P2PCR_OFFSET 0x18 #define P4PCR_OFFSET 0x1a #define P5PCR_OFFSET 0x1b /* P1DDR bits */ #define P1DDR_P17DDR bit(7) #define P1DDR_P16DDR bit(6) #define P1DDR_P15DDR bit(5) #define P1DDR_P14DDR bit(4) #define P1DDR_P13DDR bit(3) #define P1DDR_P12DDR bit(2) #define P1DDR_P11DDR bit(1) #define P1DDR_P10DDR bit(0) /* P1DR bits */ #define P1DR_P17 bit(7) #define P1DR_P16 bit(6) #define P1DR_P15 bit(5) #define P1DR_P14 bit(4) #define P1DR_P13 bit(3) #define P1DR_P12 bit(2) #define P1DR_P11 bit(1) #define P1DR_P10 bit(0) /* P2DDR bits */ #define P2DDR_P27DDR bit(7) #define P2DDR_P26DDR bit(6) #define P2DDR_P25DDR bit(5) #define P2DDR_P24DDR bit(4) #define P2DDR_P23DDR bit(3) #define P2DDR_P22DDR bit(2) #define P2DDR_P21DDR bit(1) #define P2DDR_P20DDR bit(0) /* P2DR bits */ #define P2DR_P27 bit(7) #define P2DR_P26 bit(6) #define P2DR_P25 bit(5) #define P2DR_P24 bit(4) #define P2DR_P23 bit(3) #define P2DR_P22 bit(2) #define P2DR_P21 bit(1) #define P2DR_P20 bit(0) /* P3DDR bits */ #define P3DDR_P37DDR bit(7) #define P3DDR_P36DDR bit(6) #define P3DDR_P35DDR bit(5) #define P3DDR_P34DDR bit(4) #define P3DDR_P33DDR bit(3) #define P3DDR_P32DDR bit(2) #define P3DDR_P31DDR bit(1) #define P3DDR_P30DDR bit(0) /* P3DR bits */ #define P3DR_P37 bit(7) #define P3DR_P36 bit(6) #define P3DR_P35 bit(5) #define P3DR_P34 bit(4) #define P3DR_P33 bit(3) #define P3DR_P32 bit(2) #define P3DR_P31 bit(1) #define P3DR_P30 bit(0) /* P4DDR bits */ #define P4DDR_P47DDR bit(7) #define P4DDR_P46DDR bit(6) #define P4DDR_P45DDR bit(5) #define P4DDR_P44DDR bit(4) #define P4DDR_P43DDR bit(3) #define P4DDR_P42DDR bit(2) #define P4DDR_P41DDR bit(1) #define P4DDR_P40DDR bit(0) /* P4DR bits */ #define P4DR_P47 bit(7) #define P4DR_P46 bit(6) #define P4DR_P45 bit(5) #define P4DR_P44 bit(4) #define P4DR_P43 bit(3) #define P4DR_P42 bit(2) #define P4DR_P41 bit(1) #define P4DR_P40 bit(0) /* P5DDR bits */ #define P5DDR_P53DDR bit(3) #define P5DDR_P52DDR bit(2) #define P5DDR_P51DDR bit(1) #define P5DDR_P50DDR bit(0) /* P5DR bits */ #define P5DR_P53 bit(3) #define P5DR_P52 bit(2) #define P5DR_P51 bit(1) #define P5DR_P50 bit(0) /* P6DDR bits */ #define P6DDR_P66DDR bit(6) #define P6DDR_P65DDR bit(5) #define P6DDR_P64DDR bit(4) #define P6DDR_P63DDR bit(3) #define P6DDR_P62DDR bit(2) #define P6DDR_P61DDR bit(1) #define P6DDR_P60DDR bit(0) /* P6DR bits */ #define P6DR_P66 bit(6) #define P6DR_P65 bit(5) #define P6DR_P64 bit(4) #define P6DR_P63 bit(3) #define P6DR_P62 bit(2) #define P6DR_P61 bit(1) #define P6DR_P60 bit(0) /* P7DR bits */ #define P7DR_P77 bit(7) #define P7DR_P76 bit(6) #define P7DR_P75 bit(5) #define P7DR_P74 bit(4) #define P7DR_P73 bit(3) #define P7DR_P72 bit(2) #define P7DR_P71 bit(1) #define P7DR_P70 bit(0) /* P8DDR bits */ #define P8DDR_P84DDR bit(4) #define P8DDR_P83DDR bit(3) #define P8DDR_P82DDR bit(2) #define P8DDR_P81DDR bit(1) #define P8DDR_P80DDR bit(0) /* P8DR bits */ #define P8DR_P84 bit(4) #define P8DR_P83 bit(3) #define P8DR_P82 bit(2) #define P8DR_P81 bit(1) #define P8DR_P80 bit(0) /* P9DDR bits */ #define P9DDR_P95DDR bit(5) #define P9DDR_P94DDR bit(4) #define P9DDR_P93DDR bit(3) #define P9DDR_P92DDR bit(2) #define P9DDR_P91DDR bit(1) #define P9DDR_P90DDR bit(0) /* P9DR bits */ #define P9DR_P95 bit(5) #define P9DR_P94 bit(4) #define P9DR_P93 bit(3) #define P9DR_P92 bit(2) #define P9DR_P91 bit(1) #define P9DR_P90 bit(0) /* PADDR bits */ #define PADDR_PA7DDR bit(7) #define PADDR_PA6DDR bit(6) #define PADDR_PA5DDR bit(5) #define PADDR_PA4DDR bit(4) #define PADDR_PA3DDR bit(3) #define PADDR_PA2DDR bit(2) #define PADDR_PA1DDR bit(1) #define PADDR_PA0DDR bit(0) /* PADR bits */ #define PADR_PA7 bit(7) #define PADR_PA6 bit(6) #define PADR_PA5 bit(5) #define PADR_PA4 bit(4) #define PADR_PA3 bit(3) #define PADR_PA2 bit(2) #define PADR_PA1 bit(1) #define PADR_PA0 bit(0) /* PBDDR bits */ #define PBDDR_PB7DDR bit(7) #define PBDDR_PB6DDR bit(6) #define PBDDR_PB5DDR bit(5) #define PBDDR_PB4DDR bit(4) #define PBDDR_PB3DDR bit(3) #define PBDDR_PB2DDR bit(2) #define PBDDR_PB1DDR bit(1) #define PBDDR_PB0DDR bit(0) /* PBDR bits */ #define PBDR_PB7 bit(7) #define PBDR_PB6 bit(6) #define PBDR_PB5 bit(5) #define PBDR_PB4 bit(4) #define PBDR_PB3 bit(3) #define PBDR_PB2 bit(2) #define PBDR_PB1 bit(1) #define PBDR_PB0 bit(0) /* P2PCR bits */ #define P2PCR_P27PCR bit(7) #define P2PCR_P26PCR bit(6) #define P2PCR_P25PCR bit(5) #define P2PCR_P24PCR bit(4) #define P2PCR_P23PCR bit(3) #define P2PCR_P22PCR bit(2) #define P2PCR_P21PCR bit(1) #define P2PCR_P20PCR bit(0) /* P4PCR bits */ #define P4PCR_P47PCR bit(7) #define P4PCR_P46PCR bit(6) #define P4PCR_P45PCR bit(5) #define P4PCR_P44PCR bit(4) #define P4PCR_P43PCR bit(3) #define P4PCR_P42PCR bit(2) #define P4PCR_P41PCR bit(1) #define P4PCR_P40PCR bit(0) /* P5PCR bits */ #define P5PCR_P53PCR bit(3) #define P5PCR_P52PCR bit(2) #define P5PCR_P51PCR bit(1) #define P5PCR_P50PCR bit(0) #endif /* H83048_PORTS_H */ --- NEW FILE: ic.h --- /* * $Id: ic.h,v 1.1 2005/06/01 14:15:40 brano111 Exp $ * * H8/3048 Interrupt Controller (IC) Registers * Copyright (C) 2005 Elcom s.r.o. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the copyright holders nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Written by Branislav Petrovsky <bra...@sz...>, 2005. * * Documentation: * [1] Renesas Technology Corp., "Hitachi Single-Chip Microcomputer * H8/3048 Series, H8/3048F-ZTAT Hardware Manual", * Rev. 6.0, 9/3/2002, Order Number: ADE-602-073E * */ #ifndef H83048_IC_H #define H83048_IC_H #include <common.h> #if LANGUAGE == C #include <stdint.h> #endif /* IC registers */ #define IC_BASE 0xfffff4 #if LANGUAGE == C typedef struct IC_registers { uint8_t iscr; uint8_t ier; uint8_t isr; uint8_t __reserved; uint8_t ipra; uint8_t iprb; } IC_registers_t; #define IC_pointer ((IC_registers_t*) IC_BASE) #define ISCR IC_pointer->iscr #define IER IC_pointer->ier #define ISR IC_pointer->isr #define IPRA IC_pointer->ipra #define IPRB IC_pointer->iprb #endif /* LANGUAGE == C */ #define ISCR_OFFSET 0x00 #define IER_OFFSET 0x01 #define ISR_OFFSET 0x02 #define IPRA_OFFSET 0x04 #define IPRB_OFFSET 0x05 /* ISCR bits */ #define ISCR_IRQ5SC bit(5) #define ISCR_IRQ4SC bit(4) #define ISCR_IRQ3SC bit(3) #define ISCR_IRQ2SC bit(2) #define ISCR_IRQ1SC bit(1) #define ISCR_IRQ0SC bit(0) /* IER bits */ #define IER_IRQ5E bit(5) #define IER_IRQ4E bit(4) #define IER_IRQ3E bit(3) #define IER_IRQ2E bit(2) #define IER_IRQ1E bit(1) #define IER_IRQ0E bit(0) /* ISR bits */ #define ISR_IRQ5F bit(5) #define ISR_IRQ4F bit(4) #define ISR_IRQ3F bit(3) #define ISR_IRQ2F bit(2) #define ISR_IRQ1F bit(1) #define ISR_IRQ0F bit(0) /* IPRA bits */ #define IPRA_IPRA7 bit(7) #define IPRA_IPRA6 bit(6) #define IPRA_IPRA5 bit(5) #define IPRA_IPRA4 bit(4) #define IPRA_IPRA3 bit(3) #define IPRA_IPRA2 bit(2) #define IPRA_IPRA1 bit(1) #define IPRA_IPRA0 bit(0) /* IPRB bits */ #define IPRB_IPRB7 bit(7) #define IPRB_IPRB6 bit(6) #define IPRB_IPRB5 bit(5) #define IPRB_IPRB3 bit(3) #define IPRB_IPRB2 bit(2) #define IPRB_IPRB1 bit(1) #endif /* H83048_IC_H */ --- NEW FILE: itu.h --- /* * $Id: itu.h,v 1.1 2005/06/01 14:15:40 brano111 Exp $ * * H8/3048 ITU Registers * Copyright (C) 2005 Elcom s.r.o. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the copyright holders nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Written by Branislav Petrovsky <bra...@sz...>, 2005. * * Documentation: * [1] Renesas Technology Corp., "Hitachi Single-Chip Microcomputer * H8/3048 Series, H8/3048F-ZTAT Hardware Manual", * Rev. 6.0, 9/3/2002, Order Number: ADE-602-073E * */ #ifndef H83048_ITU_H #define H83048_ITU_H #include <common.h> #if LANGUAGE == C #include <stdint.h> #endif /* ITU registers */ #define ITU_COMMON1_BASE 0xffff60 #define ITU_COMMON2_BASE 0xffff90 #define ITU0_BASE 0xffff64 #define ITU1_BASE 0xffff6e #define ITU2_BASE 0xffff78 #define ITU3_BASE 0xffff82 #define ITU4_BASE 0xffff92 #if LANGUAGE == C typedef struct ITU_registers { uint8_t tcr; uint8_t tior; uint8_t tier; uint8_t tsr; uint8_t tcnth; uint8_t tcntl; uint8_t grah; uint8_t gral; uint8_t grbh; uint8_t grbl; uint8_t brah; /* only ITU channel 3 and 4 */ uint8_t bral; /* only ITU channel 3 and 4 */ uint8_t brbh; /* only ITU channel 3 and 4 */ uint8_t brbl; /* only ITU channel 3 and 4 */ } ITU_registers_t; typedef struct ITU_common1_registers { uint8_t tstr; uint8_t tsnc; uint8_t tmdr; uint8_t tfcr; } ITU_common1_registers_t; typedef struct ITU_common2_registers { uint8_t toer; uint8_t tocr; } ITU_common2_registers_t; #define ITU_COMMON1_pointer ((ITU_common1_registers_t*) ITU_COMMON1_BASE) #define ITU_COMMON2_pointer ((ITU_common2_registers_t*) ITU_COMMON2_BASE) #define ITU0_pointer ((ITU_registers_t*) ITU0_BASE) #define ITU1_pointer ((ITU_registers_t*) ITU1_BASE) #define ITU2_pointer ((ITU_registers_t*) ITU2_BASE) #define ITU3_pointer ((ITU_registers_t*) ITU3_BASE) #define ITU4_pointer ((ITU_registers_t*) ITU4_BASE) #define TCR0 ITU0_pointer->tcr #define TIOR0 ITU0_pointer->tior #define TIER0 ITU0_pointer->tier #define TSR0 ITU0_pointer->tsr #define TCNT0H ITU0_pointer->tcnth #define TCNT0L ITU0_pointer->tcntl #define GRA0H ITU0_pointer->grah #define GRA0L ITU0_pointer->gral #define GRB0H ITU0_pointer->grbh #define GRB0L ITU0_pointer->grbl #define TCR1 ITU1_pointer->tcr #define TIOR1 ITU1_pointer->tior #define TIER1 ITU1_pointer->tier #define TSR1 ITU1_pointer->tsr #define TCNT1H ITU1_pointer->tcnth #define TCNT1L ITU1_pointer->tcntl #define GRA1H ITU1_pointer->grah #define GRA1L ITU1_pointer->gral #define GRB1H ITU1_pointer->grbh #define GRB1L ITU1_pointer->grbl #define TCR2 ITU2_pointer->tcr #define TIOR2 ITU2_pointer->tior #define TIER2 ITU2_pointer->tier #define TSR2 ITU2_pointer->tsr #define TCNT2H ITU2_pointer->tcnth #define TCNT2L ITU2_pointer->tcntl #define GRA2H ITU2_pointer->grah #define GRA2L ITU2_pointer->gral #define GRB2H ITU2_pointer->grbh #define GRB2L ITU2_pointer->grbl #define TCR3 ITU3_pointer->tcr #define TIOR3 ITU3_pointer->tior #define TIER3 ITU3_pointer->tier #define TSR3 ITU3_pointer->tsr #define TCNT3H ITU3_pointer->tcnth #define TCNT3L ITU3_pointer->tcntl #define GRA3H ITU3_pointer->grah #define GRA3L ITU3_pointer->gral #define GRB3H ITU3_pointer->grbh #define GRB3L ITU3_pointer->grbl #define BRA3H ITU3_pointer->brah #define BRA3L ITU3_pointer->bral #define BRB3H ITU3_pointer->brbh #define BRB3L ITU3_pointer->brbl #define TCR4 ITU4_pointer->tcr #define TIOR4 ITU4_pointer->tior #define TIER4 ITU4_pointer->tier #define TSR4 ITU4_pointer->tsr #define TCNT4H ITU4_pointer->tcnth #define TCNT4L ITU4_pointer->tcntl #define GRA4H ITU4_pointer->grah #define GRA4L ITU4_pointer->gral #define GRB4H ITU4_pointer->grbh #define GRB4L ITU4_pointer->grbl #define BRA4H ITU4_pointer->brah #define BRA4L ITU4_pointer->bral #define BRB4H ITU4_pointer->brbh #define BRB4L ITU4_pointer->brbl #define TSTR ITU_COMMON1_pointer->tstr #define TSNC ITU_COMMON1_pointer->tsnc #define TMDR ITU_COMMON1_pointer->tmdr #define TFCR ITU_COMMON1_pointer->tfcr #define TOER ITU_COMMON2_pointer->toer #define TOCR ITU_COMMON2_pointer->tocr #endif /* LANGUAGE == C */ #define TCR_OFFSET 0x00 #define TIOR_OFFSET 0x01 #define TIER_OFFSET 0x02 #define TSR_OFFSET 0x03 #define TCNTH_OFFSET 0x04 #define TCNTL_OFFSET 0x05 #define GRAH_OFFSET 0x06 #define GRAL_OFFSET 0x07 #define GRBH_OFFSET 0x08 #define GRBL_OFFSET 0x09 #define BRAH_OFFSET 0x0a #define BRAL_OFFSET 0x0b #define BRBH_OFFSET 0x0c #define BRBL_OFFSET 0x0d #define TSTR_OFFSET 0x00 #define TSNC_OFFSET 0x01 #define TMDR_OFFSET 0x02 #define TFCR_OFFSET 0x03 #define TOER_OFFSET 0x00 #define TOCR_OFFSET 0x01 #endif /* H83048_ITU_H */ |
