Status

Development Status

The OpenSOC86 project is still in development. The current version can boot an IBM PCXT compatible bios and boot DOS from a floppy disk image in simulation.

This version only runs in simulation and is not yet hardware proven. However the complete SOC is written in 100% synthesizable Verilog code. In order to load the SOC into a FPGA, a SDRAM, SRAM, SD-Card and Cache controller need to be added. Also there is an incompatibility issue with the instruction buffer and SDRAM behavior. The instruction buffer assumes that 8 word bursts from SDRAM can start at any memory location without addresses wrapping around. These features are currently in development.

There are several known bugs in the cpu core. These are reported by the test code. Even with these bugs the system is able to boot the PCXT bios and MSDOS.

Most peripherals are implemented minimally. These should be extended in the future. Peripherals like keyboard and mouse controllers are not yet developed.

The CPU is meant to be fully pipelined. Currently all register-to-register instructions execute in a pipelined matter. Data hazards are resolved by inserting a two clock bubble in all cases where a hazard occurs. Hazards due to simultaneous reads and writes to the register file are resolved with bypassing. Due to the pipeline length, the two-clock bubble will either result in resolving the hazard or a new read/write hazard will occur which is again resolved with bypassing.

Instructions that access memory are executed in a none-pipelined manner. In order to pipeline these, hazard detection needs to be added for segment registers.

All call, jump, push, pop and control instructions are not pipelined. These will be pipelined by first resolving the segment hazards and then changing the microcode issuing.