Description

Description

The complete design is split up in three projects: The cpu project for designing and testing the processor only. The soc project is used for simulating the cpu together with several peripherals like the timers, DMA controller and others. This is enough to boot the Bios and MSDOS in simulations. All the memory controllers (and cache) are not included in this project. The test bench loads all ROMS and provides a memory interface to the cores. The socmem project contains the complete system, including the memory controllers. This project is still in development and thus not yet included in this version. This project will result in the actual synthesized design which can be loaded into a FPGA. All the Quartus project files are located in the project directory.

All Verilog hardware description files are stored in the rtl directory. Each project will use these source files when needed. The cpu subdirectory contains the complete source code for the processor. All peripheral source code is stored in the peri subdirectory.

Technical Description

• Directory Structure
• Pipeline Architecture
• Hazards
• Tools

Compilation and Simulation

• Building the CPU
• Building the SOC