SYS TEC electronic (http://www.systec-electronic.com) and B&R Industrie Elektronik (http://www.br-automation.com) have released version 1.8.1 of the openPOWERLINK Protocol Stack. The release includes the new POWERLINK IP Core for Altera and Xilinx FPGAs. It comes with a ready-to-use building block for an easy integration into own designs of slave devices (e.g. digital and analog I/O's or drives). Furthermore it equips your devices with a fast POWERLINK interface. An integrated hardware accelerated MAC with auto response feature meets hard realtime requirements. Additional digital control lines in form of General Purpose Input/Output (GPIO) are available.
openPOWERLINK can also be used as a pure software solution on LINUX, Windows or VxWorks.Demoprojects for serveral evaluation boards with altera and Xilinx FPGA devices are included.
The major changes of the protocol stack are:
- New POWERLINK IP Core for Altera and Xilinx FPGAs with two attached MII/RMII PHY's
- Driver for Intel 82573 Ethernet controller supports additional devices:
82573L, 82567V, 82583V, 82567LM, 82574L
- Added driver for Intel 8255x Ethernet controller
- Added demo for TERASIC Industrial Networking Kit with Altera Cyclone IV FPGA
- Serveral bugs fixed
Please see the included revision history and update guide for further information.
The source code can be downloaded from here