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#242 STM32L0x too high SWD clock
Hi,
when calling reset init on STM32L0x target, function stm32l0_enable_HSI16 is called which bumps SWD frequency to 2500kHz. My adapter (STlink-V2) rounds it to 1800MHz, but it is still too high. Communication breaks and reset is needed. Wiring might be problem, I am not sure. (F7 worked on 1800kHz flawlessly with significantly longer wires)
My point is, that 2.5MHz is pretty high clock frequency to set it so blindly.
Exact target is STM32L011. I was able to reach 480kHz, 950kHz and higher does not work.
On Nucleo-L053RZ no problem even with 4 MHz SWD clock via integrated ST-Link. Although the L053 differs substantially from L011, the CPU core and debug logic are certainly quite similar.
Custom board, original ST-Link? Stable power-supply, suitable bypass, no glitches? SWD connection via jumper wires or short PCB traces or soldered wires?
Loss of connection right after reset init or during debug session?
Custom board (<60mVpp ripple), jumper wires, chinese clone of stlink. But wait!
When I let my code to configure clocks (using PLL to run on 24MHz) I can crank up SWD frequency to 4MHz without problem.
I did a little testing and swd itself seems to run fine at 1800 kHz after
reset init.Whenever I try to load hex file to flash, no matter what clk source and frequency MCU uses, it fails on 950kHz and higher. (no more steps between 450 and 950 kHz avilable)
Power path layout is in attachment. I don't think its that bad. Lowest runtime voltage (biggest spike drop) is to 3.15V. MCU is STM32L011 in TSSOP14 package.
I believe the issue might be similar to
https://sourceforge.net/p/openocd/tickets/231/
Please see -d3 log if the adapter exceeds MAX_WAIT_RETRIES (8).
Please test
http://openocd.zylin.com/5270