This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via a482b789410d1cae87961fd31af34214bfec19ed (commit)
from c168761983c50a28d2c8439fdded31dd7ec09300 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit a482b789410d1cae87961fd31af34214bfec19ed
Author: Tomas Vanek <va...@fb...>
Date: Sun Sep 14 22:40:28 2025 +0200
tcl/target: drop more useless reset-start events
These target configs implement neither device clock setting
nor boost of adapter speed in reset-init event.
Therefore it's not necessary to set back the safe speed in reset-start
Change-Id: I7dcd6f6d1a977388c7a0bc45fe46ede955bd45cb
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9129
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/altera_fpgasoc.cfg b/tcl/target/altera_fpgasoc.cfg
index a98b346c6..00ebb3726 100644
--- a/tcl/target/altera_fpgasoc.cfg
+++ b/tcl/target/altera_fpgasoc.cfg
@@ -48,7 +48,6 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x80110000
-$_TARGETNAME1 configure -event reset-start { adapter speed 1000 }
$_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
@@ -56,7 +55,6 @@ $_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
#target create $_TARGETNAME2 cortex_a -dap $_CHIPNAME.dap \
# -coreid 1 -dbgbase 0x80112000
-#$_TARGETNAME2 configure -event reset-start { adapter speed 1000 }
#$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
proc cycv_dbginit {target} {
diff --git a/tcl/target/imx6.cfg b/tcl/target/imx6.cfg
index c9b6acf79..ed83d65fc 100644
--- a/tcl/target/imx6.cfg
+++ b/tcl/target/imx6.cfg
@@ -78,6 +78,5 @@ proc imx6_dbginit {target} {
# Slow speed to be sure it will work
adapter speed 1000
-$_TARGETNAME configure -event reset-start { adapter speed 1000 }
$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"
diff --git a/tcl/target/npcx.cfg b/tcl/target/npcx.cfg
index 84bb0b7a5..8ca9f1498 100644
--- a/tcl/target/npcx.cfg
+++ b/tcl/target/npcx.cfg
@@ -46,9 +46,6 @@ $_TARGETNAME configure -work-area-phys 0x200c0000 -work-area-size $_WORKAREASIZE
# 4MHz / 6 = 666KHz, so use 600KHz for it
adapter speed 600
-# For safety purposes, set for the lowest cpu clock configuration
-$_TARGETNAME configure -event reset-start {adapter speed 600}
-
# use sysresetreq to perform a system reset
cortex_m reset_config sysresetreq
diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index bd8b111a0..c1921b437 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -66,7 +66,6 @@ proc omap3_dbginit {target} {
# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
# OK to speed up *after* PLL and clock tree setup.
adapter speed 1000
-$_TARGETNAME configure -event "reset-start" { adapter speed 1000 }
# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick
diff --git a/tcl/target/omapl138.cfg b/tcl/target/omapl138.cfg
index 78c456d5c..9d89429a8 100644
--- a/tcl/target/omapl138.cfg
+++ b/tcl/target/omapl138.cfg
@@ -55,7 +55,6 @@ $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000
# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
adapter speed 1500
-$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg
index 14ee13c37..a9cfc63d5 100644
--- a/tcl/target/pxa255.cfg
+++ b/tcl/target/pxa255.cfg
@@ -31,7 +31,6 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \
# Until the PLL kicks in, keep the JTAG clock slow enough
# that we get no errors.
adapter speed 300
-$_TARGETNAME configure -event "reset-start" { adapter speed 300 }
# both TRST and SRST are *required* for debug
# DCSR is often accessed with SRST active
-----------------------------------------------------------------------
Summary of changes:
tcl/target/altera_fpgasoc.cfg | 2 --
tcl/target/imx6.cfg | 1 -
tcl/target/npcx.cfg | 3 ---
tcl/target/omap3530.cfg | 1 -
tcl/target/omapl138.cfg | 1 -
tcl/target/pxa255.cfg | 1 -
6 files changed, 9 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
