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- Log -----------------------------------------------------------------
commit 78daf24a5c29664669bb1d9d7851cbbb90dbc444
Author: Erhan Kurubas <erh...@es...>
Date: Sun Jun 18 11:00:22 2023 +0200
tcl/target: update esp32s3.cfg to reference shared functions in the esp_common.cfg
This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.
Signed-off-by: Erhan Kurubas <erh...@es...>
Change-Id: Ifb0122f3b98a767f27746409499733b70fb7d0e8
Reviewed-on: https://review.openocd.org/c/openocd/+/7747
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/esp32s3.cfg b/tcl/target/esp32s3.cfg
index 42b219963..12c166c46 100644
--- a/tcl/target/esp32s3.cfg
+++ b/tcl/target/esp32s3.cfg
@@ -1,44 +1,20 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
-# The ESP32-S3 only supports JTAG.
-transport select jtag
-set CPU_MAX_ADDRESS 0xFFFFFFFF
-source [find bitsbytes.tcl]
-source [find memory.tcl]
-source [find mmr_helpers.tcl]
-# Source the ESP common configuration file
+# Source the ESP common configuration file.
source [find target/esp_common.cfg]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME esp32s3
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x120034e5
-}
+# Target specific global variables
+set _CHIPNAME "esp32s3"
+set _CPUTAPID 0x120034e5
+set _ESP_ARCH "xtensa"
+set _ONLYCPU 3
+set _ESP_SMP_TARGET 1
+set _ESP_SMP_BREAK 1
+set _ESP_EFUSE_MAC_ADDR_REG 0x60007044
if { [info exists ESP32_S3_ONLYCPU] } {
set _ONLYCPU $ESP32_S3_ONLYCPU
-} else {
- set _ONLYCPU 2
-}
-
-set _CPU0NAME cpu0
-set _CPU1NAME cpu1
-set _TARGETNAME_0 $_CHIPNAME.$_CPU0NAME
-set _TARGETNAME_1 $_CHIPNAME.$_CPU1NAME
-
-jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 -expected-id $_CPUTAPID
-if { $_ONLYCPU != 1 } {
- jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -expected-id $_CPUTAPID
-} else {
- jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -disable -expected-id $_CPUTAPID
}
proc esp32s3_memprot_is_enabled { } {
@@ -89,66 +65,10 @@ proc esp32s3_memprot_is_enabled { } {
return 0
}
-# PRO-CPU
-target create $_TARGETNAME_0 $_CHIPNAME -endian little -chain-position $_TARGETNAME_0 -coreid 0
-# APP-CPU
-if { $_ONLYCPU != 1 } {
- target create $_TARGETNAME_1 $_CHIPNAME -endian little -chain-position $_TARGETNAME_1 -coreid 1
- target smp $_TARGETNAME_0 $_TARGETNAME_1
-}
-
-$_TARGETNAME_0 xtensa maskisr on
-$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
-$_TARGETNAME_0 configure -event examine-end {
- # Need to enable to set 'semihosting_basedir'
- arm semihosting enable
- arm semihosting_resexit enable
- if { [info exists _SEMIHOST_BASEDIR] } {
- if { $_SEMIHOST_BASEDIR != "" } {
- arm semihosting_basedir $_SEMIHOST_BASEDIR
- }
- }
-}
-
-if { $_ONLYCPU != 1 } {
- $_TARGETNAME_1 configure -event examine-end {
- # Need to enable to set 'semihosting_basedir'
- arm semihosting enable
- arm semihosting_resexit enable
- if { [info exists _SEMIHOST_BASEDIR] } {
- if { $_SEMIHOST_BASEDIR != "" } {
- arm semihosting_basedir $_SEMIHOST_BASEDIR
- }
- }
- }
-}
-
-$_TARGETNAME_0 configure -event gdb-attach {
- $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
- # necessary to auto-probe flash bank when GDB is connected and generate proper memory map
- halt 1000
- if { [esp32s3_memprot_is_enabled] } {
- # 'reset halt' to disable memory protection and allow flasher to work correctly
- echo "Memory protection is enabled. Reset target to disable it..."
- reset halt
- }
-}
-$_TARGETNAME_0 configure -event reset-assert-post { soft_reset_halt }
-
-if { $_ONLYCPU != 1 } {
- $_TARGETNAME_1 configure -event gdb-attach {
- $_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut
- # necessary to auto-probe flash bank when GDB is connected
- halt 1000
- if { [esp32s3_memprot_is_enabled] } {
- # 'reset halt' to disable memory protection and allow flasher to work correctly
- echo "Memory protection is enabled. Reset target to disable it..."
- reset halt
- }
- }
- $_TARGETNAME_1 configure -event reset-assert-post { soft_reset_halt }
+proc esp32s3_soc_reset { } {
+ soft_reset_halt
}
-gdb_breakpoint_override hard
+create_esp_target $_ESP_ARCH
source [find target/xtensa-core-esp32s3.cfg]
-----------------------------------------------------------------------
Summary of changes:
tcl/target/esp32s3.cfg | 104 ++++++-------------------------------------------
1 file changed, 12 insertions(+), 92 deletions(-)
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