[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-231-g72131e05e

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- Log -----------------------------------------------------------------
commit 72131e05e9337f1f950f604f5e07683e887ce3ab
Author: Bohdan Tymkiv <boh...@gm...>
Date:   Tue May 23 14:40:11 2023 +0300

    cortex_m: fix reading of DCB_DSCSR register
    
    Value in the 'dscsr' variable is garbage until the DAP queue is run.
    Postpone evaluation of the 'secure_state' variable. Reading the
    core registers in between will execute the DAP queue.
    
    Change-Id: I44959e882dbafb1b9779e813c3d13f3b3dbcd47f
    Signed-off-by: Bohdan Tymkiv <boh...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7693
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 8e55014f9..ebc3bac99 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -801,15 +801,11 @@ static int cortex_m_debug_entry(struct target *target)
 		return retval;
 
 	/* examine PE security state */
-	bool secure_state = false;
+	uint32_t dscsr = 0;
 	if (armv7m->arm.arch == ARM_ARCH_V8M) {
-		uint32_t dscsr;
-
 		retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr);
 		if (retval != ERROR_OK)
 			return retval;
-
-		secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS;
 	}
 
 	/* Load all registers to arm.core_cache */
@@ -857,6 +853,7 @@ static int cortex_m_debug_entry(struct target *target)
 	if (armv7m->exception_number)
 		cortex_m_examine_exception_reason(target);
 
+	bool secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS;
 	LOG_TARGET_DEBUG(target, "entered debug state in core mode: %s at PC 0x%" PRIx32
 			", cpu in %s state, target->state: %s",
 		arm_mode_name(arm->core_mode),

-----------------------------------------------------------------------

Summary of changes:
 src/target/cortex_m.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)


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