[OpenOCD-devel] [PATCH]: e34b9f3 tcl: add support for UWP5661

[<ge...@op...>]

This is an automated email from Gerrit.

Kelvin Cheung (keg...@gm...) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/4942

-- gerrit

commit e34b9f3a974e8890df2152bae938a58786a0e607
Author: Kelvin Cheung <keg...@gm...>
Date:   Mon Feb 25 16:51:15 2019 +0800

    tcl: add support for UWP5661
    
    Initial support for UNISOC UWP5661 and for the development
    board IVY5661.
    
    Change-Id: Ie75b14456fbab0af34675ec2873ecd3cad5ccd9b
    Signed-off-by: Keguang Zhang <keg...@gm...>

diff --git a/tcl/board/ivy5661.cfg b/tcl/board/ivy5661.cfg
new file mode 100644
index 0000000..b913d41
--- /dev/null
+++ b/tcl/board/ivy5661.cfg
@@ -0,0 +1,11 @@
+# IVY5661 (UWP 5661 development board)
+# https://www.96boards.org/product/ivy5661/
+#
+
+source [find interface/jlink.cfg]
+
+transport select swd
+
+source [find target/uwp5661.cfg]
+
+reset_config none separate
diff --git a/tcl/target/uwp5661.cfg b/tcl/target/uwp5661.cfg
new file mode 100644
index 0000000..a9799e5
--- /dev/null
+++ b/tcl/target/uwp5661.cfg
@@ -0,0 +1,74 @@
+# script for UWP5661
+#
+# The Unisoc UWP5661 is a highly integrated 2-in-1 connectivity
+# single chip which offers the lowest RBOM in the industry for
+# smart home, IoT, industrial control and automotive applications.
+#
+# This chip includes 2.4GHz and 5GHz WLAN IEEE802.11 a/b/g/n/ac
+# 2x2 MU-MIMO 20/40/80 MHz VHT R2 MAC/PHY/Radio, Bluetooth 5 with
+# supporting high power mode, mesh, direction finding and long range.
+# Additionally, this radio-on-chip integrates power amplifiers,
+# receive low noise amplifiers and RF TR switch.
+#
+# This chip includes two ARM Cortex-M4 processors.
+# One is used for application processor, while the other
+# is used for offloaded Wi-Fi software and Bluetooth controller.
+#
+# Notes:
+# - Cortex-M4 for user application, operating at up to 416 MHz
+# - Cortex-M4 for Wi-Fi and Bluetooth, operating at up to 256 MHz
+# - 32KB I-Cache and 32KB D-Cache
+# - 963KB internal SRAM in application processor, operating at up 208 MHz
+# - Supports to up to 32MB external Serial NOR flash, operating at up 104 MHz
+# - SWD
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME uwp5661
+}
+
+if { [info exists CPU_JTAG_TAPID] } {
+	set _CPU_JTAG_TAPID $CPU_JTAG_TAPID
+} else {
+	set _CPU_JTAG_TAPID 0x5ba00477
+}
+
+if { [info exists CPU_SWD_TAPID] } {
+	set _CPU_SWD_TAPID $CPU_SWD_TAPID
+} else {
+	set _CPU_SWD_TAPID 0x5ba02477
+}
+
+source [find target/swj-dp.tcl]
+
+if { [using_jtag] } {
+	set _CPU_TAPID $_CPU_JTAG_TAPID
+} else {
+	set _CPU_TAPID $_CPU_SWD_TAPID
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap -ap-num 3
+
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	# 640 KB On-Chip SRAM
+	set _WORKAREASIZE 0xa0000
+}
+
+$_TARGETNAME configure -work-area-phys 0x1a0000 \
+                       -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+if { ![using_hla] } {
+	cortex_m reset_config sysresetreq
+}
+
+reset_config none separate
+
+adapter_khz 4000

--