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[Openocd-svn] r2278 - trunk/src/target
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From: <zw...@ma...> - 2009-06-18 09:09:30
|
Author: zwelch
Date: 2009-06-18 09:08:52 +0200 (Thu, 18 Jun 2009)
New Revision: 2278
Modified:
trunk/src/target/arm11.c
trunk/src/target/arm11.h
trunk/src/target/arm11_dbgtap.c
trunk/src/target/arm720t.c
trunk/src/target/arm720t.h
trunk/src/target/arm7_9_common.c
trunk/src/target/arm7_9_common.h
trunk/src/target/arm7tdmi.c
trunk/src/target/arm920t.c
trunk/src/target/arm920t.h
trunk/src/target/arm926ejs.c
trunk/src/target/arm926ejs.h
trunk/src/target/arm966e.c
trunk/src/target/arm966e.h
trunk/src/target/arm9tdmi.c
trunk/src/target/arm9tdmi.h
trunk/src/target/arm_adi_v5.c
trunk/src/target/arm_adi_v5.h
trunk/src/target/arm_disassembler.c
trunk/src/target/arm_disassembler.h
trunk/src/target/arm_jtag.c
trunk/src/target/arm_jtag.h
trunk/src/target/arm_simulator.c
trunk/src/target/arm_simulator.h
trunk/src/target/armv4_5.c
trunk/src/target/armv4_5.h
trunk/src/target/armv4_5_cache.c
trunk/src/target/armv4_5_cache.h
trunk/src/target/armv4_5_mmu.c
trunk/src/target/armv4_5_mmu.h
trunk/src/target/armv7m.c
trunk/src/target/armv7m.h
Log:
Transform 'u32' to 'uint32_t' in src/target/arm*
- Replace '\([^_]\)u32' with '\1uint32_t'.
- Replace '^u32' with 'uint32_t'.
Modified: trunk/src/target/arm11.c
===================================================================
--- trunk/src/target/arm11.c 2009-06-18 07:07:59 UTC (rev 2277)
+++ trunk/src/target/arm11.c 2009-06-18 07:08:52 UTC (rev 2278)
@@ -50,7 +50,7 @@
bool arm11_config_memwrite_burst = true;
bool arm11_config_memwrite_error_fatal = true;
-u32 arm11_vcr = 0;
+uint32_t arm11_vcr = 0;
bool arm11_config_memrw_no_increment = false;
bool arm11_config_step_irq_enable = false;
@@ -132,7 +132,7 @@
typedef struct arm11_reg_defs_s
{
char * name;
- u32 num;
+ uint32_t num;
int gdb_num;
enum arm11_regtype type;
} arm11_reg_defs_t;
@@ -311,11 +311,11 @@
* available a pointer to a word holding the
* DSCR can be passed. Otherwise use NULL.
*/
-int arm11_check_init(arm11_common_t * arm11, u32 * dscr)
+int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr)
{
FNC_INFO;
- u32 dscr_local_tmp_copy;
+ uint32_t dscr_local_tmp_copy;
if (!dscr)
{
@@ -408,7 +408,7 @@
/* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
ARM1136 seems to require this to issue ITR's as well */
- u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
+ uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
/* this executes JTAG queue: */
@@ -430,7 +430,7 @@
/* mcr 15, 0, r0, cr7, cr10, {4} */
arm11_run_instr_no_data1(arm11, 0xee070f9a);
- u32 dscr = arm11_read_DSCR(arm11);
+ uint32_t dscr = arm11_read_DSCR(arm11);
LOG_DEBUG("DRAIN, DSCR %08x", dscr);
@@ -579,7 +579,7 @@
/* spec says clear wDTR and rDTR; we assume they are clear as
otherwise our programming would be sloppy */
{
- u32 DSCR;
+ uint32_t DSCR;
CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
@@ -668,7 +668,7 @@
if (arm11->trst_active)
return ERROR_OK;
- u32 dscr;
+ uint32_t dscr;
CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
@@ -717,7 +717,7 @@
}
/* target request support */
-int arm11_target_request_data(struct target_s *target, u32 size, uint8_t *buffer)
+int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer)
{
FNC_INFO_NOTIMPLEMENTED;
@@ -755,7 +755,7 @@
CHECK_RETVAL(jtag_execute_queue());
- u32 dscr;
+ uint32_t dscr;
while (1)
{
@@ -779,7 +779,7 @@
return ERROR_OK;
}
-int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
+int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
{
FNC_INFO;
@@ -856,7 +856,7 @@
while (1)
{
- u32 dscr;
+ uint32_t dscr;
CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
@@ -884,7 +884,7 @@
return ERROR_OK;
}
-int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
+int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
{
FNC_INFO;
@@ -906,7 +906,7 @@
/** \todo TODO: Thumb not supported here */
- u32 next_instruction;
+ uint32_t next_instruction;
CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
@@ -975,7 +975,7 @@
while (1)
{
- u32 dscr;
+ uint32_t dscr;
CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
@@ -1090,9 +1090,9 @@
* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
* count: number of items of <size>
*/
-int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
+int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
- /** \todo TODO: check if buffer cast to u32* and uint16_t* might cause alignment problems */
+ /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
FNC_INFO;
@@ -1124,7 +1124,7 @@
arm11_run_instr_no_data1(arm11,
!arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
- u32 res;
+ uint32_t res;
/* MCR p14,0,R1,c0,c5,0 */
arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
@@ -1143,7 +1143,7 @@
arm11_run_instr_no_data1(arm11,
!arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
- u32 res;
+ uint32_t res;
/* MCR p14,0,R1,c0,c5,0 */
arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
@@ -1157,9 +1157,9 @@
case 4:
{
- u32 instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
- /** \todo TODO: buffer cast to u32* causes alignment warnings */
- u32 *words = (u32 *)buffer;
+ uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
+ /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
+ uint32_t *words = (uint32_t *)buffer;
/* LDC p14,c5,[R0],#4 */
/* LDC p14,c5,[R0] */
@@ -1173,7 +1173,7 @@
return ERROR_OK;
}
-int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
+int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
FNC_INFO;
@@ -1234,10 +1234,10 @@
}
case 4: {
- u32 instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
+ uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
- /** \todo TODO: buffer cast to u32* causes alignment warnings */
- u32 *words = (u32*)buffer;
+ /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
+ uint32_t *words = (uint32_t*)buffer;
if (!arm11_config_memwrite_burst)
{
@@ -1260,7 +1260,7 @@
/* r0 verification */
if (!arm11_config_memrw_no_increment)
{
- u32 r0;
+ uint32_t r0;
/* MCR p14,0,R0,c0,c5,0 */
arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
@@ -1285,7 +1285,7 @@
/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
-int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, uint8_t *buffer)
+int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer)
{
FNC_INFO;
@@ -1302,7 +1302,7 @@
* fallback code will read data from the target and calculate the CRC on the
* host.
*/
-int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
+int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
{
return ERROR_FAIL;
}
@@ -1369,14 +1369,14 @@
// HACKHACKHACK - FIXME mode/state
/* target algorithm support */
int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
- int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point,
+ int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point,
int timeout_ms, void *arch_info)
{
arm11_common_t *arm11 = target->arch_info;
// enum armv4_5_state core_state = arm11->core_state;
// enum armv4_5_mode core_mode = arm11->core_mode;
- u32 context[16];
- u32 cpsr;
+ uint32_t context[16];
+ uint32_t cpsr;
int exit_breakpoint_size = 0;
int retval = ERROR_OK;
LOG_DEBUG("Running algorithm");
@@ -1819,7 +1819,7 @@
return ERROR_OK;
}
-const u32 arm11_coproc_instruction_limits[] =
+const uint32_t arm11_coproc_instruction_limits[] =
{
15, /* coprocessor */
7, /* opcode 1 */
@@ -1879,7 +1879,7 @@
return ERROR_TARGET_NOT_HALTED;
}
- u32 values[6];
+ uint32_t values[6];
for (size_t i = 0; i < (read ? 5 : 6); i++)
{
@@ -1894,7 +1894,7 @@
}
}
- u32 instr = 0xEE000010 |
+ uint32_t instr = 0xEE000010 |
(values[0] << 8) |
(values[1] << 21) |
(values[2] << 16) |
@@ -1908,7 +1908,7 @@
if (read)
{
- u32 result;
+ uint32_t result;
arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
Modified: trunk/src/target/arm11.h
===================================================================
--- trunk/src/target/arm11.h 2009-06-18 07:07:59 UTC (rev 2277)
+++ trunk/src/target/arm11.h 2009-06-18 07:08:52 UTC (rev 2278)
@@ -65,7 +65,7 @@
typedef struct arm11_register_history_s
{
- u32 value;
+ uint32_t value;
uint8_t valid;
}arm11_register_history_t;
@@ -84,8 +84,8 @@
/** \name Processor type detection */
/*@{*/
- u32 device_id; /**< IDCODE readout */
- u32 didr; /**< DIDR readout (debug capabilities) */
+ uint32_t device_id; /**< IDCODE readout */
+ uint32_t didr; /**< DIDR readout (debug capabilities) */
uint8_t implementor; /**< DIDR Implementor readout */
size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
@@ -95,7 +95,7 @@
debug_version; /**< ARM debug architecture from DIDR */
/*@}*/
- u32 last_dscr; /**< Last retrieved DSCR value;
+ uint32_t last_dscr; /**< Last retrieved DSCR value;
Use only for debug message generation */
bool trst_active;
@@ -108,7 +108,7 @@
/*@{*/
reg_t * reg_list; /**< target register list */
- u32 reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
+ uint32_t reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
/*@}*/
@@ -181,7 +181,7 @@
typedef struct arm11_reg_state_s
{
- u32 def_index;
+ uint32_t def_index;
target_t * target;
} arm11_reg_state_t;
@@ -191,12 +191,12 @@
int arm11_arch_state(struct target_s *target);
/* target request support */
-int arm11_target_request_data(struct target_s *target, u32 size, uint8_t *buffer);
+int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer);
/* target execution control */
int arm11_halt(struct target_s *target);
-int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
-int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
+int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
+int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints);
int arm11_examine(struct target_s *target);
/* target reset control */
@@ -211,13 +211,13 @@
* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
* count: number of items of <size>
*/
-int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
-int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
+int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
-int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, uint8_t *buffer);
+int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer);
-int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
+int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum);
/* target break-/watchpoint control
* rw: 0 = write, 1 = read, 2 = access
@@ -228,7 +228,7 @@
int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
/* target algorithm support */
-int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
+int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info);
int arm11_register_commands(struct command_context_s *cmd_ctx);
int arm11_target_create(struct target_s *target, Jim_Interp *interp);
@@ -248,22 +248,22 @@
void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
void arm11_add_IR (arm11_common_t * arm11, uint8_t instr, tap_state_t state);
void arm11_add_debug_SCAN_N (arm11_common_t * arm11, uint8_t chain, tap_state_t state);
-void arm11_add_debug_INST (arm11_common_t * arm11, u32 inst, uint8_t * flag, tap_state_t state);
-int arm11_read_DSCR (arm11_common_t * arm11, u32 *dscr);
-int arm11_write_DSCR (arm11_common_t * arm11, u32 dscr);
+void arm11_add_debug_INST (arm11_common_t * arm11, uint32_t inst, uint8_t * flag, tap_state_t state);
+int arm11_read_DSCR (arm11_common_t * arm11, uint32_t *dscr);
+int arm11_write_DSCR (arm11_common_t * arm11, uint32_t dscr);
-enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr);
+enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr);
void arm11_run_instr_data_prepare (arm11_common_t * arm11);
void arm11_run_instr_data_finish (arm11_common_t * arm11);
-int arm11_run_instr_no_data (arm11_common_t * arm11, u32 * opcode, size_t count);
-void arm11_run_instr_no_data1 (arm11_common_t * arm11, u32 opcode);
-int arm11_run_instr_data_to_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
-int arm11_run_instr_data_to_core_noack (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
-int arm11_run_instr_data_to_core1 (arm11_common_t * arm11, u32 opcode, u32 data);
-int arm11_run_instr_data_from_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
-void arm11_run_instr_data_from_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 * data);
-void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 data);
+int arm11_run_instr_no_data (arm11_common_t * arm11, uint32_t * opcode, size_t count);
+void arm11_run_instr_no_data1 (arm11_common_t * arm11, uint32_t opcode);
+int arm11_run_instr_data_to_core (arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count);
+int arm11_run_instr_data_to_core_noack (arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count);
+int arm11_run_instr_data_to_core1 (arm11_common_t * arm11, uint32_t opcode, uint32_t data);
+int arm11_run_instr_data_from_core (arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count);
+void arm11_run_instr_data_from_core_via_r0 (arm11_common_t * arm11, uint32_t opcode, uint32_t * data);
+void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, uint32_t opcode, uint32_t data);
int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state);
int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state);
@@ -276,7 +276,7 @@
{
bool write; /**< Access mode: true for write, false for read. */
uint8_t address; /**< Register address mode. Use enum #arm11_sc7 */
- u32 value; /**< If write then set this to value to be written.
+ uint32_t value; /**< If write then set this to value to be written.
In read mode this receives the read value when the
function returns. */
} arm11_sc7_action_t;
@@ -285,8 +285,8 @@
/* Mid-level helper functions */
void arm11_sc7_clear_vbw(arm11_common_t * arm11);
-void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value);
+void arm11_sc7_set_vcr(arm11_common_t * arm11, uint32_t value);
-int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);
+int arm11_read_memory_word(arm11_common_t * arm11, uint32_t address, uint32_t * result);
#endif /* ARM11_H */
Modified: trunk/src/target/arm11_dbgtap.c
===================================================================
--- trunk/src/target/arm11_dbgtap.c 2009-06-18 07:07:59 UTC (rev 2277)
+++ trunk/src/target/arm11_dbgtap.c 2009-06-18 07:08:52 UTC (rev 2278)
@@ -195,7 +195,7 @@
*
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
-void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, uint8_t * flag, tap_state_t state)
+void arm11_add_debug_INST(arm11_common_t * arm11, uint32_t inst, uint8_t * flag, tap_state_t state)
{
JTAG_DEBUG("INST <= 0x%08x", inst);
@@ -217,13 +217,13 @@
*
* \remarks This is a stand-alone function that executes the JTAG command queue.
*/
-int arm11_read_DSCR(arm11_common_t * arm11, u32 *value)
+int arm11_read_DSCR(arm11_common_t * arm11, uint32_t *value)
{
arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
- u32 dscr;
+ uint32_t dscr;
scan_field_t chain1_field;
arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field);
@@ -251,7 +251,7 @@
*
* \remarks This is a stand-alone function that executes the JTAG command queue.
*/
-int arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
+int arm11_write_DSCR(arm11_common_t * arm11, uint32_t dscr)
{
arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
@@ -280,7 +280,7 @@
* \return Debug reason
*
*/
-enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr)
+enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr)
{
switch (dscr & ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK)
{
@@ -364,7 +364,7 @@
* \param count Number of opcodes to execute
*
*/
-int arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
+int arm11_run_instr_no_data(arm11_common_t * arm11, uint32_t * opcode, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
@@ -396,7 +396,7 @@
* \param opcode ARM opcode
*
*/
-void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode)
+void arm11_run_instr_no_data1(arm11_common_t * arm11, uint32_t opcode)
{
arm11_run_instr_no_data(arm11, &opcode, 1);
}
@@ -415,7 +415,7 @@
* \param count Number of data words and instruction repetitions
*
*/
-int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
+int arm11_run_instr_data_to_core(arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
@@ -425,7 +425,7 @@
scan_field_t chain5_fields[3];
- u32 Data;
+ uint32_t Data;
uint8_t Ready;
uint8_t nRetry;
@@ -502,7 +502,7 @@
* \param count Number of data words and instruction repetitions
*
*/
-int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
+int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
@@ -573,7 +573,7 @@
* \param data Data word to be passed to the core via DTR
*
*/
-int arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
+int arm11_run_instr_data_to_core1(arm11_common_t * arm11, uint32_t opcode, uint32_t data)
{
return arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
}
@@ -592,7 +592,7 @@
* \param count Number of data words and instruction repetitions
*
*/
-int arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
+int arm11_run_instr_data_from_core(arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
@@ -602,7 +602,7 @@
scan_field_t chain5_fields[3];
- u32 Data;
+ uint32_t Data;
uint8_t Ready;
uint8_t nRetry;
@@ -640,7 +640,7 @@
* \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
*
*/
-void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 * data)
+void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, uint32_t opcode, uint32_t * data)
{
arm11_run_instr_no_data1(arm11, opcode);
@@ -660,7 +660,7 @@
* \param data Data word that will be written to r0 before \p opcode is executed
*
*/
-void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 data)
+void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, uint32_t opcode, uint32_t data)
{
/* MRC p14,0,r0,c0,c5,0 */
arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data);
@@ -686,10 +686,10 @@
scan_field_t chain7_fields[3];
uint8_t nRW;
- u32 DataOut;
+ uint32_t DataOut;
uint8_t AddressOut;
uint8_t Ready;
- u32 DataIn;
+ uint32_t DataIn;
uint8_t AddressIn;
arm11_setup_field(arm11, 1, &nRW, &Ready, chain7_fields + 0);
@@ -786,7 +786,7 @@
* \param arm11 Target state variable.
* \param value Value to be written
*/
-void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value)
+void arm11_sc7_set_vcr(arm11_common_t * arm11, uint32_t value)
{
arm11_sc7_action_t set_vcr;
@@ -807,7 +807,7 @@
* \param result Pointer where to store result
*
*/
-int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
+int arm11_read_memory_word(arm11_common_t * arm11, uint32_t address, uint32_t * result)
{
arm11_run_instr_data_prepare(arm11);
Modified: trunk/src/target/arm720t.c
===================================================================
--- trunk/src/target/arm720t.c 2009-06-18 07:07:59 UTC (rev 2277)
+++ trunk/src/target/arm720t.c 2009-06-18 07:08:52 UTC (rev 2278)
@@ -43,8 +43,8 @@
int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm720t_quit(void);
int arm720t_arch_state(struct target_s *target);
-int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
-int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
+int arm720t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+int arm720t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int arm720t_soft_reset_halt(struct target_s *target);
target_type_t arm720t_target =
@@ -84,7 +84,7 @@
.quit = arm720t_quit
};
-int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int clock)
+int arm720t_scan_cp15(target_t *target, uint32_t out, uint32_t *in, int instruction, int clock)
{
int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -146,7 +146,7 @@
return ERROR_OK;
}
-int arm720t_read_cp15(target_t *target, u32 opcode, u32 *value)
+int arm720t_read_cp15(target_t *target, uint32_t opcode, uint32_t *value)
{
/* fetch CP15 opcode */
arm720t_scan_cp15(target, opcode, NULL, 1, 1);
@@ -163,7 +163,7 @@
return ERROR_OK;
}
-int arm720t_write_cp15(target_t *target, u32 opcode, u32 value)
+int arm720t_write_cp15(target_t *target, uint32_t opcode, uint32_t value)
{
/* fetch CP15 opcode */
arm720t_scan_cp15(target, opcode, NULL, 1, 1);
@@ -179,9 +179,9 @@
return ERROR_OK;
}
-u32 arm720t_get_ttb(target_t *target)
+uint32_t arm720t_get_ttb(target_t *target)
{
- u32 ttb = 0x0;
+ uint32_t ttb = 0x0;
arm720t_read_cp15(target, 0xee120f10, &ttb);
jtag_execute_queue();
@@ -193,7 +193,7 @@
void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
{
- u32 cp15_control;
+ uint32_t cp15_control;
/* read cp15 control register */
arm720t_read_cp15(target, 0xee110f10, &cp15_control);
@@ -210,7 +210,7 @@
void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
{
- u32 cp15_control;
+ uint32_t cp15_control;
/* read cp15 control register */
arm720t_read_cp15(target, 0xee110f10, &cp15_control);
@@ -329,7 +329,7 @@
return ERROR_OK;
}
-int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
+int arm720t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -349,7 +349,7 @@
return retval;
}
-int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
+int arm720t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
int retval;
@@ -527,11 +527,11 @@
/* one or more argument, access a single register (write if second argument is given */
if (argc >= 1)
{
- u32 opcode = strtoul(args[0], NULL, 0);
+ uint32_t opcode = strtoul(args[0], NULL, 0);
if (argc == 1)
{
- u32 value;
+ uint32_t value;
if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
{
command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
@@ -547,7 +547,7 @@
}
else if (argc == 2)
{
- u32 value = strtoul(args[1], NULL, 0);
+ uint32_t value = strtoul(args[1], NULL, 0);
if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
{
command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
Modified: trunk/src/target/arm720t.h
===================================================================
--- trunk/src/target/arm720t.h 2009-06-18 07:07:59 UTC (rev 2277)
+++ trunk/src/target/arm720t.h 2009-06-18 07:08:52 UTC (rev 2278)
@@ -27,12 +27,12 @@
typedef struct arm720t_common_s
{
- u32 common_magic;
+ uint32_t common_magic;
armv4_5_mmu_common_t armv4_5_mmu;
arm7tdmi_common_t arm7tdmi_common;
- u32 cp15_control_reg;
- u32 fsr_reg;
- u32 far_reg;
+ uint32_t cp15_control_reg;
+ uint32_t fsr_reg;
+ uint32_t far_reg;
} arm720t_common_t;
#endif /* ARM720T_H */
Modified: trunk/src/target/arm7_9_common.c
===================================================================
--- trunk/src/target/arm7_9_common.c 2009-06-18 07:07:59 UTC (rev 2277)
+++ trunk/src/target/arm7_9_common.c 2009-06-18 07:08:52 UTC (rev 2278)
@@ -229,7 +229,7 @@
if (breakpoint->type == BKPT_HARD)
{
/* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
- u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
+ uint32_t mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
/* reassign a hw breakpoint */
if (breakpoint->set==0)
@@ -272,7 +272,7 @@
if (breakpoint->length == 4)
{
- u32 verify = 0xffffffff;
+ uint32_t verify = 0xffffffff;
/* keep the original instruction in target endianness */
if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
{
@@ -371,7 +371,7 @@
/* restore original instruction (kept in target endianness) */
if (breakpoint->length == 4)
{
- u32 current_instr;
+ uint32_t current_instr;
/* check that user program as not modified breakpoint instruction */
if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)¤t_instr)) != ERROR_OK)
{
@@ -506,7 +506,7 @@
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
int rw_mask = 1;
- u32 mask;
+ uint32_t mask;
mask = watchpoint->length - 1;
@@ -781,16 +781,16 @@
* @param buffer Pointer to the buffer that will hold the data
* @return The result of receiving data from the Embedded ICE unit
*/
-int arm7_9_target_request_data(target_t *target, u32 size, uint8_t *buffer)
+int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
- u32 *data;
+ uint32_t *data;
int retval = ERROR_OK;
- u32 i;
+ uint32_t i;
- data = malloc(size * (sizeof(u32)));
+ data = malloc(size * (sizeof(uint32_t)));
retval = embeddedice_receive(jtag_info, data, size);
@@ -840,7 +840,7 @@
/* check W bit */
if (buf_get_u32(dcc_control->value, 1, 1) == 1)
{
- u32 request;
+ uint32_t request;
if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK)
{
@@ -921,7 +921,7 @@
if (check_pc)
{
reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
- u32 t=*((u32 *)reg->value);
+ uint32_t t=*((uint32_t *)reg->value);
if (t!=0)
{
LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
@@ -1190,7 +1190,7 @@
/* if the target is in Thumb state, change to ARM state */
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
{
- u32 r0_thumb, pc_thumb;
+ uint32_t r0_thumb, pc_thumb;
LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
/* Entered debug from Thumb mode */
armv4_5->core_state = ARMV4_5_STATE_THUMB;
@@ -1310,10 +1310,10 @@
int arm7_9_debug_entry(target_t *target)
{
int i;
- u32 context[16];
- u32* context_p[16];
- u32 r0_thumb, pc_thumb;
- u32 cpsr;
+ uint32_t context[16];
+ uint32_t* context_p[16];
+ uint32_t r0_thumb, pc_thumb;
+ uint32_t cpsr;
int retval;
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -1444,7 +1444,7 @@
/* exceptions other than USR & SYS have a saved program status register */
if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
{
- u32 spsr;
+ uint32_t spsr;
arm7_9->read_xpsr(target, &spsr, 1);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
@@ -1500,8 +1500,8 @@
*/
for (i = 0; i < 6; i++)
{
- u32 mask = 0;
- u32* reg_p[16];
+ uint32_t mask = 0;
+ uint32_t* reg_p[16];
int j;
int valid = 1;
@@ -1515,7 +1515,7 @@
if (!valid)
{
- u32 tmp_cpsr;
+ uint32_t tmp_cpsr;
/* change processor mode (and mask T bit) */
tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
@@ -1527,7 +1527,7 @@
{
if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
{
- reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
+ reg_p[j] = (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
mask |= 1 << j;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
@@ -1541,7 +1541,7 @@
/* check if the PSR has to be read */
if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
{
- arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
+ arm7_9->read_xpsr(target, (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
}
@@ -1633,13 +1633,13 @@
if (dirty)
{
- u32 mask = 0x0;
+ uint32_t mask = 0x0;
int num_regs = 0;
- u32 regs[16];
+ uint32_t regs[16];
if (mode_change)
{
- u32 tmp_cpsr;
+ uint32_t tmp_cpsr;
/* change processor mode (mask T bit) */
tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
@@ -1684,7 +1684,7 @@
if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
{
/* restore processor mode (mask T bit) */
- u32 tmp_cpsr;
+ uint32_t tmp_cpsr;
tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
tmp_cpsr |= armv4_5_number_to_mode(i);
@@ -1774,7 +1774,7 @@
}
}
-int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
+int arm7_9_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -1799,7 +1799,7 @@
if (!current)
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
- u32 current_pc;
+ uint32_t current_pc;
current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
/* the front-end may request us not to handle breakpoints */
@@ -1814,10 +1814,10 @@
}
/* calculate PC of next instruction */
- u32 next_pc;
+ uint32_t next_pc;
if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
{
- u32 current_opcode;
+ uint32_t current_opcode;
target_read_u32(target, current_pc, ¤t_opcode);
LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
return retval;
@@ -1934,12 +1934,12 @@
return ERROR_OK;
}
-void arm7_9_enable_eice_step(target_t *target, u32 next_pc)
+void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- u32 current_pc;
+ uint32_t current_pc;
current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
if(next_pc != current_pc)
@@ -1988,7 +1988,7 @@
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
}
-int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
+int arm7_9_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -2005,7 +2005,7 @@
if (!current)
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
- u32 current_pc;
+ uint32_t current_pc;
current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
/* the front-end may request us not to handle breakpoints */
@@ -2019,10 +2019,10 @@
target->debug_reason = DBG_REASON_SINGLESTEP;
/* calculate PC of next instruction */
- u32 next_pc;
+ uint32_t next_pc;
if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
{
- u32 current_opcode;
+ uint32_t current_opcode;
target_read_u32(target, current_pc, ¤t_opcode);
LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
return retval;
@@ -2083,8 +2083,8 @@
int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
{
- u32* reg_p[16];
- u32 value;
+ uint32_t* reg_p[16];
+ uint32_t value;
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -2101,7 +2101,7 @@
&& (mode != armv4_5->core_mode)
&& (reg_mode != ARMV4_5_MODE_ANY))
{
- u32 tmp_cpsr;
+ uint32_t tmp_cpsr;
/* change processor mode (mask T bit) */
tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
@@ -2147,9 +2147,9 @@
return ERROR_OK;
}
-int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
+int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value)
{
- u32 reg[16];
+ uint32_t reg[16];
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -2164,7 +2164,7 @@
if ((mode != ARMV4_5_MODE_ANY)
&& (mode != armv4_5->core_mode)
&& (reg_mode != ARMV4_5_MODE_ANY)) {
- u32 tmp_cpsr;
+ uint32_t tmp_cpsr;
/* change processor mode (mask T bit) */
tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
@@ -2208,16 +2208,16 @@
return jtag_execute_queue();
}
-int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
+int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- u32 reg[16];
- u32 num_accesses = 0;
+ uint32_t reg[16];
+ uint32_t num_accesses = 0;
int thisrun_accesses;
int i;
- u32 cpsr;
+ uint32_t cpsr;
int retval;
int last_reg = 0;
@@ -2247,7 +2247,7 @@
case 4:
while (num_accesses < count)
{
- u32 reg_list;
+ uint32_t reg_list;
thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
@@ -2281,7 +2281,7 @@
case 2:
while (num_accesses < count)
{
- u32 reg_list;
+ uint32_t reg_list;
thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
@@ -2319,7 +2319,7 @@
case 1:
while (num_accesses < count)
{
- u32 reg_list;
+ uint32_t reg_list;
thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
@@ -2384,17 +2384,17 @@
return ERROR_OK;
}
-int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
+int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
- u32 reg[16];
- u32 num_accesses = 0;
+ uint32_t reg[16];
+ uint32_t num_accesses = 0;
int thisrun_accesses;
int i;
- u32 cpsr;
+ uint32_t cpsr;
int retval;
int last_reg = 0;
@@ -2428,7 +2428,7 @@
case 4:
while (num_accesses < count)
{
- u32 reg_list;
+ uint32_t reg_list;
thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
@@ -2462,7 +2462,7 @@
case 2:
while (num_accesses < count)
{
- u32 reg_list;
+ uint32_t reg_list;
thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
@@ -2499,7 +2499,7 @@
case 1:
while (num_accesses < count)
{
- u32 reg_list;
+ uint32_t reg_list;
thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
@@ -2570,7 +2570,7 @@
static int dcc_count;
static uint8_t *dcc_buffer;
-static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)
+static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)
{
int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -2615,15 +2615,15 @@
return target_wait_state(target, TARGET_HALTED, 500);
}
-static const u32 dcc_code[] =
+static const uint32_t dcc_code[] =
{
/* MRC TST BNE MRC STR B */
0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
};
-int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info));
+int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info));
-int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, uint8_t *buffer)
+int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -2676,7 +2676,7 @@
if (retval==ERROR_OK)
{
- u32 endaddress=buf_get_u32(reg_params[0].value, 0, 32);
+ uint32_t endaddress=buf_get_u32(reg_params[0].value, 0, 32);
if (endaddress!=(address+count*4))
{
LOG_ERROR("DCC write failed, expected end address 0x%08x got 0x%0x", (address+count*4), endaddress);
@@ -2689,14 +2689,14 @@
return retval;
}
-int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
+int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
{
working_area_t *crc_algorithm;
armv4_5_algorithm_t armv4_5_info;
reg_param_t reg_params[2];
int retval;
- u32 arm7_9_crc_code[] = {
+ uint32_t arm7_9_crc_code[] = {
0xE1A02000, /* mov r2, r0 */
0xE3E00000, /* mov r0, #0xffffffff */
0xE1A03001, /* mov r3, r1 */
@@ -2724,7 +2724,7 @@
0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */
};
- u32 i;
+ uint32_t i;
if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK)
{
@@ -2732,9 +2732,9 @@
}
/* convert flash writing code into a buffer in target endianness */
- for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++)
+ for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(uint32_t)); i++)
{
- if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]))!=ERROR_OK)
+ if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i]))!=ERROR_OK)
{
return retval;
}
@@ -2770,15 +2770,15 @@
return ERROR_OK;
}
-int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank)
+int arm7_9_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank)
{
working_area_t *erase_check_algorithm;
reg_param_t reg_params[3];
armv4_5_algorithm_t armv4_5_info;
int retval;
- u32 i;
+ uint32_t i;
- u32 erase_check_code[] =
+ uint32_t erase_check_code[] =
{
/* loop: */
0xe4d03001, /* ldrb r3, [r0], #1 */
@@ -2796,8 +2796,8 @@
}
/* convert flash writing code into a buffer in target endianness */
- for (i = 0; i < (sizeof(erase_check_code)/sizeof(u32)); i++)
- if ((retval = target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i])) != ERROR_OK)
+ for (i = 0; i < (sizeof(erase_check_code)/sizeof(uint32_t)); i++)
+ if ((retval = target_write_u32(target, erase_check_algorithm->address + i*sizeof(uint32_t), erase_check_code[i])) != ERROR_OK)
{
return retval;
}
@@ -2863,7 +2863,7 @@
int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
- u32 value;
+ uint32_t value;
int spsr;
int retval;
target_t *target = get_current_target(cmd_ctx);
@@ -2907,7 +2907,7 @@
int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
- u32 value;
+ uint32_t value;
int rotate;
int spsr;
int retval;
@@ -2949,8 +2949,8 @@
int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
- u32 value;
- u32 mode;
+ uint32_t value;
+ uint32_t mode;
int num;
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
Modified: trunk/src/target/arm7_9_common.h
===================================================================
--- trunk/src/target/arm7_9_common.h 2009-06-18 07:07:59 UTC (rev 2277)
+++ trunk/src/target/arm7_9_common.h 2009-06-18 07:08:52 UTC (rev 2278)
@@ -39,12 +39,12 @@
*/
typedef struct arm7_9_common_s
{
- u32 common_magic;
+ uint32_t common_magic;
arm_jtag_t jtag_info; /**< JTAG information for target */
reg_cache_t *eice_cache; /**< Embedded ICE register cache */
- u32 arm_bkpt; /**< ARM breakpoint instruction */
+ uint32_t arm_bkpt; /**< ARM breakpoint instruction */
uint16_t thumb_bkpt; /**< Thumb breakpoint instruction */
int sw_breakpoints_added; /**< Specifies which watchpoint software breakpoints are setup on */
int breakpoint_count; /**< Current number of set breakpoints */
@@ -73,29 +73,29 @@
int (*examine_debug_reason)(target_t *target); /**< Function for determining why debug state was entered */
- void (*change_to_arm)(target_t *target, u32 *r0, u32 *pc); /**< Function for changing from Thumb to ARM mode */
+ void (*change_to_arm)(target_t *target, uint32_t *r0, uint32_t *pc); /**< Function for changing from Thumb to ARM mode */
- void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]); /**< Function for reading the core registers */
- void (*read_core_regs_target_buffer)(target_t *target, u32 mask, void *buffer, int size);
- void (*read_xpsr)(target_t *target, u32 *xpsr, int spsr); /**< Function for reading CPSR or SPSR */
+ void (*read_core_regs)(target_t *target, uint32_t mask, uint32_t *core_regs[16]); /**< Function for reading the core registers */
+ void (*read_core_regs_target_buffer)(target_t *target, uint32_t mask, void *buffer, int size);
+ void (*read_xpsr)(target_t *target, uint32_t *xpsr, int spsr); /**< Function for reading CPSR or SPSR */
- void (*write_xpsr)(target_t *target, u32 xpsr, int spsr); /**< Function for writing to CPSR or SPSR */
+ void (*write_xpsr)(target_t *target, uint32_t xpsr, int spsr); /**< Function for writing to CPSR or SPSR */
void (*write_xpsr_im8)(target_t *target, uint8_t xpsr_im, int rot, int spsr); /**< Function for writing an immediate value to CPSR or SPSR */
- void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
+ void (*write_core_regs)(target_t *target, uint32_t mask, uint32_t core_regs[16]);
- void (*load_word_regs)(target_t *target, u32 mask);
+ void (*load_word_regs)(target_t *target, uint32_t mask);
void (*load_hword_reg)(target_t *target, int num);
void (*load_byte_reg)(target_t *target, int num);
- void (*store_word_regs)(target_t *target, u32 mask);
+ void (*store_word_regs)(target_t *target, uint32_t mask);
void (*store_hword_reg)(target_t *target, int num);
void (*store_byte_reg)(target_t *target, int num);
- void (*write_pc)(target_t *target, u32 pc); /**< Function for writing to the program counter */
+ void (*write_pc)(target_t *target, uint32_t pc); /**< Function for writing to the program counter */
void (*branch_resume)(target_t *target);
void (*branch_resume_thumb)(target_t *target);
- void (*enable_single_step)(target_t *target, u32 next_pc);
+ void (*enable_single_step)(target_t *target, uint32_t next_pc);
void (*disable_single_step)(target_t *target);
void (*set_special_dbgrq)(target_t *target); /**< Function for setting DBGRQ if the normal way won't work */
@@ -115,7 +115,7 @@
int arm7_9_poll(target_t *target);
-int arm7_9_target_request_data(target_t *target, u32 size, uint8_t *buffer);
+int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer);
int arm7_9_setup(target_t *target);
int arm7_9_assert_reset(target_t *target);
@@ -128,23 +128,23 @@
int arm7_9_halt(target_t *target);
int arm7_9_full_context(target_t *target);
int arm7_9_restore_context(target_t *target);
-int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
-int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
+int arm7_9_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
+int arm7_9_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints);
int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode);
-int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
-int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
-int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, uint8_t *buffer);
-int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
-int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank);
+int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer);
+int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum);
+int arm7_9_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank);
-int arm7_9_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_prams, reg_param_t *reg_param, u32 entry_point, void *arch_info);
+int arm7_9_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_prams, reg_param_t *reg_param, uint32_t entry_point, void *arch_info);
int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
-void arm7_9_enable_eice_step(target_t *target, u32 next_pc);
+void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc);
void arm7_9_disable_eice_step(target_t *target);
int arm7_9_execute_sys_speed(struct target_s *target);
Modified: trunk/src/target/arm7tdmi.c
===================================================================
--- trunk/src/target/arm7tdmi.c 2009-06-18 07:07:59 UTC (rev 2277)
+++ trunk/src/target/arm7tdmi.c 2009-06-18 07:08:52 UTC (rev 2278)
@@ -139,9 +139,9 @@
}
static int arm7tdmi_num_bits[]={1, 32};
-static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int breakpoint)
+static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, uint32_t out, int breakpoint)
{
- u32 values[2]={breakpoint, flip_u32(out, 32)};
+ uint32_t values[2]={breakpoint, flip_u32(out, 32)};
jtag_add_dr_out(jtag_info->tap,
2,
@@ -155,7 +155,7 @@
}
/* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */
-static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *deprecated, int breakpoint)
+static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, uint32_t out, uint32_t *deprecated, int breakpoint)
{
jtag_set_end_state(TAP_DRPAUSE);
arm_jtag_scann(jtag_info, 0x1);
@@ -165,7 +165,7 @@
}
/* clock the target, reading the databus */
-int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
+int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in)
{
int retval = ERROR_OK;
scan_field_t fields[2];
@@ -216,7 +216,7 @@
void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip)
{
- u32 readback=le_to_h_u32(tmp);
+ uint32_t readback=le_to_h_u32(tmp);
if (flip)
readback=flip_u32(readback, 32);
switch (size)
@@ -292,7 +292,7 @@
if (in)
{
- LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
+ LOG_DEBUG("in: 0x%8.8x", *(uint32_t*)in);
}
else
{
@@ -304,7 +304,7 @@
return ERROR_OK;
}
-void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
+void arm7tdmi_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -361,7 +361,7 @@
* The solution is to arrange for a large out/in scan in this loop and
* and convert data afterwards.
*/
-void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
+void arm7tdmi_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16])
{
int i;
/* get pointers to arch-specific information */
@@ -387,7 +387,7 @@
}
}
-void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
+void arm7tdmi_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size)
{
int i;
/* get pointers to arch-specific information */
@@ -395,7 +395,7 @@
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
- u32 *buf_u32 = buffer;
+ uint32_t *buf_u32 = buffer;
uint16_t *buf_u16 = buffer;
uint8_t *buf_u8 = buffer;
@@ -430,7 +430,7 @@
}
}
-void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
+void arm7tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -450,7 +450,7 @@
arm7tdmi_clock_data_in(jtag_info, xpsr);
}
-void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
+void arm7tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -500,7 +500,7 @@
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
}
-void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
+void arm7tdmi_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16])
{
int i;
/* get pointers to arch-specific information */
@@ -527,7 +527,7 @@
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
}
-void arm7tdmi_load_word_regs(target_t *target, u32 mask)
+void arm7tdmi_load_word_regs(target_t *target, uint32_t mask)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -566,7 +566,7 @@
arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), NULL, 0);
}
-void arm7tdmi_store_word_regs(target_t *target, u32 mask)
+void arm7tdmi_store_word_regs(target_t *target, uint32_t mask)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -605,7 +605,7 @@
arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), NULL, 0);
}
-void arm7tdmi_write_pc(target_t *target, u32 pc)
+void arm7tdmi_write_pc(target_t *target, uint32_t pc)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
Modified: trunk/src/target/arm920t.c
===================================================================
--- trunk/src/target/arm920t.c 2009-06-18 07:07:59 UTC (rev 2277)
+++ trunk/src/target/arm920t.c 2009-06-18 07:08:52 UTC (rev 2278)
@@ -48,8 +48,8 @@
int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm920t_quit(void);
int arm920t_arch_state(struct target_s *target);
-int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
-int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
+int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int arm920t_soft_reset_halt(struct target_s *target);
#define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
@@ -93,7 +93,7 @@
.quit = arm920t_quit
};
-int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
+int arm920t_read_cp15_physical(target_t *target, int reg_addr, uint32_t *value)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -143,7 +143,7 @@
return ERROR_OK;
}
-int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
+int arm920t_write_cp15_physical(target_t *target, int reg_addr, uint32_t value)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -189,7 +189,7 @@
return ERROR_OK;
}
-int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
+int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode, uint32_t arm_opcode)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -244,12 +244,12 @@
return ERROR_OK;
}
-int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address, u32 *value)
+int arm920t_read_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t address, uint32_t *value)
{
armv4_5_common_t *armv4_5 = target->arch_info;
- u32* regs_p[1];
- u32 regs[2];
- u32 cp15c15 = 0x0;
+ uint32_t* regs_p[1];
+ uint32_t regs[2];
+ uint32_t cp15c15 = 0x0;
/* load address into R1 */
regs[1] = address;
@@ -287,11 +287,11 @@
return ERROR_OK;
}
-int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value, u32 address)
+int arm920t_write_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t value, uint32_t address)
{
- u32 cp15c15 = 0x0;
+ uint32_t cp15c15 = 0x0;
armv4_5_common_t *armv4_5 = target->arch_info;
- u32 regs[2];
+ uint32_t regs[2];
/* load value, address into R0, R1 */
regs[0] = value;
@@ -325,10 +325,10 @@
return ERROR_OK;
}
-u32 arm920t_get_ttb(target_t *target)
+uint32_t arm920t_get_ttb(target_t *target)
{
int retval;
- u32 ttb = 0x0;
+ uint32_t ttb = 0x0;
if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
return retval;
@@ -338,7 +338,7 @@
void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
{
- u32 cp15_control;
+ uint32_t cp15_control;
/* read cp15 control register */
arm920t_read_cp15_physical(target, 0x2, &cp15_control);
@@ -358,7 +358,7 @@
void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
{
- u32 cp15_control;
+ uint32_t cp15_control;
/* read cp15 control register */
arm920t_read_cp15_physical(target, 0x2, &cp15_control);
@@ -378,7 +378,7 @@
void arm920t_post_debug_entry(target_t *target)
{
- u32 cp15c15;
+ uint32_t cp15c15;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
@@ -391,7 +391,7 @@
if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
{
- u32 cache_type_reg;
+ uint32_t cache_type_reg;
/* identify caches */
arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
jtag_execute_queue();
@@ -424,7 +424,7 @@
void arm920t_pre_restore_context(target_t *target)
{
- u32 cp15c15;
+ uint32_t cp15c15;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
@@ -518,7 +518,7 @@
return ERROR_OK;
}
-int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
+int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
int retval;
@@ -527,7 +527,7 @@
return retval;
}
-int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
+int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -543,7 +543,7 @@
if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
{
LOG_DEBUG("D-Cache enabled, writing through to main memory");
- u32 pa, cb, ap;
+ uint32_t pa, cb, ap;
int type, domain;
pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap);
@@ -731,11 +731,11 @@
arm9tdmi_common_t *arm9tdmi;...
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