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[PATCH 1/2] ARM semihosting: add armv7m support
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From: Spencer O. <nt...@us...> - 2001-09-17 00:00:00
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This adds semihosting support for the ARMv7M profile devices.
Currently only been verified on the Cortex-M3 against codesourcery toolchains.
Fix issue with printing to stdout/stderr:
caused by a incorrect SYS_FLEN syscall, fstat is now called rather than lseek.
Signed-off-by: Spencer Oliver <nt...@us...>
---
src/helper/system.h | 2 +
src/target/arm.h | 9 +--
src/target/arm7_9_common.c | 8 +-
src/target/arm_semihosting.c | 148 ++++++++++++++++++++++++++++--------------
src/target/arm_semihosting.h | 17 +++++-
src/target/armv4_5.c | 2 +-
src/target/armv7m.c | 8 +-
src/target/armv7m.h | 1 +
src/target/cortex_m3.c | 44 ++++++++++++-
src/target/target.h | 1 -
10 files changed, 172 insertions(+), 68 deletions(-)
diff --git a/src/helper/system.h b/src/helper/system.h
index 169df1c..af19d01 100644
--- a/src/helper/system.h
+++ b/src/helper/system.h
@@ -50,6 +50,8 @@
#ifdef _WIN32
#include <winsock2.h>
#include <ws2tcpip.h>
+#include <sys/types.h>
+#include <sys/stat.h>
#endif
// --- platform specific headers ---
diff --git a/src/target/arm.h b/src/target/arm.h
index 988266e..54fd698 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -28,7 +28,7 @@
#include <helper/command.h>
#include "target.h"
-
+#include "arm_semihosting.h"
/**
* @file
@@ -108,11 +108,8 @@ struct arm {
/** Flag reporting unavailability of the BKPT instruction. */
bool is_armv4;
- /** Flag reporting whether semihosting is active. */
- bool is_semihosting;
-
- /** Value to be returned by semihosting SYS_ERRNO request. */
- int semihosting_errno;
+ /** info about semi hosting config. */
+ struct arm_semi_hosting semi_hosting_info;
/** Backpointer to the target. */
struct target *target;
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 509e91e..81ea81c 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -896,7 +896,7 @@ int arm7_9_poll(struct target *target)
if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
return retval;
- if (arm_semihosting(target, &retval) != 0)
+ if (armv4_5_semihosting(target, &retval) != 0)
return retval;
if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
@@ -2866,16 +2866,16 @@ COMMAND_HANDLER(handle_arm7_9_semihosting_command)
if (semihosting)
breakpoint_add(target, 8, 4, BKPT_SOFT);
else
- breakpoint_remove(target, 8);
+ breakpoint_remove(target, 8);
}
/* FIXME never let that "catch" be dropped! */
- arm7_9->armv4_5_common.is_semihosting = semihosting;
+ arm7_9->armv4_5_common.semi_hosting_info.is_semihosting = semihosting;
}
command_print(CMD_CTX, "semihosting is %s",
- arm7_9->armv4_5_common.is_semihosting
+ arm7_9->armv4_5_common.semi_hosting_info.is_semihosting
? "enabled" : "disabled");
return ERROR_OK;
diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index f4244c8..434868a 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -36,19 +36,17 @@
#include "arm.h"
#include "armv4_5.h"
+#include "armv7m.h"
+#include "cortex_m3.h"
#include "register.h"
#include "arm_semihosting.h"
#include <helper/binarybuffer.h>
#include <helper/log.h>
-
-static int do_semihosting(struct target *target)
+static int do_semihosting(struct target *target, struct arm_semi_hosting *info)
{
- struct arm *armv4_5 = target_to_arm(target);
- uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
- uint32_t r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
- uint32_t lr = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, ARM_MODE_SVC, 14).value, 0, 32);
- uint32_t spsr = buf_get_u32(armv4_5->spsr->value, 0, 32);;
+ uint32_t r0 = buf_get_u32(info->core_cache->reg_list[0].value, 0, 32);
+ uint32_t r1 = buf_get_u32(info->core_cache->reg_list[1].value, 0, 32);
uint8_t params[16];
int retval, result;
@@ -94,10 +92,10 @@ static int do_semihosting(struct target *target)
result = dup(1);
} else
result = open((char *)fn, mode);
- armv4_5->semihosting_errno = errno;
+ info->semihosting_errno = errno;
} else {
result = -1;
- armv4_5->semihosting_errno = EINVAL;
+ info->semihosting_errno = EINVAL;
}
}
break;
@@ -109,7 +107,7 @@ static int do_semihosting(struct target *target)
else {
int fd = target_buffer_get_u32(target, params+0);
result = close(fd);
- armv4_5->semihosting_errno = errno;
+ info->semihosting_errno = errno;
}
break;
@@ -148,7 +146,7 @@ static int do_semihosting(struct target *target)
uint8_t *buf = malloc(l);
if (!buf) {
result = -1;
- armv4_5->semihosting_errno = ENOMEM;
+ info->semihosting_errno = ENOMEM;
} else {
retval = target_read_buffer(target, a, l, buf);
if (retval != ERROR_OK) {
@@ -156,7 +154,7 @@ static int do_semihosting(struct target *target)
return retval;
}
result = write(fd, buf, l);
- armv4_5->semihosting_errno = errno;
+ info->semihosting_errno = errno;
if (result >= 0)
result = l - result;
free(buf);
@@ -175,10 +173,10 @@ static int do_semihosting(struct target *target)
uint8_t *buf = malloc(l);
if (!buf) {
result = -1;
- armv4_5->semihosting_errno = ENOMEM;
+ info->semihosting_errno = ENOMEM;
} else {
result = read(fd, buf, l);
- armv4_5->semihosting_errno = errno;
+ info->semihosting_errno = errno;
if (result > 0) {
retval = target_write_buffer(target, a, result, buf);
if (retval != ERROR_OK) {
@@ -218,7 +216,7 @@ static int do_semihosting(struct target *target)
int fd = target_buffer_get_u32(target, params+0);
off_t pos = target_buffer_get_u32(target, params+4);
result = lseek(fd, pos, SEEK_SET);
- armv4_5->semihosting_errno = errno;
+ info->semihosting_errno = errno;
if (result == pos)
result = 0;
}
@@ -230,18 +228,14 @@ static int do_semihosting(struct target *target)
return retval;
else {
int fd = target_buffer_get_u32(target, params+0);
- off_t cur = lseek(fd, 0, SEEK_CUR);
- if (cur == (off_t)-1) {
- armv4_5->semihosting_errno = errno;
+ struct stat buf;
+ result = fstat(fd, &buf);
+ if (result == -1) {
+ info->semihosting_errno = errno;
result = -1;
break;
}
- result = lseek(fd, 0, SEEK_END);
- armv4_5->semihosting_errno = errno;
- if (lseek(fd, cur, SEEK_SET) == (off_t)-1) {
- armv4_5->semihosting_errno = errno;
- result = -1;
- }
+ result = buf.st_size;
}
break;
@@ -259,10 +253,10 @@ static int do_semihosting(struct target *target)
return retval;
fn[l] = 0;
result = remove((char *)fn);
- armv4_5->semihosting_errno = errno;
+ info->semihosting_errno = errno;
} else {
result = -1;
- armv4_5->semihosting_errno = EINVAL;
+ info->semihosting_errno = EINVAL;
}
}
break;
@@ -287,10 +281,10 @@ static int do_semihosting(struct target *target)
fn1[l1] = 0;
fn2[l2] = 0;
result = rename((char *)fn1, (char *)fn2);
- armv4_5->semihosting_errno = errno;
+ info->semihosting_errno = errno;
} else {
result = -1;
- armv4_5->semihosting_errno = EINVAL;
+ info->semihosting_errno = EINVAL;
}
}
break;
@@ -300,7 +294,7 @@ static int do_semihosting(struct target *target)
break;
case 0x13: /* SYS_ERRNO */
- result = armv4_5->semihosting_errno;
+ result = info->semihosting_errno;
break;
case 0x15: /* SYS_GET_CMDLINE */
@@ -376,27 +370,12 @@ static int do_semihosting(struct target *target)
fprintf(stderr, "semihosting: unsupported call %#x\n",
(unsigned) r0);
result = -1;
- armv4_5->semihosting_errno = ENOTSUP;
+ info->semihosting_errno = ENOTSUP;
}
- /* resume execution to the original mode */
-
- /* return value in R0 */
- buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, result);
- armv4_5->core_cache->reg_list[0].dirty = 1;
-
- /* LR --> PC */
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, lr);
- armv4_5->core_cache->reg_list[15].dirty = 1;
-
- /* saved PSR --> current PSR */
- buf_set_u32(armv4_5->cpsr->value, 0, 32, spsr);
- armv4_5->cpsr->dirty = 1;
- armv4_5->core_mode = spsr & 0x1f;
- if (spsr & 0x20)
- armv4_5->core_state = ARM_STATE_THUMB;
+ info->result = result;
- return target_resume(target, 1, 0, 0, 0);
+ return ERROR_OK;
}
/**
@@ -412,13 +391,13 @@ static int do_semihosting(struct target *target)
* @param retval Pointer to a location where the return code will be stored
* @return non-zero value if a request was processed or an error encountered
*/
-int arm_semihosting(struct target *target, int *retval)
+int armv4_5_semihosting(struct target *target, int *retval)
{
struct arm *arm = target_to_arm(target);
uint32_t pc, lr, spsr;
struct reg *r;
- if (!arm->is_semihosting || arm->core_mode != ARM_MODE_SVC)
+ if (!arm->semi_hosting_info.is_semihosting || arm->core_mode != ARM_MODE_SVC)
return 0;
/* Check for PC == 0x00000008 or 0xffff0008: Supervisor Call vector. */
@@ -473,6 +452,75 @@ int arm_semihosting(struct target *target, int *retval)
return 0;
}
- *retval = do_semihosting(target);
+ lr = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache, ARM_MODE_SVC, 14).value, 0, 32);
+ spsr = buf_get_u32(arm->spsr->value, 0, 32);
+
+ arm->semi_hosting_info.core_cache = arm->core_cache;
+
+ if ((*retval = do_semihosting(target, &arm->semi_hosting_info)) != ERROR_OK)
+ return 0;
+
+ /* resume execution to the original mode */
+
+ /* return value in R0 */
+ buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, arm->semi_hosting_info.result);
+ arm->core_cache->reg_list[0].dirty = 1;
+
+ /* LR --> PC */
+ buf_set_u32(arm->core_cache->reg_list[15].value, 0, 32, lr);
+ arm->core_cache->reg_list[15].dirty = 1;
+
+ /* saved PSR --> current PSR */
+ buf_set_u32(arm->cpsr->value, 0, 32, spsr);
+ arm->cpsr->dirty = 1;
+ arm->core_mode = spsr & 0x1f;
+ if (spsr & 0x20)
+ arm->core_state = ARM_STATE_THUMB;
+
+ *retval = target_resume(target, 1, 0, 0, 0);
+
+ return 1;
+}
+
+int armv7m_semihosting(struct target *target, int *retval)
+{
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct armv7m_common *armv7m = &cortex_m3->armv7m;
+ uint32_t pc;
+ struct reg *r;
+ uint16_t insn;
+
+ if (!armv7m->semi_hosting_info.is_semihosting)
+ return 0;
+
+ if (target->debug_reason != DBG_REASON_BREAKPOINT)
+ return 0;
+
+ r = &armv7m->core_cache->reg_list[ARMV7M_PC];
+ pc = buf_get_u32(r->value, 0, 32);
+
+ pc &= ~1;
+ *retval = target_read_u16(target, pc, &insn);
+ if (*retval != ERROR_OK)
+ return 1;
+
+ /* bkpt 0xAB */
+ if (insn != 0xBEAB)
+ return 0;
+
+ armv7m->semi_hosting_info.core_cache = armv7m->core_cache;
+
+ if ((*retval = do_semihosting(target, &armv7m->semi_hosting_info)) != ERROR_OK)
+ return 0;
+
+ /* resume execution, this will be pc+2 to skip over the
+ * bkpt instruction */
+
+ /* return result in R0 */
+ buf_set_u32(armv7m->core_cache->reg_list[0].value, 0, 32, armv7m->semi_hosting_info.result);
+ armv7m->core_cache->reg_list[0].dirty = 1;
+
+ *retval = target_resume(target, 1, 0, 0, 0);
+
return 1;
}
diff --git a/src/target/arm_semihosting.h b/src/target/arm_semihosting.h
index 80cad39..a2d4e0c 100644
--- a/src/target/arm_semihosting.h
+++ b/src/target/arm_semihosting.h
@@ -21,6 +21,21 @@
#ifndef ARM_SEMIHOSTING_H
#define ARM_SEMIHOSTING_H
-int arm_semihosting(struct target *target, int *retval);
+struct arm_semi_hosting {
+
+ /** Flag reporting whether semihosting is active. */
+ bool is_semihosting;
+
+ /** Value to be returned by semihosting SYS_ERRNO request. */
+ int semihosting_errno;
+
+ /** Value holding semi hosting result. */
+ int result;
+
+ struct reg_cache *core_cache;
+};
+
+int armv4_5_semihosting(struct target *target, int *retval);
+int armv7m_semihosting(struct target *target, int *retval);
#endif
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index c7b7367..1dcfe88 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -600,7 +600,7 @@ int arm_arch_state(struct target *target)
buf_get_u32(armv4_5->cpsr->value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value,
0, 32),
- armv4_5->is_semihosting ? ", semihosting" : "");
+ armv4_5->semi_hosting_info.is_semihosting ? ", semihosting" : "");
return ERROR_OK;
}
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index c172a27..7650c14 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -473,20 +473,20 @@ int armv7m_run_algorithm(struct target *target,
int armv7m_arch_state(struct target *target)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
- uint32_t ctrl, sp;
+ uint32_t ctrl;
ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
- sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
LOG_USER("target halted due to %s, current mode: %s %s\n"
- "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32,
+ "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s",
debug_reason_name(target),
armv7m_mode_strings[armv7m->core_mode],
armv7m_exception_string(armv7m->exception_number),
buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_PC].value, 0, 32),
(ctrl & 0x02) ? 'p' : 'm',
- sp);
+ buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32),
+ armv7m->semi_hosting_info.is_semihosting ? ", semihosting" : "");
return ERROR_OK;
}
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 9787e30..d470507 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -105,6 +105,7 @@ struct armv7m_common
enum armv7m_mode core_mode;
int exception_number;
struct swjdp_common swjdp_info;
+ struct arm_semi_hosting semi_hosting_info;
uint32_t demcr;
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index adce4d9..0230824 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -38,7 +38,7 @@
#include "arm_disassembler.h"
#include "register.h"
#include "arm_opcodes.h"
-
+#include "arm_semihosting.h"
/* NOTE: most of this should work fine for the Cortex-M1 and
* Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
@@ -449,6 +449,9 @@ static int cortex_m3_poll(struct target *target)
if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
return retval;
+ if (armv7m_semihosting(target, &retval) != 0)
+ return retval;
+
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
}
if (prev_target_state == TARGET_DEBUG_RUNNING)
@@ -2010,6 +2013,38 @@ COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
return ERROR_OK;
}
+COMMAND_HANDLER(handle_cortex_m3_semihosting_command)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ int retval;
+
+ retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (CMD_ARGC > 0)
+ {
+ int semihosting;
+
+ COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
+
+ if (!target_was_examined(target))
+ {
+ LOG_ERROR("Target not examined yet");
+ return ERROR_FAIL;
+ }
+
+ cortex_m3->armv7m.semi_hosting_info.is_semihosting = semihosting;
+ }
+
+ command_print(CMD_CTX, "semihosting is %s",
+ cortex_m3->armv7m.semi_hosting_info.is_semihosting
+ ? "enabled" : "disabled");
+
+ return ERROR_OK;
+}
+
static const struct command_registration cortex_m3_exec_command_handlers[] = {
{
.name = "disassemble",
@@ -2032,6 +2067,13 @@ static const struct command_registration cortex_m3_exec_command_handlers[] = {
.help = "configure hardware vectors to trigger debug entry",
.usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
},
+ {
+ .name = "semihosting",
+ .handler = handle_cortex_m3_semihosting_command,
+ .mode = COMMAND_EXEC,
+ .help = "activate support for semihosting operations",
+ .usage = "['enable'|'disable']",
+ },
COMMAND_REGISTRATION_DONE
};
static const struct command_registration cortex_m3_command_handlers[] = {
diff --git a/src/target/target.h b/src/target/target.h
index da91d46..0131575 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -36,7 +36,6 @@ struct watchpoint;
struct mem_param;
struct reg_param;
-
/*
* TARGET_UNKNOWN = 0: we don't know anything about the target yet
* TARGET_RUNNING = 1: the target is executing user code
--
1.6.5.1.1367.gcd48
--------------010708040704050309040302--
|
