From: <mar...@us...> - 2008-06-02 17:07:15
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Revision: 587 http://openamt.svn.sourceforge.net/openamt/?rev=587&view=rev Author: marcin_obara Date: 2008-06-02 10:07:24 -0700 (Mon, 02 Jun 2008) Log Message: ----------- add comments to heci registers defines Modified Paths: -------------- heci/trunk/src/heci_data_structures.h Modified: heci/trunk/src/heci_data_structures.h =================================================================== --- heci/trunk/src/heci_data_structures.h 2008-06-02 17:05:58 UTC (rev 586) +++ heci/trunk/src/heci_data_structures.h 2008-06-02 17:07:24 UTC (rev 587) @@ -76,32 +76,53 @@ * HECI HW Section */ -/* HECI addresses and defines */ +/* HECI registers */ +/* H_CB_WW - Host Circular Buffer (CB) Write Window register */ #define H_CB_WW 0 +/* H_CSR - Host Control Status register */ #define H_CSR 4 +/* ME_CB_RW - ME Circular Buffer Read Window register (read only) */ #define ME_CB_RW 8 +/* ME_CSR_HA - ME Control Status Host Access register (read only) */ #define ME_CSR_HA 0xC -/* register bits - H_CSR */ +/* register bits of H_CSR (Host Control Status register) */ +/* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */ #define H_CBD 0xFF000000 +/* Host Circular Buffer Write Pointer */ #define H_CBWP 0x00FF0000 +/* Host Circular Buffer Read Pointer */ #define H_CBRP 0x0000FF00 +/* Host Reset */ #define H_RST 0x00000010 +/* Host Ready */ #define H_RDY 0x00000008 +/* Host Interrupt Generate */ #define H_IG 0x00000004 +/* Host Interrupt Status */ #define H_IS 0x00000002 +/* Host Interrupt Enable */ #define H_IE 0x00000001 -/* register bits - ME_CSR_HA */ +/* register bits of ME_CSR_HA (ME Control Status Host Access register) */ +/* ME CB (Circular Buffer) Depth HRA (Host Read Access) + * - host read only access to ME_CBD */ #define ME_CBD_HRA 0xFF000000 +/* ME CB Write Pointer HRA - host read only access to ME_CBWP */ #define ME_CBWP_HRA 0x00FF0000 +/* ME CB Read Pointer HRA - host read only access to ME_CBRP */ #define ME_CBRP_HRA 0x0000FF00 +/* ME Reset HRA - host read only access to ME_RST */ #define ME_RST_HRA 0x00000010 +/* ME Ready HRA - host read only access to ME_RDY */ #define ME_RDY_HRA 0x00000008 +/* ME Interrupt Generate HRA - host read only access to ME_IG */ #define ME_IG_HRA 0x00000004 +/* ME Interrupt Status HRA - host read only access to ME_IS */ #define ME_IS_HRA 0x00000002 +/* ME Interrupt Enable HRA - host read only access to ME_IE */ #define ME_IE_HRA 0x00000001 #define HECI_MINORS_BASE 1 This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site. |