#21 Improve code generation backend


Implement instruction re-ordering by modifying

After having allocated registers for the current
instruction, determine if all used values of the
subsequent instructions are in registers at this point. If
a value is not in a register and if registers are available,
generate a restore operation for this register before
issueing the principal instruction to be emitted by


  • Hans-Martin Will

    • status: open --> open-later
  • Hans-Martin Will

    • assigned_to: hmwill --> nobody
  • Hans-Martin Will

    • summary: Instruction re-ordering --> Improve code generation backend
    • status: open-later --> pending-accepted
  • Hans-Martin Will

    Logged In: YES

    Ideas on how to improve JIT:

    - Register targeting:

    Mainly for function calls: If next use of a register is for
    a function call, calcualte value
    directly into target register.

    Issue: Can this lead to premature and unnecessary stores?

    - Increase cache performance:

    Allocate actual storage offsets for registers only after we
    have identified, which different
    values actually need to be persisted.

    - Read only parameters are copy onto stack:

    Alternatives: Move all parameters onto stack, so we can use
    direct frame pointer access
    Or: Convert function to a method, and have a second pointer
    (this->ptr) available for
    direct adressing of parameter values.
    Or: Implement reference variables (could lead to cascaded
    load instructions in inner loops)

    - Remove stalls in execution pipeline:

    Register loads: Have cg_codegen_emit_simple_inst look for
    register values that need to/could be
    preloaded for following instruction. If those exist, and
    registers are available, emit
    pre-load instruction before actual instruction to be
    scheduled at this point. This will
    ensure that data will be available (given it resides in
    on-chip cache).

    Multiplications: Rewrite fixed point multiplies as
    instructions that can be scheduled individually

    Have general instruction scheduling on intermediate code:
    Assuming all data is available, just take instuction
    execution cycles and next use into


    - Texture coordinate to texel mapping:

    Can clamping to 0..1 become its own IR instruction (no
    blocks, no branches)?

    - Multiple formats for alpha, stencil & depth buffer?

    0, 8-bit alpha buffer
    0, 8, 16, 32-bit stencil buffer
    16 & 32-bit depth buffer

    Also needs corresponding entries in EGL configurations

  • Hans-Martin Will

    • assigned_to: nobody --> hmwill
    • status: pending-accepted --> open-accepted
  • Hans-Martin Will

    • status: open-accepted --> closed-accepted

Get latest updates about Open Source Projects, Conferences and News.

Sign up for the SourceForge newsletter:

No, thanks