Love this verilog plugin for Notepad++. However, I have noticed a couple things that it doesn't seem to handle correctly.
1) When a module is "copied" (CTRL+SHFT+C), if the width specification of a port contains spaces (e.g., "input [ 3:0] a"), subsequent module instantiations are incorrect. I use this plugin often with auto-generated code that makes generous use of spaces to format the code more uniformly.
2) When a module is "copied", if the port is specified as "signed" (e.g., "input signed [31:0] x"), subsequent module instantiations are incorrect.
Also, as a feature request, it would be awesome (if it's possible), to be able to compare a module's port definition with an instantiation of that module in another file. This would help when the interface changes for a module that you've instantiated with lots of ports.