I have the digital model which take the input as clock signal and reset signal.
I came across the in built model called d_osc which generate the digital clock signal,but I cant find the example on it.
I am trying to use it in this way,but its not working
.tran 1e-5 1e-3
v1 1 0 1.0 pulse( 0 1 1e−4 1e−6)
r1 1 0 1k
a5 1 8 var_clock
.model var_clock d_osc(cntl_array = [-2 -1 1 2]
+ freq_array = [1e3 1e3 10e3 10e3]
+ duty_cycle = 0.4 init_phase = 180.0
+ rise_delay = 10e-9 fall_delay=8e-9)
Can you please share the example on how to use d_osc?
d_osc is a voltage controlled oscillator.
Make the input voltage a ramp between -1 and 1, its output frequency will vary between 1k and 10k.
As an example please see the nspiace pll example at
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