I am trying to implement NgSpice netlist in which I am converting sinusoidal into digital form using adc and after some processing signal I want to convert the digital signal in sinusoidal form to give feedback to my input signal.
But the problem is when I am using dac to convert digital into analog I am getting only square wave only.
My question is how can I sample the sinusoidal signal in NgSpice and using dac how can I get the signal in sinusoidal form again.
Any initiative help is appreciated
have a look at
I am trying to implement sigma-delta modulator with below netlist. For time being I am not considering counter.
Please find the netlist below.
****Integrator using VCVS
.tran 1e-6 1.5e-3
vin in 0 SIN(0 1 10k)
Vreset areset 0 PWL(0ms 0.0 0.1ms 0.0 0.15ms 2.0 1.5ms 2.0)
Vset aset 0 PWL(0ms 0.0 0.1ms 0.0 0.15ms 2.0 1.5ms 2.0)
Vclk aclk 0 PULSE(0 1 0ms 0ms 0ms 0.05ms 0.1ms)
ro in vi1 10K
co vi1 vo1 1nF
r1 vi1 vo1 100k
*E1 vo1 0 vi1 0 1e6
E1 0 vo1 0 vi1 300e6
adc1 [aclk] [dclk] adc
adc2 [areset] [dreset] adc
adc3 [aset] [dset] adc
aadc [vo1] [dout] adc
adff dout dclk dset dreset qout nqout dff
adac [qout] [aout] dac
*E2 in aout vi1 0 1
a1 %v[in aout] vi1 sum
.model dff d_dff(clk_delay = 13.0e-9 set_delay = 25.0e-9 reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9
.model adc adc_bridge ( in_low =0.0 in_high =1.0 rise_delay =1.0e-10 fall_delay =1.0e-10)
.model dac dac_bridge(out_low = -5.0 out_high = 5.0 out_undef = 1.0
+ input_load = 5.0e-14 t_rise = 1.0e-10
+ t_fall = 1.0e-10)
.model sum summer(out_gain = 1)
I just want to get sinusoidal output at dac and to give as feedback to my input.
Can you just enlighten me how can I reconstruct sinosoidal output.?
What changes should I made with ADC and DAC?
I am using voltage controlled voltage source to implement integrator as
E1 0 vo1 0 vi1 300e6
Is it correct way to use?
unfortunately I have no time resources to support your design work.
Of course I am open to questions concerning ngspice use.
Can you let me know what should I use for adding two signal like if I want to add input signal with -ve feedback signal.
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