#227 Cannot simulate saturation

analyses (40)

I'm trying to simulate a common source amplifier with a VDD of 1.2 V and biased with an independent current source. I expect the output waveform to rail out at 1.2 V, but the simulations show full swing.

Is this a problem with ngspice or my netlist?

The netlist can be found below or at https://gist.github.com/4370307
The plot of the transient response can be found at http://i.imgur.com/QWGkj.png

NETLIST: Circuit D

* NOTE: Plot of transient response is in http://i.imgur.com/QWGkj.png
* The output response is supposed to rail out at 1.2 V

* PTM model from http://ptm.asu.edu/modelcard/2006/65nm_bulk.pm
.include 65nm_bulk.pm

VD vdd 0 dc 1.2 ac pwl(0 1.2 100 1.2)
M1 drain gate 0 0 nmos w=3.00771369299e-06 l=9.5e-08
V1 gate 0 dc 0 ac sin(0.3833 0.0196 1 0 0)
ID vdd drain 3.76991118431e-05
CL drain 0 1e-13

save @m1[vgs]
save @m1[vds]
save @m1[id]
save gate
save drain
save vdd
tran 1m 2.0
wrdata circuitd_95n @m1[vgs] @m1[vds] @m1[id] gate drain vdd



  • Kit

    Kit - 2012-12-24

    Transient response waveform

  • marcel hendrix

    marcel hendrix - 2012-12-24

    If you put an ideal voltage source of 1 Volt, an ideal current source of 1uA, and a resistor of 100 Ohms in series, what is then the voltage across the resistor :-)


  • Kit

    Kit - 2012-12-25

    @mhx_at_sf Thanks, I tested it. It's 0.1mV across the resistor. What does this mean? That ideal current sources take precedence over voltage sources?

  • Holger Vogt

    Holger Vogt - 2013-01-21
    • assigned_to: nobody --> h_vogt
    • status: open --> closed-rejected
  • Holger Vogt

    Holger Vogt - 2013-01-21

    basic ee question.

    No ngspice bug involved



Log in to post a comment.

Get latest updates about Open Source Projects, Conferences and News.

Sign up for the SourceForge newsletter:

No, thanks