I'm trying to simulate a common source amplifier with a VDD of 1.2 V and biased with an independent current source. I expect the output waveform to rail out at 1.2 V, but the simulations show full swing.
Is this a problem with ngspice or my netlist?
NETLIST: Circuit D
* NOTE: Plot of transient response is in http://i.imgur.com/QWGkj.png
* The output response is supposed to rail out at 1.2 V
* PTM model from http://ptm.asu.edu/modelcard/2006/65nm_bulk.pm
VD vdd 0 dc 1.2 ac pwl(0 1.2 100 1.2)
M1 drain gate 0 0 nmos w=3.00771369299e-06 l=9.5e-08
V1 gate 0 dc 0 ac sin(0.3833 0.0196 1 0 0)
ID vdd drain 3.76991118431e-05
CL drain 0 1e-13
tran 1m 2.0
wrdata circuitd_95n @m1[vgs] @m1[vds] @m1[id] gate drain vdd
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