Addition of VHDL, Verilog and SystemVerilog iis appreciated.
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#174 Addition of VHDL, Verilog and SystemVerilog iis appreciated.
open
nobody
None
5
2012-09-14
2009-08-14
Anonymous
No
Language: VHDL
Extensions: vhd vhdl
Line Comment: --
Block Comment:
Package Separator: .
Enum Values: Global
Class Prototype Ender: ;
Function Prototype Ender: ;
Variable Prototype Ender: ;
Line Extender:
Language: Verilog
Extensions: v vh inc
Line Comment: //
Block Comment: / /
Package Separator: ::
Enum Values: Global
Class Prototype Ender: ;
Function Prototype Ender: ;
Variable Prototype Ender: ;
Line Extender: \
Language: SystemVerilog
Extensions: sv svh
Line Comment: //
Block Comment: / /
Package Separator: ::
Enum Values: Global
Class Prototype Ender: ;
Function Prototype Ender: ;
Variable Prototype Ender: ;
Line Extender: \
-- Amal
