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From: Jin K. S. <jin...@in...> - 2013-09-13 21:14:07
|
Added AVX-512CD / ER / PF instructions and corresponding test cases. This time IF_AVX512 has been changed to a bit mask because this needs to be shared by all AVX-512 family. Jin Kyu Song (3): AVX-512: Add AVX-512CD instructions AVX-512: Add AVX-512ER instructions AVX-512: Added AVX-512PF instructions assemble.c | 2 +- insns.dat | 39 +++++++++++++++ insns.h | 5 +- test/avx512cd.asm | 105 +++++++++++++++++++++++++++++++++++++++ test/avx512er.asm | 143 +++++++++++++++++++++++++++++++++++++++++++++++++++++ test/avx512pf.asm | 87 ++++++++++++++++++++++++++++++++ 6 files changed, 379 insertions(+), 2 deletions(-) create mode 100644 test/avx512cd.asm create mode 100644 test/avx512er.asm create mode 100644 test/avx512pf.asm -- 1.7.9.5 |
|
From: Cyrill G. <gor...@gm...> - 2013-09-07 07:51:25
|
On Sat, Sep 07, 2013 at 07:44:56AM +0000, Song, Jin Kyu wrote: > Hi Cyrill, > > Could you apply the previous patch set? > ([Nasm-devel] [PATCH 0/2] Fix EVEX.RC with SAE) > There were two more patches in between. > > ---------------------- > AVX-512: Fix rounding mode value in EVEX prefix with SAE > AVX-512: Reorder instructions in insns.dat > ---------------------- Ouch, I managed to miss them. Everything applied and pushed out, thanks! |
|
From: Song, J. K. <jin...@in...> - 2013-09-07 07:45:31
|
Hi Cyrill, Could you apply the previous patch set? ([Nasm-devel] [PATCH 0/2] Fix EVEX.RC with SAE) There were two more patches in between. ---------------------- AVX-512: Fix rounding mode value in EVEX prefix with SAE AVX-512: Reorder instructions in insns.dat ---------------------- Thanks, Jin > -----Original Message----- > From: Cyrill Gorcunov [mailto:gor...@gm...] > Sent: Friday, September 06, 2013 10:59 PM > To: Song, Jin Kyu > Cc: nas...@li... > Subject: Re: [Nasm-devel] [PATCH] Added pseudo-ops for CMP > > On Fri, Sep 06, 2013 at 09:22:17PM -0700, Jin Kyu Song wrote: > > By adding these instructions, the complete set of AVX-512F instructions > > are now supported. > > Hi Jin, > > [cyrill@moon nasm.git]$ git am -s ~/mutt-patches/foo.patch > Applying: AVX-512: Add Pseudo-ops for CMP instructions > error: patch failed: insns.dat:3478 > error: insns.dat: patch does not apply > Patch failed at 0001 AVX-512: Add Pseudo-ops for CMP instructions > The copy of the patch that failed is found in: > /home/cyrill/projects/nasm.git/.git/rebase-apply/patch > > could you please refresh your repo? The last commit I'm trying > to fetch patch into is > > commit 088827bc6c8590108e5d752fd1f968d128b5586e > Author: Jin Kyu Song <jin...@in...> > Date: Wed Aug 28 19:15:29 2013 -0700 > > AVX-512: Add test case for opmask instructions |
|
From: Cyrill G. <gor...@gm...> - 2013-09-07 05:58:50
|
On Fri, Sep 06, 2013 at 09:22:17PM -0700, Jin Kyu Song wrote:
> By adding these instructions, the complete set of AVX-512F instructions
> are now supported.
Hi Jin,
[cyrill@moon nasm.git]$ git am -s ~/mutt-patches/foo.patch
Applying: AVX-512: Add Pseudo-ops for CMP instructions
error: patch failed: insns.dat:3478
error: insns.dat: patch does not apply
Patch failed at 0001 AVX-512: Add Pseudo-ops for CMP instructions
The copy of the patch that failed is found in:
/home/cyrill/projects/nasm.git/.git/rebase-apply/patch
could you please refresh your repo? The last commit I'm trying
to fetch patch into is
commit 088827bc6c8590108e5d752fd1f968d128b5586e
Author: Jin Kyu Song <jin...@in...>
Date: Wed Aug 28 19:15:29 2013 -0700
AVX-512: Add test case for opmask instructions
|
|
From: Jin K. S. <jin...@in...> - 2013-09-07 04:24:02
|
Added three-operand pseudo-ops for VCMPPD, VPCMPD and so on.
Test case is also updated to validate them.
Signed-off-by: Jin Kyu Song <jin...@in...>
---
insns.dat | 150 ++++
test/avx512f.asm | 2378 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
test/gas2nasm.py | 8 +-
3 files changed, 2531 insertions(+), 5 deletions(-)
diff --git a/insns.dat b/insns.dat
index 3c9b1ca..ad72d61 100644
--- a/insns.dat
+++ b/insns.dat
@@ -3478,9 +3478,137 @@ VBROADCASTSD zmmreg|mask|z,mem64 [rm:t1s:
VBROADCASTSD zmmreg|mask|z,xmmreg [rm: evex.512.66.0f38.w1 19 /r ] AVX512,FUTURE
VBROADCASTSS zmmreg|mask|z,xmmreg [rm: evex.512.66.0f38.w0 18 /r ] AVX512,FUTURE
VBROADCASTSS zmmreg|mask|z,mem32 [rm:t1s: evex.512.66.0f38.w0 18 /r ] AVX512,FUTURE
+VCMPEQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 00 ] AVX512,FUTURE
+VCMPLTPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 01 ] AVX512,FUTURE
+VCMPLEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 02 ] AVX512,FUTURE
+VCMPUNORDPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 03 ] AVX512,FUTURE
+VCMPNEQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 04 ] AVX512,FUTURE
+VCMPNLTPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 05 ] AVX512,FUTURE
+VCMPNLEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 06 ] AVX512,FUTURE
+VCMPORDPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 07 ] AVX512,FUTURE
+VCMPEQ_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 08 ] AVX512,FUTURE
+VCMPNGEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 09 ] AVX512,FUTURE
+VCMPNGTPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 0a ] AVX512,FUTURE
+VCMPFALSEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 0b ] AVX512,FUTURE
+VCMPNEQ_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 0c ] AVX512,FUTURE
+VCMPGEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 0d ] AVX512,FUTURE
+VCMPGTPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 0e ] AVX512,FUTURE
+VCMPTRUEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 0f ] AVX512,FUTURE
+VCMPEQ_OSPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 10 ] AVX512,FUTURE
+VCMPLT_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 11 ] AVX512,FUTURE
+VCMPLE_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 12 ] AVX512,FUTURE
+VCMPUNORD_SPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 13 ] AVX512,FUTURE
+VCMPNEQ_USPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 14 ] AVX512,FUTURE
+VCMPNLT_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 15 ] AVX512,FUTURE
+VCMPNLE_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 16 ] AVX512,FUTURE
+VCMPORD_SPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 17 ] AVX512,FUTURE
+VCMPEQ_USPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 18 ] AVX512,FUTURE
+VCMPNGE_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 19 ] AVX512,FUTURE
+VCMPNGT_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 1a ] AVX512,FUTURE
+VCMPFALSE_OSPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 1b ] AVX512,FUTURE
+VCMPNEQ_OSPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 1c ] AVX512,FUTURE
+VCMPGE_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 1d ] AVX512,FUTURE
+VCMPGT_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 1e ] AVX512,FUTURE
+VCMPTRUE_USPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 1f ] AVX512,FUTURE
VCMPPD kreg|mask,zmmreg,zmmrm512|b64|sae,imm8 [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r ib ] AVX512,FUTURE
+VCMPEQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 00 ] AVX512,FUTURE
+VCMPLTPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 01 ] AVX512,FUTURE
+VCMPLEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 02 ] AVX512,FUTURE
+VCMPUNORDPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 03 ] AVX512,FUTURE
+VCMPNEQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 04 ] AVX512,FUTURE
+VCMPNLTPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 05 ] AVX512,FUTURE
+VCMPNLEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 06 ] AVX512,FUTURE
+VCMPORDPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 07 ] AVX512,FUTURE
+VCMPEQ_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 08 ] AVX512,FUTURE
+VCMPNGEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 09 ] AVX512,FUTURE
+VCMPNGTPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 0a ] AVX512,FUTURE
+VCMPFALSEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 0b ] AVX512,FUTURE
+VCMPNEQ_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 0c ] AVX512,FUTURE
+VCMPGEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 0d ] AVX512,FUTURE
+VCMPGTPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 0e ] AVX512,FUTURE
+VCMPTRUEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 0f ] AVX512,FUTURE
+VCMPEQ_OSPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 10 ] AVX512,FUTURE
+VCMPLT_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 11 ] AVX512,FUTURE
+VCMPLE_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 12 ] AVX512,FUTURE
+VCMPUNORD_SPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 13 ] AVX512,FUTURE
+VCMPNEQ_USPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 14 ] AVX512,FUTURE
+VCMPNLT_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 15 ] AVX512,FUTURE
+VCMPNLE_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 16 ] AVX512,FUTURE
+VCMPORD_SPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 17 ] AVX512,FUTURE
+VCMPEQ_USPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 18 ] AVX512,FUTURE
+VCMPNGE_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 19 ] AVX512,FUTURE
+VCMPNGT_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 1a ] AVX512,FUTURE
+VCMPFALSE_OSPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 1b ] AVX512,FUTURE
+VCMPNEQ_OSPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 1c ] AVX512,FUTURE
+VCMPGE_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 1d ] AVX512,FUTURE
+VCMPGT_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 1e ] AVX512,FUTURE
+VCMPTRUE_USPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 1f ] AVX512,FUTURE
VCMPPS kreg|mask,zmmreg,zmmrm512|b32|sae,imm8 [rvmi:fv: evex.nds.512.0f.w0 c2 /r ib ] AVX512,FUTURE
+VCMPEQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 00 ] AVX512,FUTURE
+VCMPLTSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 01 ] AVX512,FUTURE
+VCMPLESD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 02 ] AVX512,FUTURE
+VCMPUNORDSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 03 ] AVX512,FUTURE
+VCMPNEQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 04 ] AVX512,FUTURE
+VCMPNLTSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 05 ] AVX512,FUTURE
+VCMPNLESD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 06 ] AVX512,FUTURE
+VCMPORDSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 07 ] AVX512,FUTURE
+VCMPEQ_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 08 ] AVX512,FUTURE
+VCMPNGESD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 09 ] AVX512,FUTURE
+VCMPNGTSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0a ] AVX512,FUTURE
+VCMPFALSESD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0b ] AVX512,FUTURE
+VCMPNEQ_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0c ] AVX512,FUTURE
+VCMPGESD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0d ] AVX512,FUTURE
+VCMPGTSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0e ] AVX512,FUTURE
+VCMPTRUESD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0f ] AVX512,FUTURE
+VCMPEQ_OSSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 10 ] AVX512,FUTURE
+VCMPLT_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 11 ] AVX512,FUTURE
+VCMPLE_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 12 ] AVX512,FUTURE
+VCMPUNORD_SSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 13 ] AVX512,FUTURE
+VCMPNEQ_USSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 14 ] AVX512,FUTURE
+VCMPNLT_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 15 ] AVX512,FUTURE
+VCMPNLE_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 16 ] AVX512,FUTURE
+VCMPORD_SSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 17 ] AVX512,FUTURE
+VCMPEQ_USSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 18 ] AVX512,FUTURE
+VCMPNGE_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 19 ] AVX512,FUTURE
+VCMPNGT_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 1a ] AVX512,FUTURE
+VCMPFALSE_OSSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 1b ] AVX512,FUTURE
+VCMPNEQ_OSSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 1c ] AVX512,FUTURE
+VCMPGE_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 1d ] AVX512,FUTURE
+VCMPGT_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 1e ] AVX512,FUTURE
+VCMPTRUE_USSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 1f ] AVX512,FUTURE
VCMPSD kreg|mask,xmmreg,xmmrm64|sae,imm8 [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r ib ] AVX512,FUTURE
+VCMPEQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 00 ] AVX512,FUTURE
+VCMPLTSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 01 ] AVX512,FUTURE
+VCMPLESS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 02 ] AVX512,FUTURE
+VCMPUNORDSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 03 ] AVX512,FUTURE
+VCMPNEQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 04 ] AVX512,FUTURE
+VCMPNLTSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 05 ] AVX512,FUTURE
+VCMPNLESS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 06 ] AVX512,FUTURE
+VCMPORDSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 07 ] AVX512,FUTURE
+VCMPEQ_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 08 ] AVX512,FUTURE
+VCMPNGESS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 09 ] AVX512,FUTURE
+VCMPNGTSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0a ] AVX512,FUTURE
+VCMPFALSESS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0b ] AVX512,FUTURE
+VCMPNEQ_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0c ] AVX512,FUTURE
+VCMPGESS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0d ] AVX512,FUTURE
+VCMPGTSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0e ] AVX512,FUTURE
+VCMPTRUESS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0f ] AVX512,FUTURE
+VCMPEQ_OSSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 10 ] AVX512,FUTURE
+VCMPLT_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 11 ] AVX512,FUTURE
+VCMPLE_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 12 ] AVX512,FUTURE
+VCMPUNORD_SSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 13 ] AVX512,FUTURE
+VCMPNEQ_USSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 14 ] AVX512,FUTURE
+VCMPNLT_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 15 ] AVX512,FUTURE
+VCMPNLE_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 16 ] AVX512,FUTURE
+VCMPORD_SSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 17 ] AVX512,FUTURE
+VCMPEQ_USSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 18 ] AVX512,FUTURE
+VCMPNGE_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 19 ] AVX512,FUTURE
+VCMPNGT_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 1a ] AVX512,FUTURE
+VCMPFALSE_OSSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 1b ] AVX512,FUTURE
+VCMPNEQ_OSSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 1c ] AVX512,FUTURE
+VCMPGE_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 1d ] AVX512,FUTURE
+VCMPGT_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 1e ] AVX512,FUTURE
+VCMPTRUE_USSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 1f ] AVX512,FUTURE
VCMPSS kreg|mask,xmmreg,xmmrm32|sae,imm8 [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r ib ] AVX512,FUTURE
VCOMISD xmmreg,xmmrm64|sae [rm:t1s: evex.lig.66.0f.w1 2f /r ] AVX512,FUTURE
VCOMISS xmmreg,xmmrm32|sae [rm:t1s: evex.lig.0f.w0 2f /r ] AVX512,FUTURE
@@ -3713,13 +3841,35 @@ VPBROADCASTD zmmreg|mask|z,reg32 [rm:
VPBROADCASTQ zmmreg|mask|z,xmmreg [rm: evex.512.66.0f38.w1 59 /r ] AVX512,FUTURE
VPBROADCASTQ zmmreg|mask|z,mem64 [rm:t1s: evex.512.66.0f38.w1 59 /r ] AVX512,FUTURE
VPBROADCASTQ zmmreg|mask|z,reg64 [rm: evex.512.66.0f38.w1 7c /r ] AVX512,FUTURE
+VPCMPLTD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1f /r 01 ] AVX512,FUTURE
+VPCMPLED kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1f /r 02 ] AVX512,FUTURE
+VPCMPNEQD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1f /r 04 ] AVX512,FUTURE
+VPCMPNLTD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1f /r 05 ] AVX512,FUTURE
+VPCMPNLED kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1f /r 06 ] AVX512,FUTURE
VPCMPD kreg|mask,zmmreg,zmmrm512|b32,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 1f /r ib ] AVX512,FUTURE
VPCMPEQD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 76 /r ] AVX512,FUTURE
VPCMPEQQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 29 /r ] AVX512,FUTURE
VPCMPGTD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 66 /r ] AVX512,FUTURE
VPCMPGTQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 37 /r ] AVX512,FUTURE
+VPCMPLTQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1f /r 01 ] AVX512,FUTURE
+VPCMPLEQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1f /r 02 ] AVX512,FUTURE
+VPCMPNEQQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1f /r 04 ] AVX512,FUTURE
+VPCMPNLTQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1f /r 05 ] AVX512,FUTURE
+VPCMPNLEQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1f /r 06 ] AVX512,FUTURE
VPCMPQ kreg|mask,zmmreg,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 1f /r ib ] AVX512,FUTURE
+VPCMPEQUD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1e /r 00 ] AVX512,FUTURE
+VPCMPLTUD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1e /r 01 ] AVX512,FUTURE
+VPCMPLEUD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1e /r 02 ] AVX512,FUTURE
+VPCMPNEQUD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1e /r 04 ] AVX512,FUTURE
+VPCMPNLTUD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1e /r 05 ] AVX512,FUTURE
+VPCMPNLEUD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1e /r 06 ] AVX512,FUTURE
VPCMPUD kreg|mask,zmmreg,zmmrm512|b32,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 1e /r ib ] AVX512,FUTURE
+VPCMPEQUQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1e /r 00 ] AVX512,FUTURE
+VPCMPLTUQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1e /r 01 ] AVX512,FUTURE
+VPCMPLEUQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1e /r 02 ] AVX512,FUTURE
+VPCMPNEQUQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1e /r 04 ] AVX512,FUTURE
+VPCMPNLTUQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1e /r 05 ] AVX512,FUTURE
+VPCMPNLEUQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1e /r 06 ] AVX512,FUTURE
VPCMPUQ kreg|mask,zmmreg,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 1e /r ib ] AVX512,FUTURE
VPCOMPRESSD zmmreg|mask|z,zmmreg [mr: evex.512.66.0f38.w0 8b /r ] AVX512,FUTURE
VPCOMPRESSD mem512|mask,zmmreg [mr:t1s: evex.512.66.0f38.w0 8b /r ] AVX512,FUTURE
diff --git a/test/avx512f.asm b/test/avx512f.asm
index 3dcae37..282dbea 100644
--- a/test/avx512f.asm
+++ b/test/avx512f.asm
@@ -190,6 +190,650 @@ testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x7b
testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x7b }, { vcmppd k5,zmm30,QWORD [rdx+0x400]\{1to8\},0x7b }
testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x7b }, { vcmppd k5,zmm30,QWORD [rdx-0x400]\{1to8\},0x7b }
testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x7b }, { vcmppd k5,zmm30,QWORD [rdx-0x408]\{1to8\},0x7b }
+testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x00 }, { vcmpeqpd k5,zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x00 }, { vcmpeqpd k5\{k7\},zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x00 }, { vcmpeqpd k5,zmm30,zmm29,\{sae\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rcx] }
+testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rax+r14*8+0x123] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x00 }, { vcmpeqpd k5,zmm30,QWORD [rcx]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rdx+0x1fc0] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rdx+0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rdx-0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rdx-0x2040] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x00 }, { vcmpeqpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x00 }, { vcmpeqpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x00 }, { vcmpeqpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x00 }, { vcmpeqpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} }
+testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x00 }, { vcmpeqpd k5,zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x00 }, { vcmpeqpd k5\{k7\},zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x00 }, { vcmpeqpd k5,zmm30,zmm29,\{sae\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rcx] }
+testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rax+r14*8+0x123] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x00 }, { vcmpeqpd k5,zmm30,QWORD [rcx]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rdx+0x1fc0] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rdx+0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rdx-0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rdx-0x2040] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x00 }, { vcmpeqpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x00 }, { vcmpeqpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x00 }, { vcmpeqpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x00 }, { vcmpeqpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} }
+testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x01 }, { vcmpltpd k5,zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x01 }, { vcmpltpd k5\{k7\},zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x01 }, { vcmpltpd k5,zmm30,zmm29,\{sae\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rcx] }
+testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rax+r14*8+0x123] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x01 }, { vcmpltpd k5,zmm30,QWORD [rcx]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rdx+0x1fc0] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rdx+0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rdx-0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rdx-0x2040] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x01 }, { vcmpltpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x01 }, { vcmpltpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x01 }, { vcmpltpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x01 }, { vcmpltpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} }
+testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x01 }, { vcmpltpd k5,zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x01 }, { vcmpltpd k5\{k7\},zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x01 }, { vcmpltpd k5,zmm30,zmm29,\{sae\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rcx] }
+testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rax+r14*8+0x123] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x01 }, { vcmpltpd k5,zmm30,QWORD [rcx]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rdx+0x1fc0] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rdx+0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rdx-0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rdx-0x2040] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x01 }, { vcmpltpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x01 }, { vcmpltpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x01 }, { vcmpltpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x01 }, { vcmpltpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} }
+testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x02 }, { vcmplepd k5,zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x02 }, { vcmplepd k5\{k7\},zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x02 }, { vcmplepd k5,zmm30,zmm29,\{sae\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rcx] }
+testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rax+r14*8+0x123] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x02 }, { vcmplepd k5,zmm30,QWORD [rcx]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rdx+0x1fc0] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rdx+0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rdx-0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rdx-0x2040] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x02 }, { vcmplepd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x02 }, { vcmplepd k5,zmm30,QWORD [rdx+0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x02 }, { vcmplepd k5,zmm30,QWORD [rdx-0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x02 }, { vcmplepd k5,zmm30,QWORD [rdx-0x408]\{1to8\} }
+testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x02 }, { vcmplepd k5,zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x02 }, { vcmplepd k5\{k7\},zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x02 }, { vcmplepd k5,zmm30,zmm29,\{sae\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rcx] }
+testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rax+r14*8+0x123] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x02 }, { vcmplepd k5,zmm30,QWORD [rcx]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rdx+0x1fc0] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rdx+0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rdx-0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rdx-0x2040] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x02 }, { vcmplepd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x02 }, { vcmplepd k5,zmm30,QWORD [rdx+0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x02 }, { vcmplepd k5,zmm30,QWORD [rdx-0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x02 }, { vcmplepd k5,zmm30,QWORD [rdx-0x408]\{1to8\} }
+testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x03 }, { vcmpunordpd k5,zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x03 }, { vcmpunordpd k5\{k7\},zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x03 }, { vcmpunordpd k5,zmm30,zmm29,\{sae\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rcx] }
+testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rax+r14*8+0x123] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x03 }, { vcmpunordpd k5,zmm30,QWORD [rcx]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rdx+0x1fc0] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rdx+0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rdx-0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rdx-0x2040] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x03 }, { vcmpunordpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x03 }, { vcmpunordpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x03 }, { vcmpunordpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x03 }, { vcmpunordpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} }
+testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x03 }, { vcmpunordpd k5,zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x03 }, { vcmpunordpd k5\{k7\},zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x03 }, { vcmpunordpd k5,zmm30,zmm29,\{sae\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rcx] }
+testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rax+r14*8+0x123] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x03 }, { vcmpunordpd k5,zmm30,QWORD [rcx]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rdx+0x1fc0] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rdx+0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rdx-0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rdx-0x2040] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x03 }, { vcmpunordpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x03 }, { vcmpunordpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x03 }, { vcmpunordpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x03 }, { vcmpunordpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} }
+testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x04 }, { vcmpneqpd k5,zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x04 }, { vcmpneqpd k5\{k7\},zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x04 }, { vcmpneqpd k5,zmm30,zmm29,\{sae\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rcx] }
+testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rax+r14*8+0x123] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x04 }, { vcmpneqpd k5,zmm30,QWORD [rcx]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rdx+0x1fc0] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rdx+0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rdx-0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rdx-0x2040] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x04 }, { vcmpneqpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x04 }, { vcmpneqpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x04 }, { vcmpneqpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x04 }, { vcmpneqpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} }
+testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x04 }, { vcmpneqpd k5,zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x04 }, { vcmpneqpd k5\{k7\},zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x04 }, { vcmpneqpd k5,zmm30,zmm29,\{sae\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rcx] }
+testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rax+r14*8+0x123] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x04 }, { vcmpneqpd k5,zmm30,QWORD [rcx]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rdx+0x1fc0] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rdx+0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rdx-0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rdx-0x2040] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x04 }, { vcmpneqpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x04 }, { vcmpneqpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x04 }, { vcmpneqpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x04 }, { vcmpneqpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} }
+testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x05 }, { vcmpnltpd k5,zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x05 }, { vcmpnltpd k5\{k7\},zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x05 }, { vcmpnltpd k5,zmm30,zmm29,\{sae\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rcx] }
+testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rax+r14*8+0x123] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x05 }, { vcmpnltpd k5,zmm30,QWORD [rcx]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rdx+0x1fc0] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rdx+0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rdx-0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rdx-0x2040] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x05 }, { vcmpnltpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x05 }, { vcmpnltpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x05 }, { vcmpnltpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x05 }, { vcmpnltpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} }
+testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x05 }, { vcmpnltpd k5,zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x05 }, { vcmpnltpd k5\{k7\},zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x05 }, { vcmpnltpd k5,zmm30,zmm29,\{sae\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rcx] }
+testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rax+r14*8+0x123] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x05 }, { vcmpnltpd k5,zmm30,QWORD [rcx]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rdx+0x1fc0] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rdx+0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rdx-0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rdx-0x2040] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x05 }, { vcmpnltpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x05 }, { vcmpnltpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x05 }, { vcmpnltpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x05 }, { vcmpnltpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} }
+testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x06 }, { vcmpnlepd k5,zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x06 }, { vcmpnlepd k5\{k7\},zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x06 }, { vcmpnlepd k5,zmm30,zmm29,\{sae\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rcx] }
+testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rax+r14*8+0x123] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x06 }, { vcmpnlepd k5,zmm30,QWORD [rcx]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rdx+0x1fc0] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rdx+0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rdx-0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rdx-0x2040] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x06 }, { vcmpnlepd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x06 }, { vcmpnlepd k5,zmm30,QWORD [rdx+0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x06 }, { vcmpnlepd k5,zmm30,QWORD [rdx-0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x06 }, { vcmpnlepd k5,zmm30,QWORD [rdx-0x408]\{1to8\} }
+testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x06 }, { vcmpnlepd k5,zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x06 }, { vcmpnlepd k5\{k7\},zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x06 }, { vcmpnlepd k5,zmm30,zmm29,\{sae\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rcx] }
+testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rax+r14*8+0x123] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x06 }, { vcmpnlepd k5,zmm30,QWORD [rcx]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rdx+0x1fc0] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rdx+0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rdx-0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rdx-0x2040] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x06 }, { vcmpnlepd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x06 }, { vcmpnlepd k5,zmm30,QWORD [rdx+0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x06 }, { vcmpnlepd k5,zmm30,QWORD [rdx-0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x06 }, { vcmpnlepd k5,zmm30,QWORD [rdx-0x408]\{1to8\} }
+testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x07 }, { vcmpordpd k5,zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x07 }, { vcmpordpd k5\{k7\},zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x07 }, { vcmpordpd k5,zmm30,zmm29,\{sae\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rcx] }
+testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rax+r14*8+0x123] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x07 }, { vcmpordpd k5,zmm30,QWORD [rcx]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rdx+0x1fc0] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rdx+0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rdx-0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rdx-0x2040] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x07 }, { vcmpordpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x07 }, { vcmpordpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x07 }, { vcmpordpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x07 }, { vcmpordpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} }
+testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x07 }, { vcmpordpd k5,zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x07 }, { vcmpordpd k5\{k7\},zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x07 }, { vcmpordpd k5,zmm30,zmm29,\{sae\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rcx] }
+testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rax+r14*8+0x123] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x07 }, { vcmpordpd k5,zmm30,QWORD [rcx]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rdx+0x1fc0] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rdx+0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rdx-0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rdx-0x2040] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x07 }, { vcmpordpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x07 }, { vcmpordpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x07 }, { vcmpordpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x07 }, { vcmpordpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} }
+testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x08 }, { vcmpeq_uqpd k5,zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x08 }, { vcmpeq_uqpd k5\{k7\},zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x08 }, { vcmpeq_uqpd k5,zmm30,zmm29,\{sae\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x08 }, { vcmpeq_uqpd k5,zmm30,ZWORD [rcx] }
+testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x08 }, { vcmpeq_uqpd k5,zmm30,ZWORD [rax+r14*8+0x123] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x08 }, { vcmpeq_uqpd k5,zmm30,QWORD [rcx]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x08 }, { vcmpeq_uqpd k5,zmm30,ZWORD [rdx+0x1fc0] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x08 }, { vcmpeq_uqpd k5,zmm30,ZWORD [rdx+0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x08 }, { vcmpeq_uqpd k5,zmm30,ZWORD [rdx-0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x08 }, { vcmpeq_uqpd k5,zmm30,ZWORD [rdx-0x2040] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x08 }, { vcmpeq_uqpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x08 }, { vcmpeq_uqpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x08 }, { vcmpeq_uqpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x08 }, { vcmpeq_uqpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} }
+testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x09 }, { vcmpngepd k5,zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x09 }, { vcmpngepd k5\{k7\},zmm30,zmm29 }
+testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x09 }, { vcmpngepd k5,zmm30,zmm29,\{sae\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x09 }, { vcmpngepd k5,zmm30,ZWORD [rcx] }
+testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x09 }, { vcmpngepd k5,zmm30,ZWORD [rax+r14*8+0x123] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x09 }, { vcmpngepd k5,zmm30,QWORD [rcx]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x09 }, { vcmpngepd k5,zmm30,ZWORD [rdx+0x1fc0] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x09 }, { vcmpngepd k5,zmm30,ZWORD [rdx+0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x09 }, { vcmpngepd k5,zmm30,ZWORD [rdx-0x2000] }
+testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x09 }, { vcmpngepd k5,zmm30,ZWORD [rdx-0x2040] }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x09 }, { vcmpngepd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} }
+testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x09 }, { vcmpngepd k5,zmm30,QWORD [rdx+0x400]\{1to8\} }
...
[truncated message content] |
|
From: Jin K. S. <jin...@in...> - 2013-09-07 04:23:45
|
By adding these instructions, the complete set of AVX-512F instructions are now supported. Jin Kyu Song (1): AVX-512: Add Pseudo-ops for CMP instructions insns.dat | 150 ++++ test/avx512f.asm | 2378 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ test/gas2nasm.py | 8 +- 3 files changed, 2531 insertions(+), 5 deletions(-) -- 1.7.9.5 |
|
From: Jin K. S. <jin...@in...> - 2013-08-31 01:11:41
|
Within a same instruction mnemonic, instructions are reordered in order of opcode byte value. Therefore when there are two possible opcode candidates, smaller opcode is picked now. e.g.) vmovapd zmm30, zmm29 -> now 28h is used. 29h previously Signed-off-by: Jin Kyu Song <jin...@in...> --- insns.dat | 114 ++++++++++++++++++++++++++++++------------------------------- 1 file changed, 57 insertions(+), 57 deletions(-) diff --git a/insns.dat b/insns.dat index cfb2d71..3c9b1ca 100644 --- a/insns.dat +++ b/insns.dat @@ -3458,7 +3458,7 @@ TZMSK reg64,rm64 [vm: xop.ndd.lz.m9.w1 01 /4] LONG,FUTURE,TBM T1MSKC reg32,rm32 [vm: xop.ndd.lz.m9.w0 01 /7] FUTURE,TBM T1MSKC reg64,rm64 [vm: xop.ndd.lz.m9.w1 01 /7] LONG,FUTURE,TBM -;# Intel AVX512 instructions +;# Intel AVX-512 instructions ; ; based on pub number 319433-015 dated July 2013 ; @@ -3476,8 +3476,8 @@ VBROADCASTI32X4 zmmreg|mask|z,mem128 [rm:t4: VBROADCASTI64X4 zmmreg|mask|z,mem256 [rm:t4: evex.512.66.0f38.w1 5b /r ] AVX512,FUTURE VBROADCASTSD zmmreg|mask|z,mem64 [rm:t1s: evex.512.66.0f38.w1 19 /r ] AVX512,FUTURE VBROADCASTSD zmmreg|mask|z,xmmreg [rm: evex.512.66.0f38.w1 19 /r ] AVX512,FUTURE -VBROADCASTSS zmmreg|mask|z,mem32 [rm:t1s: evex.512.66.0f38.w0 18 /r ] AVX512,FUTURE VBROADCASTSS zmmreg|mask|z,xmmreg [rm: evex.512.66.0f38.w0 18 /r ] AVX512,FUTURE +VBROADCASTSS zmmreg|mask|z,mem32 [rm:t1s: evex.512.66.0f38.w0 18 /r ] AVX512,FUTURE VCMPPD kreg|mask,zmmreg,zmmrm512|b64|sae,imm8 [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r ib ] AVX512,FUTURE VCMPPS kreg|mask,zmmreg,zmmrm512|b32|sae,imm8 [rvmi:fv: evex.nds.512.0f.w0 c2 /r ib ] AVX512,FUTURE VCMPSD kreg|mask,xmmreg,xmmrm64|sae,imm8 [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r ib ] AVX512,FUTURE @@ -3496,16 +3496,16 @@ VCVTPD2UDQ ymmreg|mask|z,zmmrm512|b64|er [rm:fv: VCVTPH2PS zmmreg|mask|z,ymmrm256|sae [rm:hvm: evex.512.66.0f38.w0 13 /r ] AVX512,FUTURE VCVTPS2DQ zmmreg|mask|z,zmmrm512|b32|er [rm:fv: evex.512.66.0f.w0 5b /r ] AVX512,FUTURE VCVTPS2PD zmmreg|mask|z,ymmrm256|b32|sae [rm:hv: evex.512.0f.w0 5a /r ] AVX512,FUTURE -VCVTPS2PH mem256|mask,zmmreg|sae,imm8 [mri:hvm: evex.512.66.0f3a.w0 1d /r ib ] AVX512,FUTURE VCVTPS2PH ymmreg|mask|z,zmmreg|sae,imm8 [mri:hvm: evex.512.66.0f3a.w0 1d /r ib ] AVX512,FUTURE +VCVTPS2PH mem256|mask,zmmreg|sae,imm8 [mri:hvm: evex.512.66.0f3a.w0 1d /r ib ] AVX512,FUTURE VCVTPS2UDQ zmmreg|mask|z,zmmrm512|b32|er [rm:fv: evex.512.0f.w0 79 /r ] AVX512,FUTURE -VCVTSD2SI reg32,xmmrm64|er [rm:t1f64: evex.lig.f2.0f.w0 2d /r ] AVX512,FUTURE VCVTSD2SI reg64,xmmrm64|er [rm:t1f64: evex.lig.f2.0f.w1 2d /r ] AVX512,FUTURE +VCVTSD2SI reg32,xmmrm64|er [rm:t1f64: evex.lig.f2.0f.w0 2d /r ] AVX512,FUTURE VCVTSD2SS xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s: evex.nds.lig.f2.0f.w1 5a /r ] AVX512,FUTURE -VCVTSD2USI reg32,xmmrm64|er [rm:t1f64: evex.lig.f2.0f.w0 79 /r ] AVX512,FUTURE VCVTSD2USI reg64,xmmrm64|er [rm:t1f64: evex.lig.f2.0f.w1 79 /r ] AVX512,FUTURE -VCVTSI2SD xmmreg,xmmreg|er,rm32 [rvm:t1s: evex.nds.lig.f2.0f.w0 2a /r ] AVX512,FUTURE +VCVTSD2USI reg32,xmmrm64|er [rm:t1f64: evex.lig.f2.0f.w0 79 /r ] AVX512,FUTURE VCVTSI2SD xmmreg,xmmreg|er,rm64 [rvm:t1s: evex.nds.lig.f2.0f.w1 2a /r ] AVX512,FUTURE +VCVTSI2SD xmmreg,xmmreg|er,rm32 [rvm:t1s: evex.nds.lig.f2.0f.w0 2a /r ] AVX512,FUTURE VCVTSI2SS xmmreg,xmmreg|er,rm32 [rvm:t1s: evex.nds.lig.f3.0f.w0 2a /r ] AVX512,FUTURE VCVTSI2SS xmmreg,xmmreg|er,rm64 [rvm:t1s: evex.nds.lig.f3.0f.w1 2a /r ] AVX512,FUTURE VCVTSS2SD xmmreg|mask|z,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 5a /r ] AVX512,FUTURE @@ -3517,20 +3517,20 @@ VCVTTPD2DQ ymmreg|mask|z,zmmrm512|b64|sae [rm:fv: VCVTTPD2UDQ ymmreg|mask|z,zmmrm512|b64|sae [rm:fv: evex.512.0f.w1 78 /r ] AVX512,FUTURE VCVTTPS2DQ zmmreg|mask|z,zmmrm512|b32|sae [rm:fv: evex.512.f3.0f.w0 5b /r ] AVX512,FUTURE VCVTTPS2UDQ zmmreg|mask|z,zmmrm512|b32|sae [rm:fv: evex.512.0f.w0 78 /r ] AVX512,FUTURE -VCVTTSD2SI reg32,xmmrm64|sae [rm:t1f64: evex.lig.f2.0f.w0 2c /r ] AVX512,FUTURE VCVTTSD2SI reg64,xmmrm64|sae [rm:t1f64: evex.lig.f2.0f.w1 2c /r ] AVX512,FUTURE +VCVTTSD2SI reg32,xmmrm64|sae [rm:t1f64: evex.lig.f2.0f.w0 2c /r ] AVX512,FUTURE VCVTTSD2USI reg32,xmmrm64|sae [rm:t1f64: evex.lig.f2.0f.w0 78 /r ] AVX512,FUTURE VCVTTSD2USI reg64,xmmrm64|sae [rm:t1f64: evex.lig.f2.0f.w1 78 /r ] AVX512,FUTURE -VCVTTSS2SI reg32,xmmrm32|sae [rm:t1f32: evex.lig.f3.0f.w0 2c /r ] AVX512,FUTURE VCVTTSS2SI reg64,xmmrm32|sae [rm:t1f32: evex.lig.f3.0f.w1 2c /r ] AVX512,FUTURE +VCVTTSS2SI reg32,xmmrm32|sae [rm:t1f32: evex.lig.f3.0f.w0 2c /r ] AVX512,FUTURE VCVTTSS2USI reg32,xmmrm32|sae [rm:t1f32: evex.lig.f3.0f.w0 78 /r ] AVX512,FUTURE VCVTTSS2USI reg64,xmmrm32|sae [rm:t1f32: evex.lig.f3.0f.w1 78 /r ] AVX512,FUTURE VCVTUDQ2PD zmmreg|mask|z,ymmrm256|b32|er [rm:hv: evex.512.f3.0f.w0 7a /r ] AVX512,FUTURE VCVTUDQ2PS zmmreg|mask|z,zmmrm512|b32|er [rm:fv: evex.512.f2.0f.w0 7a /r ] AVX512,FUTURE VCVTUSI2SD xmmreg,xmmreg|er,rm32 [rvm:t1s: evex.nds.lig.f2.0f.w0 7b /r ] AVX512,FUTURE VCVTUSI2SD xmmreg,xmmreg|er,rm64 [rvm:t1s: evex.nds.lig.f2.0f.w1 7b /r ] AVX512,FUTURE -VCVTUSI2SS xmmreg,xmmreg|er,rm32 [rvm:t1s: evex.nds.lig.f3.0f.w0 7b /r ] AVX512,FUTURE VCVTUSI2SS xmmreg,xmmreg|er,rm64 [rvm:t1s: evex.nds.lig.f3.0f.w1 7b /r ] AVX512,FUTURE +VCVTUSI2SS xmmreg,xmmreg|er,rm32 [rvm:t1s: evex.nds.lig.f3.0f.w0 7b /r ] AVX512,FUTURE VDIVPD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f.w1 5e /r ] AVX512,FUTURE VDIVPS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv: evex.nds.512.0f.w0 5e /r ] AVX512,FUTURE VDIVSD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s: evex.nds.lig.f2.0f.w1 5e /r ] AVX512,FUTURE @@ -3545,8 +3545,8 @@ VEXTRACTF64X4 mem256|mask,zmmreg,imm8 [mri:t4: e VEXTRACTF64X4 ymmreg|mask|z,zmmreg,imm8 [mri: evex.512.66.0f3a.w1 1b /r ib ] AVX512,FUTURE VEXTRACTI32X4 mem128|mask,zmmreg,imm8 [mri:t4: evex.512.66.0f3a.w0 39 /r ib ] AVX512,FUTURE VEXTRACTI32X4 xmmreg|mask|z,zmmreg,imm8 [mri: evex.512.66.0f3a.w0 39 /r ib ] AVX512,FUTURE -VEXTRACTI64X4 mem256|mask,zmmreg,imm8 [mri:t4: evex.512.66.0f3a.w1 3b /r ib ] AVX512,FUTURE VEXTRACTI64X4 ymmreg|mask|z,zmmreg,imm8 [mri: evex.512.66.0f3a.w1 3b /r ib ] AVX512,FUTURE +VEXTRACTI64X4 mem256|mask,zmmreg,imm8 [mri:t4: evex.512.66.0f3a.w1 3b /r ib ] AVX512,FUTURE VEXTRACTPS rm32,xmmreg,imm8 [mri:t1s: evex.128.66.0f3a.wig 17 /r ib ] AVX512,FUTURE VEXTRACTPS rm64,xmmreg,imm8 [mri:t1s: evex.128.66.0f3a.w1 17 /r ib ] AVX512,FUTURE VFIXUPIMMPD zmmreg|mask|z,zmmreg,zmmrm512|b64|sae,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 54 /r ib ] AVX512,FUTURE @@ -3638,61 +3638,61 @@ VMINPD zmmreg|mask|z,zmmreg,zmmrm512|b64|sae [rvm:fv: VMINPS zmmreg|mask|z,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 5d /r ] AVX512,FUTURE VMINSD xmmreg|mask|z,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 5d /r ] AVX512,FUTURE VMINSS xmmreg|mask|z,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 5d /r ] AVX512,FUTURE +VMOVAPD zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.66.0f.w1 28 /r ] AVX512,FUTURE VMOVAPD mem512|mask,zmmreg [mr:fvm: evex.512.66.0f.w1 29 /r ] AVX512,FUTURE VMOVAPD zmmreg|mask|z,zmmreg [mr: evex.512.66.0f.w1 29 /r ] AVX512,FUTURE -VMOVAPD zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.66.0f.w1 28 /r ] AVX512,FUTURE -VMOVAPS mem512|mask,zmmreg [mr:fvm: evex.512.0f.w0 29 /r ] AVX512,FUTURE -VMOVAPS zmmreg|mask|z,zmmreg [mr: evex.512.0f.w0 29 /r ] AVX512,FUTURE VMOVAPS zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.0f.w0 28 /r ] AVX512,FUTURE -VMOVD rm32,xmmreg [mr:t1s: evex.128.66.0f.w0 7e /r ] AVX512,FUTURE +VMOVAPS zmmreg|mask|z,zmmreg [mr: evex.512.0f.w0 29 /r ] AVX512,FUTURE +VMOVAPS mem512|mask,zmmreg [mr:fvm: evex.512.0f.w0 29 /r ] AVX512,FUTURE VMOVD xmmreg,rm32 [rm:t1s: evex.128.66.0f.w0 6e /r ] AVX512,FUTURE +VMOVD rm32,xmmreg [mr:t1s: evex.128.66.0f.w0 7e /r ] AVX512,FUTURE VMOVDDUP zmmreg|mask|z,zmmrm512 [rm:dup: evex.512.f2.0f.w1 12 /r ] AVX512,FUTURE +VMOVDQA32 zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.66.0f.w0 6f /r ] AVX512,FUTURE VMOVDQA32 mem512|mask,zmmreg [mr:fvm: evex.512.66.0f.w0 7f /r ] AVX512,FUTURE VMOVDQA32 zmmreg|mask|z,zmmreg [mr: evex.512.66.0f.w0 7f /r ] AVX512,FUTURE -VMOVDQA32 zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.66.0f.w0 6f /r ] AVX512,FUTURE -VMOVDQA64 mem512|mask,zmmreg [mr:fvm: evex.512.66.0f.w1 7f /r ] AVX512,FUTURE -VMOVDQA64 zmmreg|mask|z,zmmreg [mr: evex.512.66.0f.w1 7f /r ] AVX512,FUTURE VMOVDQA64 zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.66.0f.w1 6f /r ] AVX512,FUTURE +VMOVDQA64 zmmreg|mask|z,zmmreg [mr: evex.512.66.0f.w1 7f /r ] AVX512,FUTURE +VMOVDQA64 mem512|mask,zmmreg [mr:fvm: evex.512.66.0f.w1 7f /r ] AVX512,FUTURE +VMOVDQU32 zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.f3.0f.w0 6f /r ] AVX512,FUTURE VMOVDQU32 mem512|mask,zmmreg [mr:fvm: evex.512.f3.0f.w0 7f /r ] AVX512,FUTURE VMOVDQU32 zmmreg|mask|z,zmmreg [mr: evex.512.f3.0f.w0 7f /r ] AVX512,FUTURE -VMOVDQU32 zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.f3.0f.w0 6f /r ] AVX512,FUTURE +VMOVDQU64 zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.f3.0f.w1 6f /r ] AVX512,FUTURE VMOVDQU64 mem512|mask,zmmreg [mr:fvm: evex.512.f3.0f.w1 7f /r ] AVX512,FUTURE VMOVDQU64 zmmreg|mask|z,zmmreg [mr: evex.512.f3.0f.w1 7f /r ] AVX512,FUTURE -VMOVDQU64 zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.f3.0f.w1 6f /r ] AVX512,FUTURE VMOVHLPS xmmreg,xmmreg,xmmreg [rvm: evex.nds.128.0f.w0 12 /r ] AVX512,FUTURE -VMOVHPD mem64,xmmreg [mr:t1s: evex.128.66.0f.w1 17 /r ] AVX512,FUTURE VMOVHPD xmmreg,xmmreg,mem64 [rvm:t1s: evex.nds.128.66.0f.w1 16 /r ] AVX512,FUTURE -VMOVHPS mem64,xmmreg [mr:t2: evex.128.0f.w0 17 /r ] AVX512,FUTURE +VMOVHPD mem64,xmmreg [mr:t1s: evex.128.66.0f.w1 17 /r ] AVX512,FUTURE VMOVHPS xmmreg,xmmreg,mem64 [rvm:t2: evex.nds.128.0f.w0 16 /r ] AVX512,FUTURE +VMOVHPS mem64,xmmreg [mr:t2: evex.128.0f.w0 17 /r ] AVX512,FUTURE VMOVLHPS xmmreg,xmmreg,xmmreg [rvm: evex.nds.128.0f.w0 16 /r ] AVX512,FUTURE -VMOVLPD mem64,xmmreg [mr:t1s: evex.128.66.0f.w1 13 /r ] AVX512,FUTURE VMOVLPD xmmreg,xmmreg,mem64 [rvm:t1s: evex.nds.128.66.0f.w1 12 /r ] AVX512,FUTURE -VMOVLPS mem64,xmmreg [mr:t2: evex.128.0f.w0 13 /r ] AVX512,FUTURE +VMOVLPD mem64,xmmreg [mr:t1s: evex.128.66.0f.w1 13 /r ] AVX512,FUTURE VMOVLPS xmmreg,xmmreg,mem64 [rvm:t2: evex.nds.128.0f.w0 12 /r ] AVX512,FUTURE +VMOVLPS mem64,xmmreg [mr:t2: evex.128.0f.w0 13 /r ] AVX512,FUTURE VMOVNTDQ mem512,zmmreg [mr:fvm: evex.512.66.0f.w0 e7 /r ] AVX512,FUTURE VMOVNTDQA zmmreg,mem512 [rm:fvm: evex.512.66.0f38.w0 2a /r ] AVX512,FUTURE VMOVNTPD mem512,zmmreg [mr:fvm: evex.512.66.0f.w1 2b /r ] AVX512,FUTURE VMOVNTPS mem512,zmmreg [mr:fvm: evex.512.0f.w0 2b /r ] AVX512,FUTURE -VMOVQ rm64,xmmreg [mr:t1s: evex.128.66.0f.w1 7e /r ] AVX512,FUTURE VMOVQ xmmreg,rm64 [rm:t1s: evex.128.66.0f.w1 6e /r ] AVX512,FUTURE +VMOVQ rm64,xmmreg [mr:t1s: evex.128.66.0f.w1 7e /r ] AVX512,FUTURE VMOVQ xmmreg,xmmrm64 [rm:t1s: evex.128.f3.0f.w1 7e /r ] AVX512,FUTURE VMOVQ xmmrm64,xmmreg [mr:t1s: evex.128.66.0f.w1 d6 /r ] AVX512,FUTURE -VMOVSD mem64|mask,xmmreg [mr:t1s: evex.lig.f2.0f.w1 11 /r ] AVX512,FUTURE +VMOVSD xmmreg|mask|z,xmmreg,xmmreg [rvm: evex.nds.lig.f2.0f.w1 10 /r ] AVX512,FUTURE VMOVSD xmmreg|mask|z,mem64 [rm:t1s: evex.lig.f2.0f.w1 10 /r ] AVX512,FUTURE +VMOVSD mem64|mask,xmmreg [mr:t1s: evex.lig.f2.0f.w1 11 /r ] AVX512,FUTURE VMOVSD xmmreg|mask|z,xmmreg,xmmreg [mvr: evex.nds.lig.f2.0f.w1 11 /r ] AVX512,FUTURE -VMOVSD xmmreg|mask|z,xmmreg,xmmreg [rvm: evex.nds.lig.f2.0f.w1 10 /r ] AVX512,FUTURE VMOVSHDUP zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.f3.0f.w0 16 /r ] AVX512,FUTURE VMOVSLDUP zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.f3.0f.w0 12 /r ] AVX512,FUTURE -VMOVSS mem32|mask,xmmreg [mr:t1s: evex.lig.f3.0f.w0 11 /r ] AVX512,FUTURE VMOVSS xmmreg|mask|z,mem32 [rm:t1s: evex.lig.f3.0f.w0 10 /r ] AVX512,FUTURE -VMOVSS xmmreg|mask|z,xmmreg,xmmreg [mvr: evex.nds.lig.f3.0f.w0 11 /r ] AVX512,FUTURE VMOVSS xmmreg|mask|z,xmmreg,xmmreg [rvm: evex.nds.lig.f3.0f.w0 10 /r ] AVX512,FUTURE +VMOVSS mem32|mask,xmmreg [mr:t1s: evex.lig.f3.0f.w0 11 /r ] AVX512,FUTURE +VMOVSS xmmreg|mask|z,xmmreg,xmmreg [mvr: evex.nds.lig.f3.0f.w0 11 /r ] AVX512,FUTURE +VMOVUPD zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.66.0f.w1 10 /r ] AVX512,FUTURE VMOVUPD mem512|mask,zmmreg [mr:fvm: evex.512.66.0f.w1 11 /r ] AVX512,FUTURE VMOVUPD zmmreg|mask|z,zmmreg [mr: evex.512.66.0f.w1 11 /r ] AVX512,FUTURE -VMOVUPD zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.66.0f.w1 10 /r ] AVX512,FUTURE -VMOVUPS mem512|mask,zmmreg [mr:fvm: evex.512.0f.w0 11 /r ] AVX512,FUTURE -VMOVUPS zmmreg|mask|z,zmmreg [mr: evex.512.0f.w0 11 /r ] AVX512,FUTURE VMOVUPS zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.0f.w0 10 /r ] AVX512,FUTURE +VMOVUPS zmmreg|mask|z,zmmreg [mr: evex.512.0f.w0 11 /r ] AVX512,FUTURE +VMOVUPS mem512|mask,zmmreg [mr:fvm: evex.512.0f.w0 11 /r ] AVX512,FUTURE VMULPD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f.w1 59 /r ] AVX512,FUTURE VMULPS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv: evex.nds.512.0f.w0 59 /r ] AVX512,FUTURE VMULSD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s: evex.nds.lig.f2.0f.w1 59 /r ] AVX512,FUTURE @@ -3707,12 +3707,12 @@ VPANDNQ zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: VPANDQ zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f.w1 db /r ] AVX512,FUTURE VPBLENDMD zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 64 /r ] AVX512,FUTURE VPBLENDMQ zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 64 /r ] AVX512,FUTURE +VPBROADCASTD zmmreg|mask|z,xmmreg [rm: evex.512.66.0f38.w0 58 /r ] AVX512,FUTURE VPBROADCASTD zmmreg|mask|z,mem32 [rm:t1s: evex.512.66.0f38.w0 58 /r ] AVX512,FUTURE VPBROADCASTD zmmreg|mask|z,reg32 [rm: evex.512.66.0f38.w0 7c /r ] AVX512,FUTURE -VPBROADCASTD zmmreg|mask|z,xmmreg [rm: evex.512.66.0f38.w0 58 /r ] AVX512,FUTURE +VPBROADCASTQ zmmreg|mask|z,xmmreg [rm: evex.512.66.0f38.w1 59 /r ] AVX512,FUTURE VPBROADCASTQ zmmreg|mask|z,mem64 [rm:t1s: evex.512.66.0f38.w1 59 /r ] AVX512,FUTURE VPBROADCASTQ zmmreg|mask|z,reg64 [rm: evex.512.66.0f38.w1 7c /r ] AVX512,FUTURE -VPBROADCASTQ zmmreg|mask|z,xmmreg [rm: evex.512.66.0f38.w1 59 /r ] AVX512,FUTURE VPCMPD kreg|mask,zmmreg,zmmrm512|b32,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 1f /r ib ] AVX512,FUTURE VPCMPEQD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 76 /r ] AVX512,FUTURE VPCMPEQQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 29 /r ] AVX512,FUTURE @@ -3721,30 +3721,30 @@ VPCMPGTQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: ev VPCMPQ kreg|mask,zmmreg,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 1f /r ib ] AVX512,FUTURE VPCMPUD kreg|mask,zmmreg,zmmrm512|b32,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 1e /r ib ] AVX512,FUTURE VPCMPUQ kreg|mask,zmmreg,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 1e /r ib ] AVX512,FUTURE -VPCOMPRESSD mem512|mask,zmmreg [mr:t1s: evex.512.66.0f38.w0 8b /r ] AVX512,FUTURE VPCOMPRESSD zmmreg|mask|z,zmmreg [mr: evex.512.66.0f38.w0 8b /r ] AVX512,FUTURE -VPCOMPRESSQ mem512|mask,zmmreg [mr:t1s: evex.512.66.0f38.w1 8b /r ] AVX512,FUTURE +VPCOMPRESSD mem512|mask,zmmreg [mr:t1s: evex.512.66.0f38.w0 8b /r ] AVX512,FUTURE VPCOMPRESSQ zmmreg|mask|z,zmmreg [mr: evex.512.66.0f38.w1 8b /r ] AVX512,FUTURE +VPCOMPRESSQ mem512|mask,zmmreg [mr:t1s: evex.512.66.0f38.w1 8b /r ] AVX512,FUTURE VPERMD zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 36 /r ] AVX512,FUTURE VPERMI2D zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 76 /r ] AVX512,FUTURE VPERMI2PD zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 77 /r ] AVX512,FUTURE VPERMI2PS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 77 /r ] AVX512,FUTURE VPERMI2Q zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 76 /r ] AVX512,FUTURE -VPERMILPD zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 0d /r ] AVX512,FUTURE VPERMILPD zmmreg|mask|z,zmmrm512|b64,imm8 [rmi:fv: evex.512.66.0f3a.w1 05 /r ib ] AVX512,FUTURE -VPERMILPS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 0c /r ] AVX512,FUTURE +VPERMILPD zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 0d /r ] AVX512,FUTURE VPERMILPS zmmreg|mask|z,zmmrm512|b32,imm8 [rmi:fv: evex.512.66.0f3a.w0 04 /r ib ] AVX512,FUTURE -VPERMPD zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 16 /r ] AVX512,FUTURE +VPERMILPS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 0c /r ] AVX512,FUTURE VPERMPD zmmreg|mask|z,zmmrm512|b64,imm8 [rmi:fv: evex.512.66.0f3a.w1 01 /r ib ] AVX512,FUTURE +VPERMPD zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 16 /r ] AVX512,FUTURE VPERMPS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 16 /r ] AVX512,FUTURE -VPERMQ zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 36 /r ] AVX512,FUTURE VPERMQ zmmreg|mask|z,zmmrm512|b64,imm8 [rmi:fv: evex.512.66.0f3a.w1 00 /r ib ] AVX512,FUTURE +VPERMQ zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 36 /r ] AVX512,FUTURE VPERMT2D zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 7e /r ] AVX512,FUTURE VPERMT2PD zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 7f /r ] AVX512,FUTURE VPERMT2PS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 7f /r ] AVX512,FUTURE VPERMT2Q zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 7e /r ] AVX512,FUTURE -VPEXPANDD zmmreg|mask|z,mem512 [rm:t1s: evex.512.66.0f38.w0 89 /r ] AVX512,FUTURE VPEXPANDD zmmreg|mask|z,zmmreg [rm:t1s: evex.512.66.0f38.w0 89 /r ] AVX512,FUTURE +VPEXPANDD zmmreg|mask|z,mem512 [rm:t1s: evex.512.66.0f38.w0 89 /r ] AVX512,FUTURE VPEXPANDQ zmmreg|mask|z,mem512 [rm:t1s: evex.512.66.0f38.w1 89 /r ] AVX512,FUTURE VPEXPANDQ zmmreg|mask|z,zmmreg [rm:t1s: evex.512.66.0f38.w1 89 /r ] AVX512,FUTURE VPGATHERDD zmmreg|mask,zmem32 [rm:t1s: vsibz evex.512.66.0f38.w0 90 /r ] AVX512,FUTURE @@ -3759,16 +3759,16 @@ VPMINSD zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: ev VPMINSQ zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 39 /r ] AVX512,FUTURE VPMINUD zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 3b /r ] AVX512,FUTURE VPMINUQ zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 3b /r ] AVX512,FUTURE -VPMOVDB mem128|mask,zmmreg [mr:qvm: evex.512.f3.0f38.w0 31 /r ] AVX512,FUTURE VPMOVDB xmmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 31 /r ] AVX512,FUTURE -VPMOVDW mem256|mask,zmmreg [mr:hvm: evex.512.f3.0f38.w0 33 /r ] AVX512,FUTURE +VPMOVDB mem128|mask,zmmreg [mr:qvm: evex.512.f3.0f38.w0 31 /r ] AVX512,FUTURE VPMOVDW ymmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 33 /r ] AVX512,FUTURE -VPMOVQB mem64|mask,zmmreg [mr:ovm: evex.512.f3.0f38.w0 32 /r ] AVX512,FUTURE +VPMOVDW mem256|mask,zmmreg [mr:hvm: evex.512.f3.0f38.w0 33 /r ] AVX512,FUTURE VPMOVQB xmmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 32 /r ] AVX512,FUTURE -VPMOVQD mem256|mask,zmmreg [mr:hvm: evex.512.f3.0f38.w0 35 /r ] AVX512,FUTURE +VPMOVQB mem64|mask,zmmreg [mr:ovm: evex.512.f3.0f38.w0 32 /r ] AVX512,FUTURE VPMOVQD ymmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 35 /r ] AVX512,FUTURE -VPMOVQW mem128|mask,zmmreg [mr:qvm: evex.512.f3.0f38.w0 34 /r ] AVX512,FUTURE +VPMOVQD mem256|mask,zmmreg [mr:hvm: evex.512.f3.0f38.w0 35 /r ] AVX512,FUTURE VPMOVQW xmmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 34 /r ] AVX512,FUTURE +VPMOVQW mem128|mask,zmmreg [mr:qvm: evex.512.f3.0f38.w0 34 /r ] AVX512,FUTURE VPMOVSDB mem128|mask,zmmreg [mr:qvm: evex.512.f3.0f38.w0 21 /r ] AVX512,FUTURE VPMOVSDB xmmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 21 /r ] AVX512,FUTURE VPMOVSDW mem256|mask,zmmreg [mr:hvm: evex.512.f3.0f38.w0 23 /r ] AVX512,FUTURE @@ -3777,23 +3777,23 @@ VPMOVSQB mem64|mask,zmmreg [mr:ovm: VPMOVSQB xmmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 22 /r ] AVX512,FUTURE VPMOVSQD mem256|mask,zmmreg [mr:hvm: evex.512.f3.0f38.w0 25 /r ] AVX512,FUTURE VPMOVSQD ymmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 25 /r ] AVX512,FUTURE -VPMOVSQW mem128|mask,zmmreg [mr:qvm: evex.512.f3.0f38.w0 24 /r ] AVX512,FUTURE VPMOVSQW xmmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 24 /r ] AVX512,FUTURE +VPMOVSQW mem128|mask,zmmreg [mr:qvm: evex.512.f3.0f38.w0 24 /r ] AVX512,FUTURE VPMOVSXBD zmmreg|mask|z,xmmrm128 [rm:qvm: evex.512.66.0f38.wig 21 /r ] AVX512,FUTURE VPMOVSXBQ zmmreg|mask|z,xmmrm64 [rm:ovm: evex.512.66.0f38.wig 22 /r ] AVX512,FUTURE VPMOVSXDQ zmmreg|mask|z,ymmrm256 [rm:hvm: evex.512.66.0f38.w0 25 /r ] AVX512,FUTURE VPMOVSXWD zmmreg|mask|z,ymmrm256 [rm:hvm: evex.512.66.0f38.wig 23 /r ] AVX512,FUTURE VPMOVSXWQ zmmreg|mask|z,xmmrm128 [rm:qvm: evex.512.66.0f38.wig 24 /r ] AVX512,FUTURE -VPMOVUSDB mem128|mask,zmmreg [mr:qvm: evex.512.f3.0f38.w0 11 /r ] AVX512,FUTURE VPMOVUSDB xmmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 11 /r ] AVX512,FUTURE -VPMOVUSDW mem256|mask,zmmreg [mr:hvm: evex.512.f3.0f38.w0 13 /r ] AVX512,FUTURE +VPMOVUSDB mem128|mask,zmmreg [mr:qvm: evex.512.f3.0f38.w0 11 /r ] AVX512,FUTURE VPMOVUSDW ymmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 13 /r ] AVX512,FUTURE -VPMOVUSQB mem64|mask,zmmreg [mr:ovm: evex.512.f3.0f38.w0 12 /r ] AVX512,FUTURE +VPMOVUSDW mem256|mask,zmmreg [mr:hvm: evex.512.f3.0f38.w0 13 /r ] AVX512,FUTURE VPMOVUSQB xmmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 12 /r ] AVX512,FUTURE -VPMOVUSQD mem256|mask,zmmreg [mr:hvm: evex.512.f3.0f38.w0 15 /r ] AVX512,FUTURE +VPMOVUSQB mem64|mask,zmmreg [mr:ovm: evex.512.f3.0f38.w0 12 /r ] AVX512,FUTURE VPMOVUSQD ymmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 15 /r ] AVX512,FUTURE -VPMOVUSQW mem128|mask,zmmreg [mr:qvm: evex.512.f3.0f38.w0 14 /r ] AVX512,FUTURE +VPMOVUSQD mem256|mask,zmmreg [mr:hvm: evex.512.f3.0f38.w0 15 /r ] AVX512,FUTURE VPMOVUSQW xmmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 14 /r ] AVX512,FUTURE +VPMOVUSQW mem128|mask,zmmreg [mr:qvm: evex.512.f3.0f38.w0 14 /r ] AVX512,FUTURE VPMOVZXBD zmmreg|mask|z,xmmrm128 [rm:qvm: evex.512.66.0f38.wig 31 /r ] AVX512,FUTURE VPMOVZXBQ zmmreg|mask|z,xmmrm64 [rm:ovm: evex.512.66.0f38.wig 32 /r ] AVX512,FUTURE VPMOVZXDQ zmmreg|mask|z,ymmrm256 [rm:hvm: evex.512.66.0f38.w0 35 /r ] AVX512,FUTURE @@ -3817,22 +3817,22 @@ VPSCATTERDQ ymem64|mask,zmmreg [mr:t1s: vsib VPSCATTERQD zmem32|mask,ymmreg [mr:t1s: vsibz evex.512.66.0f38.w0 a1 /r ] AVX512,FUTURE VPSCATTERQQ zmem64|mask,zmmreg [mr:t1s: vsibz evex.512.66.0f38.w1 a1 /r ] AVX512,FUTURE VPSHUFD zmmreg|mask|z,zmmrm512|b32,imm8 [rmi:fv: evex.512.66.0f.w0 70 /r ib ] AVX512,FUTURE -VPSLLD zmmreg|mask|z,zmmreg,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w0 f2 /r ] AVX512,FUTURE VPSLLD zmmreg|mask|z,zmmrm512|b32,imm8 [vmi:fv: evex.ndd.512.66.0f.w0 72 /6 ib ] AVX512,FUTURE -VPSLLQ zmmreg|mask|z,zmmreg,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w1 f3 /r ] AVX512,FUTURE +VPSLLD zmmreg|mask|z,zmmreg,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w0 f2 /r ] AVX512,FUTURE VPSLLQ zmmreg|mask|z,zmmrm512|b64,imm8 [vmi:fv: evex.ndd.512.66.0f.w1 73 /6 ib ] AVX512,FUTURE +VPSLLQ zmmreg|mask|z,zmmreg,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w1 f3 /r ] AVX512,FUTURE VPSLLVD zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 47 /r ] AVX512,FUTURE VPSLLVQ zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 47 /r ] AVX512,FUTURE -VPSRAD zmmreg|mask|z,zmmreg,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w0 e2 /r ] AVX512,FUTURE VPSRAD zmmreg|mask|z,zmmrm512|b32,imm8 [vmi:fv: evex.ndd.512.66.0f.w0 72 /4 ib ] AVX512,FUTURE -VPSRAQ zmmreg|mask|z,zmmreg,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w1 e2 /r ] AVX512,FUTURE +VPSRAD zmmreg|mask|z,zmmreg,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w0 e2 /r ] AVX512,FUTURE VPSRAQ zmmreg|mask|z,zmmrm512|b64,imm8 [vmi:fv: evex.ndd.512.66.0f.w1 72 /4 ib ] AVX512,FUTURE +VPSRAQ zmmreg|mask|z,zmmreg,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w1 e2 /r ] AVX512,FUTURE VPSRAVD zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 46 /r ] AVX512,FUTURE VPSRAVQ zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 46 /r ] AVX512,FUTURE -VPSRLD zmmreg|mask|z,zmmreg,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w0 d2 /r ] AVX512,FUTURE VPSRLD zmmreg|mask|z,zmmrm512|b32,imm8 [vmi:fv: evex.ndd.512.66.0f.w0 72 /2 ib ] AVX512,FUTURE -VPSRLQ zmmreg|mask|z,zmmreg,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w1 d3 /r ] AVX512,FUTURE +VPSRLD zmmreg|mask|z,zmmreg,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w0 d2 /r ] AVX512,FUTURE VPSRLQ zmmreg|mask|z,zmmrm512|b64,imm8 [vmi:fv: evex.ndd.512.66.0f.w1 73 /2 ib ] AVX512,FUTURE +VPSRLQ zmmreg|mask|z,zmmreg,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w1 d3 /r ] AVX512,FUTURE VPSRLVD zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 45 /r ] AVX512,FUTURE VPSRLVQ zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 45 /r ] AVX512,FUTURE VPSUBD zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 fa /r ] AVX512,FUTURE -- 1.7.9.5 |
|
From: Jin K. S. <jin...@in...> - 2013-08-31 01:11:39
|
If SAE is set, VL(vector length) is implied to be 512.
EVEX.L'L (=EVEX.RC) is set to 00b by default.
Signed-off-by: Jin Kyu Song <jin...@in...>
---
assemble.c | 15 +++++++++------
nasm.h | 3 ++-
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/assemble.c b/assemble.c
index 6ea8be6..ad34523 100644
--- a/assemble.c
+++ b/assemble.c
@@ -1167,15 +1167,18 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
op_er_sae = (ins->evex_brerop >= 0 ?
&ins->oprs[ins->evex_brerop] : NULL);
- if (op_er_sae && (op_er_sae->decoflags & ER)) {
- /* set EVEX.RC (rounding control) and b */
- ins->evex_p[2] |= (((ins->evex_rm - BRC_RN) << 5) & EVEX_P2LL) |
- EVEX_P2B;
+ if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
+ /* set EVEX.b */
+ ins->evex_p[2] |= EVEX_P2B;
+ if (op_er_sae->decoflags & ER) {
+ /* set EVEX.RC (rounding control) */
+ ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
+ & EVEX_P2RC;
+ }
} else {
/* set EVEX.L'L (vector length) */
ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
- if ((op_er_sae && (op_er_sae->decoflags & SAE)) ||
- (opy->decoflags & BRDCAST_MASK)) {
+ if (opy->decoflags & BRDCAST_MASK) {
/* set EVEX.b */
ins->evex_p[2] |= EVEX_P2B;
}
diff --git a/nasm.h b/nasm.h
index e9ef585..50e4b63 100644
--- a/nasm.h
+++ b/nasm.h
@@ -514,7 +514,8 @@ static inline uint8_t get_cond_opcode(enum ccode c)
#define EVEX_P2AAA 0x07 /* EVEX P[18:16] : Embedded opmask */
#define EVEX_P2VP 0x08 /* EVEX P[19] : High-16 NDS reg */
#define EVEX_P2B 0x10 /* EVEX P[20] : Broadcast / RC / SAE */
-#define EVEX_P2LL 0x60 /* EVEX P[22:21] : Vector length / RC */
+#define EVEX_P2LL 0x60 /* EVEX P[22:21] : Vector length */
+#define EVEX_P2RC EVEX_P2LL /* EVEX P[22:21] : Rounding control */
#define EVEX_P2Z 0x80 /* EVEX P[23] : Zeroing/Merging */
/*
--
1.7.9.5
|
|
From: Jin K. S. <jin...@in...> - 2013-08-31 01:11:38
|
EVEX.RC (=00b) should be encoded rather than EVEX.L'L (=10b = 512bit VL)
when {sae} is used. It is because SAE is available only when 512b VL is used.
So the VL is implied like {er} and EVEX.RC becomes 00b since it does not have
a rounding semantic.
Reordered the instructions data mainly in order to comply with the convention
to use the lower opcode when there are more than one candidates.
Jin Kyu Song (2):
AVX-512: Fix rounding mode value in EVEX prefix with SAE
AVX-512: Reorder instructions in insns.dat
assemble.c | 15 ++++----
insns.dat | 114 ++++++++++++++++++++++++++++++------------------------------
nasm.h | 3 +-
3 files changed, 68 insertions(+), 64 deletions(-)
--
1.7.9.5
|
|
From: Cyrill G. <gor...@gm...> - 2013-08-29 06:05:24
|
On Wed, Aug 28, 2013 at 07:15:22PM -0700, Jin Kyu Song wrote:
> To find out the position of the operand containing broadcast,
> embedded roudning or SAE decorator information is a bit tricky
> due to the syntax of putting {er} and {sae} decorators.
> So the position is now stored from the parser if any of these is used.
>
> Opmask instructions (K*) are added in this patch set. These are encoded
> with VEX rather than EVEX even though they are added in AVX-512.
All applied, thanks!
|
|
From: Jin K. S. <jin...@in...> - 2013-08-29 02:16:37
|
Added K* instructions test cases in test/avx512f.asm.
The previous test case from GNU AS were repeating the same instruction twice,
so the repeated half part is removed.
Changed the python script (gas2nasm.py) to include opmask instructions.
Signed-off-by: Jin Kyu Song <jin...@in...>
---
test/avx512f.asm | 4600 +-----------------------------------------------------
test/gas2nasm.py | 2 +-
2 files changed, 24 insertions(+), 4578 deletions(-)
diff --git a/test/avx512f.asm b/test/avx512f.asm
index 45fa0b3..3dcae37 100644
--- a/test/avx512f.asm
+++ b/test/avx512f.asm
@@ -4230,6 +4230,29 @@ testcase { 0x62, 0x62, 0xfd, 0x48, 0x8b, 0xb2, 0xf8, 0xfb, 0xff, 0xff
testcase { 0x62, 0x02, 0xfd, 0x48, 0x8b, 0xee }, { vpcompressq zmm30,zmm29 }
testcase { 0x62, 0x02, 0xfd, 0x4f, 0x8b, 0xee }, { vpcompressq zmm30\{k7\},zmm29 }
testcase { 0x62, 0x02, 0xfd, 0xcf, 0x8b, 0xee }, { vpcompressq zmm30\{k7\}\{z\},zmm29 }
+testcase { 0xc5, 0xcc, 0x41, 0xef }, { kandw k5,k6,k7 }
+testcase { 0xc5, 0xcc, 0x42, 0xef }, { kandnw k5,k6,k7 }
+testcase { 0xc5, 0xcc, 0x45, 0xef }, { korw k5,k6,k7 }
+testcase { 0xc5, 0xcc, 0x46, 0xef }, { kxnorw k5,k6,k7 }
+testcase { 0xc5, 0xcc, 0x47, 0xef }, { kxorw k5,k6,k7 }
+testcase { 0xc5, 0xf8, 0x44, 0xee }, { knotw k5,k6 }
+testcase { 0xc5, 0xf8, 0x98, 0xee }, { kortestw k5,k6 }
+testcase { 0xc4, 0xe3, 0xf9, 0x30, 0xee, 0xab }, { kshiftrw k5,k6,0xab }
+testcase { 0xc4, 0xe3, 0xf9, 0x30, 0xee, 0x7b }, { kshiftrw k5,k6,0x7b }
+testcase { 0xc4, 0xe3, 0xf9, 0x32, 0xee, 0xab }, { kshiftlw k5,k6,0xab }
+testcase { 0xc4, 0xe3, 0xf9, 0x32, 0xee, 0x7b }, { kshiftlw k5,k6,0x7b }
+testcase { 0xc5, 0xf8, 0x90, 0xee }, { kmovw k5,k6 }
+testcase { 0xc5, 0xf8, 0x90, 0x29 }, { kmovw k5,WORD [rcx] }
+testcase { 0xc4, 0xa1, 0x78, 0x90, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { kmovw k5,WORD [rax+r14*8+0x123] }
+testcase { 0xc5, 0xf8, 0x91, 0x29 }, { kmovw WORD [rcx],k5 }
+testcase { 0xc4, 0xa1, 0x78, 0x91, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { kmovw WORD [rax+r14*8+0x123],k5 }
+testcase { 0xc5, 0xf8, 0x92, 0xe8 }, { kmovw k5,eax }
+testcase { 0xc5, 0xf8, 0x92, 0xed }, { kmovw k5,ebp }
+testcase { 0xc4, 0xc1, 0x78, 0x92, 0xed }, { kmovw k5,r13d }
+testcase { 0xc5, 0xf8, 0x93, 0xc5 }, { kmovw eax,k5 }
+testcase { 0xc5, 0xf8, 0x93, 0xed }, { kmovw ebp,k5 }
+testcase { 0xc5, 0x78, 0x93, 0xed }, { kmovw r13d,k5 }
+testcase { 0xc5, 0xcd, 0x4b, 0xef }, { kunpckbw k5,k6,k7 }
testcase { 0x62, 0x63, 0x7d, 0x48, 0x1d, 0x31, 0xab }, { vcvtps2ph YWORD [rcx],zmm30,0xab }
testcase { 0x62, 0x63, 0x7d, 0x4f, 0x1d, 0x31, 0xab }, { vcvtps2ph YWORD [rcx]\{k7\},zmm30,0xab }
testcase { 0x62, 0x63, 0x7d, 0x48, 0x1d, 0x31, 0x7b }, { vcvtps2ph YWORD [rcx],zmm30,0x7b }
@@ -4596,4580 +4619,3 @@ testcase { 0x62, 0x62, 0x95, 0x50, 0x77, 0x72, 0x7f
testcase { 0x62, 0x62, 0x95, 0x50, 0x77, 0xb2, 0x00, 0x04, 0x00, 0x00 }, { vpermi2pd zmm30,zmm29,QWORD [rdx+0x400]\{1to8\} }
testcase { 0x62, 0x62, 0x95, 0x50, 0x77, 0x72, 0x80 }, { vpermi2pd zmm30,zmm29,QWORD [rdx-0x400]\{1to8\} }
testcase { 0x62, 0x62, 0x95, 0x50, 0x77, 0xb2, 0xf8, 0xfb, 0xff, 0xff }, { vpermi2pd zmm30,zmm29,QWORD [rdx-0x408]\{1to8\} }
-testcase { 0x62, 0x01, 0x95, 0x40, 0x58, 0xf4 }, { vaddpd zmm30,zmm29,zmm28 }
-testcase { 0x62, 0x01, 0x95, 0x47, 0x58, 0xf4 }, { vaddpd zmm30\{k7\},zmm29,zmm28 }
-testcase { 0x62, 0x01, 0x95, 0xc7, 0x58, 0xf4 }, { vaddpd zmm30\{k7\}\{z\},zmm29,zmm28 }
-testcase { 0x62, 0x01, 0x95, 0x10, 0x58, 0xf4 }, { vaddpd zmm30,zmm29,zmm28,\{rn-sae\} }
-testcase { 0x62, 0x01, 0x95, 0x50, 0x58, 0xf4 }, { vaddpd zmm30,zmm29,zmm28,\{ru-sae\} }
-testcase { 0x62, 0x01, 0x95, 0x30, 0x58, 0xf4 }, { vaddpd zmm30,zmm29,zmm28,\{rd-sae\} }
-testcase { 0x62, 0x01, 0x95, 0x70, 0x58, 0xf4 }, { vaddpd zmm30,zmm29,zmm28,\{rz-sae\} }
-testcase { 0x62, 0x61, 0x95, 0x40, 0x58, 0x31 }, { vaddpd zmm30,zmm29,ZWORD [rcx] }
-testcase { 0x62, 0x21, 0x95, 0x40, 0x58, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vaddpd zmm30,zmm29,ZWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x61, 0x95, 0x50, 0x58, 0x31 }, { vaddpd zmm30,zmm29,QWORD [rcx]\{1to8\} }
-testcase { 0x62, 0x61, 0x95, 0x40, 0x58, 0x72, 0x7f }, { vaddpd zmm30,zmm29,ZWORD [rdx+0x1fc0] }
-testcase { 0x62, 0x61, 0x95, 0x40, 0x58, 0xb2, 0x00, 0x20, 0x00, 0x00 }, { vaddpd zmm30,zmm29,ZWORD [rdx+0x2000] }
-testcase { 0x62, 0x61, 0x95, 0x40, 0x58, 0x72, 0x80 }, { vaddpd zmm30,zmm29,ZWORD [rdx-0x2000] }
-testcase { 0x62, 0x61, 0x95, 0x40, 0x58, 0xb2, 0xc0, 0xdf, 0xff, 0xff }, { vaddpd zmm30,zmm29,ZWORD [rdx-0x2040] }
-testcase { 0x62, 0x61, 0x95, 0x50, 0x58, 0x72, 0x7f }, { vaddpd zmm30,zmm29,QWORD [rdx+0x3f8]\{1to8\} }
-testcase { 0x62, 0x61, 0x95, 0x50, 0x58, 0xb2, 0x00, 0x04, 0x00, 0x00 }, { vaddpd zmm30,zmm29,QWORD [rdx+0x400]\{1to8\} }
-testcase { 0x62, 0x61, 0x95, 0x50, 0x58, 0x72, 0x80 }, { vaddpd zmm30,zmm29,QWORD [rdx-0x400]\{1to8\} }
-testcase { 0x62, 0x61, 0x95, 0x50, 0x58, 0xb2, 0xf8, 0xfb, 0xff, 0xff }, { vaddpd zmm30,zmm29,QWORD [rdx-0x408]\{1to8\} }
-testcase { 0x62, 0x01, 0x14, 0x40, 0x58, 0xf4 }, { vaddps zmm30,zmm29,zmm28 }
-testcase { 0x62, 0x01, 0x14, 0x47, 0x58, 0xf4 }, { vaddps zmm30\{k7\},zmm29,zmm28 }
-testcase { 0x62, 0x01, 0x14, 0xc7, 0x58, 0xf4 }, { vaddps zmm30\{k7\}\{z\},zmm29,zmm28 }
-testcase { 0x62, 0x01, 0x14, 0x10, 0x58, 0xf4 }, { vaddps zmm30,zmm29,zmm28,\{rn-sae\} }
-testcase { 0x62, 0x01, 0x14, 0x50, 0x58, 0xf4 }, { vaddps zmm30,zmm29,zmm28,\{ru-sae\} }
-testcase { 0x62, 0x01, 0x14, 0x30, 0x58, 0xf4 }, { vaddps zmm30,zmm29,zmm28,\{rd-sae\} }
-testcase { 0x62, 0x01, 0x14, 0x70, 0x58, 0xf4 }, { vaddps zmm30,zmm29,zmm28,\{rz-sae\} }
-testcase { 0x62, 0x61, 0x14, 0x40, 0x58, 0x31 }, { vaddps zmm30,zmm29,ZWORD [rcx] }
-testcase { 0x62, 0x21, 0x14, 0x40, 0x58, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vaddps zmm30,zmm29,ZWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x61, 0x14, 0x50, 0x58, 0x31 }, { vaddps zmm30,zmm29,DWORD [rcx]\{1to16\} }
-testcase { 0x62, 0x61, 0x14, 0x40, 0x58, 0x72, 0x7f }, { vaddps zmm30,zmm29,ZWORD [rdx+0x1fc0] }
-testcase { 0x62, 0x61, 0x14, 0x40, 0x58, 0xb2, 0x00, 0x20, 0x00, 0x00 }, { vaddps zmm30,zmm29,ZWORD [rdx+0x2000] }
-testcase { 0x62, 0x61, 0x14, 0x40, 0x58, 0x72, 0x80 }, { vaddps zmm30,zmm29,ZWORD [rdx-0x2000] }
-testcase { 0x62, 0x61, 0x14, 0x40, 0x58, 0xb2, 0xc0, 0xdf, 0xff, 0xff }, { vaddps zmm30,zmm29,ZWORD [rdx-0x2040] }
-testcase { 0x62, 0x61, 0x14, 0x50, 0x58, 0x72, 0x7f }, { vaddps zmm30,zmm29,DWORD [rdx+0x1fc]\{1to16\} }
-testcase { 0x62, 0x61, 0x14, 0x50, 0x58, 0xb2, 0x00, 0x02, 0x00, 0x00 }, { vaddps zmm30,zmm29,DWORD [rdx+0x200]\{1to16\} }
-testcase { 0x62, 0x61, 0x14, 0x50, 0x58, 0x72, 0x80 }, { vaddps zmm30,zmm29,DWORD [rdx-0x200]\{1to16\} }
-testcase { 0x62, 0x61, 0x14, 0x50, 0x58, 0xb2, 0xfc, 0xfd, 0xff, 0xff }, { vaddps zmm30,zmm29,DWORD [rdx-0x204]\{1to16\} }
-testcase { 0x62, 0x01, 0x97, 0x07, 0x58, 0xf4 }, { vaddsd xmm30\{k7\},xmm29,xmm28 }
-testcase { 0x62, 0x01, 0x97, 0x87, 0x58, 0xf4 }, { vaddsd xmm30\{k7\}\{z\},xmm29,xmm28 }
-testcase { 0x62, 0x01, 0x97, 0x17, 0x58, 0xf4 }, { vaddsd xmm30\{k7\},xmm29,xmm28,\{rn-sae\} }
-testcase { 0x62, 0x01, 0x97, 0x57, 0x58, 0xf4 }, { vaddsd xmm30\{k7\},xmm29,xmm28,\{ru-sae\} }
-testcase { 0x62, 0x01, 0x97, 0x37, 0x58, 0xf4 }, { vaddsd xmm30\{k7\},xmm29,xmm28,\{rd-sae\} }
-testcase { 0x62, 0x01, 0x97, 0x77, 0x58, 0xf4 }, { vaddsd xmm30\{k7\},xmm29,xmm28,\{rz-sae\} }
-testcase { 0x62, 0x61, 0x97, 0x07, 0x58, 0x31 }, { vaddsd xmm30\{k7\},xmm29,QWORD [rcx] }
-testcase { 0x62, 0x21, 0x97, 0x07, 0x58, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vaddsd xmm30\{k7\},xmm29,QWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x61, 0x97, 0x07, 0x58, 0x72, 0x7f }, { vaddsd xmm30\{k7\},xmm29,QWORD [rdx+0x3f8] }
-testcase { 0x62, 0x61, 0x97, 0x07, 0x58, 0xb2, 0x00, 0x04, 0x00, 0x00 }, { vaddsd xmm30\{k7\},xmm29,QWORD [rdx+0x400] }
-testcase { 0x62, 0x61, 0x97, 0x07, 0x58, 0x72, 0x80 }, { vaddsd xmm30\{k7\},xmm29,QWORD [rdx-0x400] }
-testcase { 0x62, 0x61, 0x97, 0x07, 0x58, 0xb2, 0xf8, 0xfb, 0xff, 0xff }, { vaddsd xmm30\{k7\},xmm29,QWORD [rdx-0x408] }
-testcase { 0x62, 0x01, 0x16, 0x07, 0x58, 0xf4 }, { vaddss xmm30\{k7\},xmm29,xmm28 }
-testcase { 0x62, 0x01, 0x16, 0x87, 0x58, 0xf4 }, { vaddss xmm30\{k7\}\{z\},xmm29,xmm28 }
-testcase { 0x62, 0x01, 0x16, 0x17, 0x58, 0xf4 }, { vaddss xmm30\{k7\},xmm29,xmm28,\{rn-sae\} }
-testcase { 0x62, 0x01, 0x16, 0x57, 0x58, 0xf4 }, { vaddss xmm30\{k7\},xmm29,xmm28,\{ru-sae\} }
-testcase { 0x62, 0x01, 0x16, 0x37, 0x58, 0xf4 }, { vaddss xmm30\{k7\},xmm29,xmm28,\{rd-sae\} }
-testcase { 0x62, 0x01, 0x16, 0x77, 0x58, 0xf4 }, { vaddss xmm30\{k7\},xmm29,xmm28,\{rz-sae\} }
-testcase { 0x62, 0x61, 0x16, 0x07, 0x58, 0x31 }, { vaddss xmm30\{k7\},xmm29,DWORD [rcx] }
-testcase { 0x62, 0x21, 0x16, 0x07, 0x58, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vaddss xmm30\{k7\},xmm29,DWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x61, 0x16, 0x07, 0x58, 0x72, 0x7f }, { vaddss xmm30\{k7\},xmm29,DWORD [rdx+0x1fc] }
-testcase { 0x62, 0x61, 0x16, 0x07, 0x58, 0xb2, 0x00, 0x02, 0x00, 0x00 }, { vaddss xmm30\{k7\},xmm29,DWORD [rdx+0x200] }
-testcase { 0x62, 0x61, 0x16, 0x07, 0x58, 0x72, 0x80 }, { vaddss xmm30\{k7\},xmm29,DWORD [rdx-0x200] }
-testcase { 0x62, 0x61, 0x16, 0x07, 0x58, 0xb2, 0xfc, 0xfd, 0xff, 0xff }, { vaddss xmm30\{k7\},xmm29,DWORD [rdx-0x204] }
-testcase { 0x62, 0x03, 0x15, 0x40, 0x03, 0xf4, 0xab }, { valignd zmm30,zmm29,zmm28,0xab }
-testcase { 0x62, 0x03, 0x15, 0x47, 0x03, 0xf4, 0xab }, { valignd zmm30\{k7\},zmm29,zmm28,0xab }
-testcase { 0x62, 0x03, 0x15, 0xc7, 0x03, 0xf4, 0xab }, { valignd zmm30\{k7\}\{z\},zmm29,zmm28,0xab }
-testcase { 0x62, 0x03, 0x15, 0x40, 0x03, 0xf4, 0x7b }, { valignd zmm30,zmm29,zmm28,0x7b }
-testcase { 0x62, 0x63, 0x15, 0x40, 0x03, 0x31, 0x7b }, { valignd zmm30,zmm29,ZWORD [rcx],0x7b }
-testcase { 0x62, 0x23, 0x15, 0x40, 0x03, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00, 0x7b }, { valignd zmm30,zmm29,ZWORD [rax+r14*8+0x1234],0x7b }
-testcase { 0x62, 0x63, 0x15, 0x50, 0x03, 0x31, 0x7b }, { valignd zmm30,zmm29,DWORD [rcx]\{1to16\},0x7b }
-testcase { 0x62, 0x63, 0x15, 0x40, 0x03, 0x72, 0x7f, 0x7b }, { valignd zmm30,zmm29,ZWORD [rdx+0x1fc0],0x7b }
-testcase { 0x62, 0x63, 0x15, 0x40, 0x03, 0xb2, 0x00, 0x20, 0x00, 0x00, 0x7b }, { valignd zmm30,zmm29,ZWORD [rdx+0x2000],0x7b }
-testcase { 0x62, 0x63, 0x15, 0x40, 0x03, 0x72, 0x80, 0x7b }, { valignd zmm30,zmm29,ZWORD [rdx-0x2000],0x7b }
-testcase { 0x62, 0x63, 0x15, 0x40, 0x03, 0xb2, 0xc0, 0xdf, 0xff, 0xff, 0x7b }, { valignd zmm30,zmm29,ZWORD [rdx-0x2040],0x7b }
-testcase { 0x62, 0x63, 0x15, 0x50, 0x03, 0x72, 0x7f, 0x7b }, { valignd zmm30,zmm29,DWORD [rdx+0x1fc]\{1to16\},0x7b }
-testcase { 0x62, 0x63, 0x15, 0x50, 0x03, 0xb2, 0x00, 0x02, 0x00, 0x00, 0x7b }, { valignd zmm30,zmm29,DWORD [rdx+0x200]\{1to16\},0x7b }
-testcase { 0x62, 0x63, 0x15, 0x50, 0x03, 0x72, 0x80, 0x7b }, { valignd zmm30,zmm29,DWORD [rdx-0x200]\{1to16\},0x7b }
-testcase { 0x62, 0x63, 0x15, 0x50, 0x03, 0xb2, 0xfc, 0xfd, 0xff, 0xff, 0x7b }, { valignd zmm30,zmm29,DWORD [rdx-0x204]\{1to16\},0x7b }
-testcase { 0x62, 0x02, 0x95, 0x40, 0x65, 0xf4 }, { vblendmpd zmm30,zmm29,zmm28 }
-testcase { 0x62, 0x02, 0x95, 0x47, 0x65, 0xf4 }, { vblendmpd zmm30\{k7\},zmm29,zmm28 }
-testcase { 0x62, 0x02, 0x95, 0xc7, 0x65, 0xf4 }, { vblendmpd zmm30\{k7\}\{z\},zmm29,zmm28 }
-testcase { 0x62, 0x62, 0x95, 0x40, 0x65, 0x31 }, { vblendmpd zmm30,zmm29,ZWORD [rcx] }
-testcase { 0x62, 0x22, 0x95, 0x40, 0x65, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vblendmpd zmm30,zmm29,ZWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x62, 0x95, 0x50, 0x65, 0x31 }, { vblendmpd zmm30,zmm29,QWORD [rcx]\{1to8\} }
-testcase { 0x62, 0x62, 0x95, 0x40, 0x65, 0x72, 0x7f }, { vblendmpd zmm30,zmm29,ZWORD [rdx+0x1fc0] }
-testcase { 0x62, 0x62, 0x95, 0x40, 0x65, 0xb2, 0x00, 0x20, 0x00, 0x00 }, { vblendmpd zmm30,zmm29,ZWORD [rdx+0x2000] }
-testcase { 0x62, 0x62, 0x95, 0x40, 0x65, 0x72, 0x80 }, { vblendmpd zmm30,zmm29,ZWORD [rdx-0x2000] }
-testcase { 0x62, 0x62, 0x95, 0x40, 0x65, 0xb2, 0xc0, 0xdf, 0xff, 0xff }, { vblendmpd zmm30,zmm29,ZWORD [rdx-0x2040] }
-testcase { 0x62, 0x62, 0x95, 0x50, 0x65, 0x72, 0x7f }, { vblendmpd zmm30,zmm29,QWORD [rdx+0x3f8]\{1to8\} }
-testcase { 0x62, 0x62, 0x95, 0x50, 0x65, 0xb2, 0x00, 0x04, 0x00, 0x00 }, { vblendmpd zmm30,zmm29,QWORD [rdx+0x400]\{1to8\} }
-testcase { 0x62, 0x62, 0x95, 0x50, 0x65, 0x72, 0x80 }, { vblendmpd zmm30,zmm29,QWORD [rdx-0x400]\{1to8\} }
-testcase { 0x62, 0x62, 0x95, 0x50, 0x65, 0xb2, 0xf8, 0xfb, 0xff, 0xff }, { vblendmpd zmm30,zmm29,QWORD [rdx-0x408]\{1to8\} }
-testcase { 0x62, 0x02, 0x15, 0x40, 0x65, 0xf4 }, { vblendmps zmm30,zmm29,zmm28 }
-testcase { 0x62, 0x02, 0x15, 0x47, 0x65, 0xf4 }, { vblendmps zmm30\{k7\},zmm29,zmm28 }
-testcase { 0x62, 0x02, 0x15, 0xc7, 0x65, 0xf4 }, { vblendmps zmm30\{k7\}\{z\},zmm29,zmm28 }
-testcase { 0x62, 0x62, 0x15, 0x40, 0x65, 0x31 }, { vblendmps zmm30,zmm29,ZWORD [rcx] }
-testcase { 0x62, 0x22, 0x15, 0x40, 0x65, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vblendmps zmm30,zmm29,ZWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x62, 0x15, 0x50, 0x65, 0x31 }, { vblendmps zmm30,zmm29,DWORD [rcx]\{1to16\} }
-testcase { 0x62, 0x62, 0x15, 0x40, 0x65, 0x72, 0x7f }, { vblendmps zmm30,zmm29,ZWORD [rdx+0x1fc0] }
-testcase { 0x62, 0x62, 0x15, 0x40, 0x65, 0xb2, 0x00, 0x20, 0x00, 0x00 }, { vblendmps zmm30,zmm29,ZWORD [rdx+0x2000] }
-testcase { 0x62, 0x62, 0x15, 0x40, 0x65, 0x72, 0x80 }, { vblendmps zmm30,zmm29,ZWORD [rdx-0x2000] }
-testcase { 0x62, 0x62, 0x15, 0x40, 0x65, 0xb2, 0xc0, 0xdf, 0xff, 0xff }, { vblendmps zmm30,zmm29,ZWORD [rdx-0x2040] }
-testcase { 0x62, 0x62, 0x15, 0x50, 0x65, 0x72, 0x7f }, { vblendmps zmm30,zmm29,DWORD [rdx+0x1fc]\{1to16\} }
-testcase { 0x62, 0x62, 0x15, 0x50, 0x65, 0xb2, 0x00, 0x02, 0x00, 0x00 }, { vblendmps zmm30,zmm29,DWORD [rdx+0x200]\{1to16\} }
-testcase { 0x62, 0x62, 0x15, 0x50, 0x65, 0x72, 0x80 }, { vblendmps zmm30,zmm29,DWORD [rdx-0x200]\{1to16\} }
-testcase { 0x62, 0x62, 0x15, 0x50, 0x65, 0xb2, 0xfc, 0xfd, 0xff, 0xff }, { vblendmps zmm30,zmm29,DWORD [rdx-0x204]\{1to16\} }
-testcase { 0x62, 0x62, 0x7d, 0x48, 0x1a, 0x31 }, { vbroadcastf32x4 zmm30,OWORD [rcx] }
-testcase { 0x62, 0x62, 0x7d, 0x4f, 0x1a, 0x31 }, { vbroadcastf32x4 zmm30\{k7\},OWORD [rcx] }
-testcase { 0x62, 0x62, 0x7d, 0xcf, 0x1a, 0x31 }, { vbroadcastf32x4 zmm30\{k7\}\{z\},OWORD [rcx] }
-testcase { 0x62, 0x22, 0x7d, 0x48, 0x1a, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vbroadcastf32x4 zmm30,OWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x62, 0x7d, 0x48, 0x1a, 0x72, 0x7f }, { vbroadcastf32x4 zmm30,OWORD [rdx+0x7f0] }
-testcase { 0x62, 0x62, 0x7d, 0x48, 0x1a, 0xb2, 0x00, 0x08, 0x00, 0x00 }, { vbroadcastf32x4 zmm30,OWORD [rdx+0x800] }
-testcase { 0x62, 0x62, 0x7d, 0x48, 0x1a, 0x72, 0x80 }, { vbroadcastf32x4 zmm30,OWORD [rdx-0x800] }
-testcase { 0x62, 0x62, 0x7d, 0x48, 0x1a, 0xb2, 0xf0, 0xf7, 0xff, 0xff }, { vbroadcastf32x4 zmm30,OWORD [rdx-0x810] }
-testcase { 0x62, 0x62, 0xfd, 0x48, 0x1b, 0x31 }, { vbroadcastf64x4 zmm30,YWORD [rcx] }
-testcase { 0x62, 0x62, 0xfd, 0x4f, 0x1b, 0x31 }, { vbroadcastf64x4 zmm30\{k7\},YWORD [rcx] }
-testcase { 0x62, 0x62, 0xfd, 0xcf, 0x1b, 0x31 }, { vbroadcastf64x4 zmm30\{k7\}\{z\},YWORD [rcx] }
-testcase { 0x62, 0x22, 0xfd, 0x48, 0x1b, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vbroadcastf64x4 zmm30,YWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x62, 0xfd, 0x48, 0x1b, 0x72, 0x7f }, { vbroadcastf64x4 zmm30,YWORD [rdx+0xfe0] }
-testcase { 0x62, 0x62, 0xfd, 0x48, 0x1b, 0xb2, 0x00, 0x10, 0x00, 0x00 }, { vbroadcastf64x4 zmm30,YWORD [rdx+0x1000] }
-testcase { 0x62, 0x62, 0xfd, 0x48, 0x1b, 0x72, 0x80 }, { vbroadcastf64x4 zmm30,YWORD [rdx-0x1000] }
-testcase { 0x62, 0x62, 0xfd, 0x48, 0x1b, 0xb2, 0xe0, 0xef, 0xff, 0xff }, { vbroadcastf64x4 zmm30,YWORD [rdx-0x1020] }
-testcase { 0x62, 0x62, 0x7d, 0x48, 0x5a, 0x31 }, { vbroadcasti32x4 zmm30,OWORD [rcx] }
-testcase { 0x62, 0x62, 0x7d, 0x4f, 0x5a, 0x31 }, { vbroadcasti32x4 zmm30\{k7\},OWORD [rcx] }
-testcase { 0x62, 0x62, 0x7d, 0xcf, 0x5a, 0x31 }, { vbroadcasti32x4 zmm30\{k7\}\{z\},OWORD [rcx] }
-testcase { 0x62, 0x22, 0x7d, 0x48, 0x5a, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vbroadcasti32x4 zmm30,OWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x62, 0x7d, 0x48, 0x5a, 0x72, 0x7f }, { vbroadcasti32x4 zmm30,OWORD [rdx+0x7f0] }
-testcase { 0x62, 0x62, 0x7d, 0x48, 0x5a, 0xb2, 0x00, 0x08, 0x00, 0x00 }, { vbroadcasti32x4 zmm30,OWORD [rdx+0x800] }
-testcase { 0x62, 0x62, 0x7d, 0x48, 0x5a, 0x72, 0x80 }, { vbroadcasti32x4 zmm30,OWORD [rdx-0x800] }
-testcase { 0x62, 0x62, 0x7d, 0x48, 0x5a, 0xb2, 0xf0, 0xf7, 0xff, 0xff }, { vbroadcasti32x4 zmm30,OWORD [rdx-0x810] }
-testcase { 0x62, 0x62, 0xfd, 0x48, 0x5b, 0x31 }, { vbroadcasti64x4 zmm30,YWORD [rcx] }
-testcase { 0x62, 0x62, 0xfd, 0x4f, 0x5b, 0x31 }, { vbroadcasti64x4 zmm30\{k7\},YWORD [rcx] }
-testcase { 0x62, 0x62, 0xfd, 0xcf, 0x5b, 0x31 }, { vbroadcasti64x4 zmm30\{k7\}\{z\},YWORD [rcx] }
-testcase { 0x62, 0x22, 0xfd, 0x48, 0x5b, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vbroadcasti64x4 zmm30,YWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x62, 0xfd, 0x48, 0x5b, 0x72, 0x7f }, { vbroadcasti64x4 zmm30,YWORD [rdx+0xfe0] }
-testcase { 0x62, 0x62, 0xfd, 0x48, 0x5b, 0xb2, 0x00, 0x10, 0x00, 0x00 }, { vbroadcasti64x4 zmm30,YWORD [rdx+0x1000] }
-testcase { 0x62, 0x62, 0xfd, 0x48, 0x5b, 0x72, 0x80 }, { vbroadcasti64x4 zmm30,YWORD [rdx-0x1000] }
-testcase { 0x62, 0x62, 0xfd, 0x48, 0x5b, 0xb2, 0xe0, 0xef, 0xff, 0xff }, { vbroadcasti64x4 zmm30,YWORD [rdx-0x1020] }
-testcase { 0x62, 0x62, 0xfd, 0x48, 0x19, 0x31 }, { vbroadcastsd zmm30,QWORD [rcx] }
-testcase { 0x62, 0x62, 0xfd, 0x4f, 0x19, 0x31 }, { vbroadcastsd zmm30\{k7\},QWORD [rcx] }
-testcase { 0x62, 0x62, 0xfd, 0xcf, 0x19, 0x31 }, { vbroadcastsd zmm30\{k7\}\{z\},QWORD [rcx] }
-testcase { 0x62, 0x22, 0xfd, 0x48, 0x19, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vbroadcastsd zmm30,QWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x62, 0xfd, 0x48, 0x19, 0x72, 0x7f }, { vbroadcastsd zmm30,QWORD [rdx+0x3f8] }
-testcase { 0x62, 0x62, 0xfd, 0x48, 0x19, 0xb2, 0x00, 0x04, 0x00, 0x00 }, { vbroadcastsd zmm30,QWORD [rdx+0x400] }
-testcase { 0x62, 0x62, 0xfd, 0x48, 0x19, 0x72, 0x80 }, { vbroadcastsd zmm30,QWORD [rdx-0x400] }
-testcase { 0x62, 0x62, 0xfd, 0x48, 0x19, 0xb2, 0xf8, 0xfb, 0xff, 0xff }, { vbroadcastsd zmm30,QWORD [rdx-0x408] }
-testcase { 0x62, 0x02, 0xfd, 0x4f, 0x19, 0xf5 }, { vbroadcastsd zmm30\{k7\},xmm29 }
-testcase { 0x62, 0x02, 0xfd, 0xcf, 0x19, 0xf5 }, { vbroadcastsd zmm30\{k7\}\{z\},xmm29 }
-testcase { 0x62, 0x62, 0x7d, 0x48, 0x18, 0x31 }, { vbroadcastss zmm30,DWORD [rcx] }
-testcase { 0x62, 0x62, 0x7d, 0x4f, 0x18, 0x31 }, { vbroadcastss zmm30\{k7\},DWORD [rcx] }
-testcase { 0x62, 0x62, 0x7d, 0xcf, 0x18, 0x31 }, { vbroadcastss zmm30\{k7\}\{z\},DWORD [rcx] }
-testcase { 0x62, 0x22, 0x7d, 0x48, 0x18, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vbroadcastss zmm30,DWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x62, 0x7d, 0x48, 0x18, 0x72, 0x7f }, { vbroadcastss zmm30,DWORD [rdx+0x1fc] }
-testcase { 0x62, 0x62, 0x7d, 0x48, 0x18, 0xb2, 0x00, 0x02, 0x00, 0x00 }, { vbroadcastss zmm30,DWORD [rdx+0x200] }
-testcase { 0x62, 0x62, 0x7d, 0x48, 0x18, 0x72, 0x80 }, { vbroadcastss zmm30,DWORD [rdx-0x200] }
-testcase { 0x62, 0x62, 0x7d, 0x48, 0x18, 0xb2, 0xfc, 0xfd, 0xff, 0xff }, { vbroadcastss zmm30,DWORD [rdx-0x204] }
-testcase { 0x62, 0x02, 0x7d, 0x4f, 0x18, 0xf5 }, { vbroadcastss zmm30\{k7\},xmm29 }
-testcase { 0x62, 0x02, 0x7d, 0xcf, 0x18, 0xf5 }, { vbroadcastss zmm30\{k7\}\{z\},xmm29 }
-testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0xab }, { vcmppd k5,zmm30,zmm29,0xab }
-testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0xab }, { vcmppd k5\{k7\},zmm30,zmm29,0xab }
-testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0xab }, { vcmppd k5,zmm30,zmm29,\{sae\},0xab }
-testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x7b }, { vcmppd k5,zmm30,zmm29,0x7b }
-testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x7b }, { vcmppd k5,zmm30,zmm29,\{sae\},0x7b }
-testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x7b }, { vcmppd k5,zmm30,ZWORD [rcx],0x7b }
-testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x34, 0x12, 0x00, 0x00, 0x7b }, { vcmppd k5,zmm30,ZWORD [rax+r14*8+0x1234],0x7b }
-testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x7b }, { vcmppd k5,zmm30,QWORD [rcx]\{1to8\},0x7b }
-testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x7b }, { vcmppd k5,zmm30,ZWORD [rdx+0x1fc0],0x7b }
-testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x7b }, { vcmppd k5,zmm30,ZWORD [rdx+0x2000],0x7b }
-testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x7b }, { vcmppd k5,zmm30,ZWORD [rdx-0x2000],0x7b }
-testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x7b }, { vcmppd k5,zmm30,ZWORD [rdx-0x2040],0x7b }
-testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x7b }, { vcmppd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\},0x7b }
-testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x7b }, { vcmppd k5,zmm30,QWORD [rdx+0x400]\{1to8\},0x7b }
-testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x7b }, { vcmppd k5,zmm30,QWORD [rdx-0x400]\{1to8\},0x7b }
-testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x7b }, { vcmppd k5,zmm30,QWORD [rdx-0x408]\{1to8\},0x7b }
-testcase { 0x62, 0x91, 0x0c, 0x40, 0xc2, 0xed, 0xab }, { vcmpps k5,zmm30,zmm29,0xab }
-testcase { 0x62, 0x91, 0x0c, 0x47, 0xc2, 0xed, 0xab }, { vcmpps k5\{k7\},zmm30,zmm29,0xab }
-testcase { 0x62, 0x91, 0x0c, 0x10, 0xc2, 0xed, 0xab }, { vcmpps k5,zmm30,zmm29,\{sae\},0xab }
-testcase { 0x62, 0x91, 0x0c, 0x40, 0xc2, 0xed, 0x7b }, { vcmpps k5,zmm30,zmm29,0x7b }
-testcase { 0x62, 0x91, 0x0c, 0x10, 0xc2, 0xed, 0x7b }, { vcmpps k5,zmm30,zmm29,\{sae\},0x7b }
-testcase { 0x62, 0xf1, 0x0c, 0x40, 0xc2, 0x29, 0x7b }, { vcmpps k5,zmm30,ZWORD [rcx],0x7b }
-testcase { 0x62, 0xb1, 0x0c, 0x40, 0xc2, 0xac, 0xf0, 0x34, 0x12, 0x00, 0x00, 0x7b }, { vcmpps k5,zmm30,ZWORD [rax+r14*8+0x1234],0x7b }
-testcase { 0x62, 0xf1, 0x0c, 0x50, 0xc2, 0x29, 0x7b }, { vcmpps k5,zmm30,DWORD [rcx]\{1to16\},0x7b }
-testcase { 0x62, 0xf1, 0x0c, 0x40, 0xc2, 0x6a, 0x7f, 0x7b }, { vcmpps k5,zmm30,ZWORD [rdx+0x1fc0],0x7b }
-testcase { 0x62, 0xf1, 0x0c, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x7b }, { vcmpps k5,zmm30,ZWORD [rdx+0x2000],0x7b }
-testcase { 0x62, 0xf1, 0x0c, 0x40, 0xc2, 0x6a, 0x80, 0x7b }, { vcmpps k5,zmm30,ZWORD [rdx-0x2000],0x7b }
-testcase { 0x62, 0xf1, 0x0c, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x7b }, { vcmpps k5,zmm30,ZWORD [rdx-0x2040],0x7b }
-testcase { 0x62, 0xf1, 0x0c, 0x50, 0xc2, 0x6a, 0x7f, 0x7b }, { vcmpps k5,zmm30,DWORD [rdx+0x1fc]\{1to16\},0x7b }
-testcase { 0x62, 0xf1, 0x0c, 0x50, 0xc2, 0xaa, 0x00, 0x02, 0x00, 0x00, 0x7b }, { vcmpps k5,zmm30,DWORD [rdx+0x200]\{1to16\},0x7b }
-testcase { 0x62, 0xf1, 0x0c, 0x50, 0xc2, 0x6a, 0x80, 0x7b }, { vcmpps k5,zmm30,DWORD [rdx-0x200]\{1to16\},0x7b }
-testcase { 0x62, 0xf1, 0x0c, 0x50, 0xc2, 0xaa, 0xfc, 0xfd, 0xff, 0xff, 0x7b }, { vcmpps k5,zmm30,DWORD [rdx-0x204]\{1to16\},0x7b }
-testcase { 0x62, 0x91, 0x97, 0x07, 0xc2, 0xec, 0xab }, { vcmpsd k5\{k7\},xmm29,xmm28,0xab }
-testcase { 0x62, 0x91, 0x97, 0x17, 0xc2, 0xec, 0xab }, { vcmpsd k5\{k7\},xmm29,xmm28,\{sae\},0xab }
-testcase { 0x62, 0x91, 0x97, 0x07, 0xc2, 0xec, 0x7b }, { vcmpsd k5\{k7\},xmm29,xmm28,0x7b }
-testcase { 0x62, 0x91, 0x97, 0x17, 0xc2, 0xec, 0x7b }, { vcmpsd k5\{k7\},xmm29,xmm28,\{sae\},0x7b }
-testcase { 0x62, 0xf1, 0x97, 0x07, 0xc2, 0x29, 0x7b }, { vcmpsd k5\{k7\},xmm29,QWORD [rcx],0x7b }
-testcase { 0x62, 0xb1, 0x97, 0x07, 0xc2, 0xac, 0xf0, 0x34, 0x12, 0x00, 0x00, 0x7b }, { vcmpsd k5\{k7\},xmm29,QWORD [rax+r14*8+0x1234],0x7b }
-testcase { 0x62, 0xf1, 0x97, 0x07, 0xc2, 0x6a, 0x7f, 0x7b }, { vcmpsd k5\{k7\},xmm29,QWORD [rdx+0x3f8],0x7b }
-testcase { 0x62, 0xf1, 0x97, 0x07, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x7b }, { vcmpsd k5\{k7\},xmm29,QWORD [rdx+0x400],0x7b }
-testcase { 0x62, 0xf1, 0x97, 0x07, 0xc2, 0x6a, 0x80, 0x7b }, { vcmpsd k5\{k7\},xmm29,QWORD [rdx-0x400],0x7b }
-testcase { 0x62, 0xf1, 0x97, 0x07, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x7b }, { vcmpsd k5\{k7\},xmm29,QWORD [rdx-0x408],0x7b }
-testcase { 0x62, 0x91, 0x16, 0x07, 0xc2, 0xec, 0xab }, { vcmpss k5\{k7\},xmm29,xmm28,0xab }
-testcase { 0x62, 0x91, 0x16, 0x17, 0xc2, 0xec, 0xab }, { vcmpss k5\{k7\},xmm29,xmm28,\{sae\},0xab }
-testcase { 0x62, 0x91, 0x16, 0x07, 0xc2, 0xec, 0x7b }, { vcmpss k5\{k7\},xmm29,xmm28,0x7b }
-testcase { 0x62, 0x91, 0x16, 0x17, 0xc2, 0xec, 0x7b }, { vcmpss k5\{k7\},xmm29,xmm28,\{sae\},0x7b }
-testcase { 0x62, 0xf1, 0x16, 0x07, 0xc2, 0x29, 0x7b }, { vcmpss k5\{k7\},xmm29,DWORD [rcx],0x7b }
-testcase { 0x62, 0xb1, 0x16, 0x07, 0xc2, 0xac, 0xf0, 0x34, 0x12, 0x00, 0x00, 0x7b }, { vcmpss k5\{k7\},xmm29,DWORD [rax+r14*8+0x1234],0x7b }
-testcase { 0x62, 0xf1, 0x16, 0x07, 0xc2, 0x6a, 0x7f, 0x7b }, { vcmpss k5\{k7\},xmm29,DWORD [rdx+0x1fc],0x7b }
-testcase { 0x62, 0xf1, 0x16, 0x07, 0xc2, 0xaa, 0x00, 0x02, 0x00, 0x00, 0x7b }, { vcmpss k5\{k7\},xmm29,DWORD [rdx+0x200],0x7b }
-testcase { 0x62, 0xf1, 0x16, 0x07, 0xc2, 0x6a, 0x80, 0x7b }, { vcmpss k5\{k7\},xmm29,DWORD [rdx-0x200],0x7b }
-testcase { 0x62, 0xf1, 0x16, 0x07, 0xc2, 0xaa, 0xfc, 0xfd, 0xff, 0xff, 0x7b }, { vcmpss k5\{k7\},xmm29,DWORD [rdx-0x204],0x7b }
-testcase { 0x62, 0x01, 0xfd, 0x08, 0x2f, 0xf5 }, { vcomisd xmm30,xmm29 }
-testcase { 0x62, 0x01, 0xfd, 0x18, 0x2f, 0xf5 }, { vcomisd xmm30,xmm29,\{sae\} }
-testcase { 0x62, 0x61, 0xfd, 0x08, 0x2f, 0x31 }, { vcomisd xmm30,QWORD [rcx] }
-testcase { 0x62, 0x21, 0xfd, 0x08, 0x2f, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vcomisd xmm30,QWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x61, 0xfd, 0x08, 0x2f, 0x72, 0x7f }, { vcomisd xmm30,QWORD [rdx+0x3f8] }
-testcase { 0x62, 0x61, 0xfd, 0x08, 0x2f, 0xb2, 0x00, 0x04, 0x00, 0x00 }, { vcomisd xmm30,QWORD [rdx+0x400] }
-testcase { 0x62, 0x61, 0xfd, 0x08, 0x2f, 0x72, 0x80 }, { vcomisd xmm30,QWORD [rdx-0x400] }
-testcase { 0x62, 0x61, 0xfd, 0x08, 0x2f, 0xb2, 0xf8, 0xfb, 0xff, 0xff }, { vcomisd xmm30,QWORD [rdx-0x408] }
-testcase { 0x62, 0x01, 0x7c, 0x08, 0x2f, 0xf5 }, { vcomiss xmm30,xmm29 }
-testcase { 0x62, 0x01, 0x7c, 0x18, 0x2f, 0xf5 }, { vcomiss xmm30,xmm29,\{sae\} }
-testcase { 0x62, 0x61, 0x7c, 0x08, 0x2f, 0x31 }, { vcomiss xmm30,DWORD [rcx] }
-testcase { 0x62, 0x21, 0x7c, 0x08, 0x2f, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vcomiss xmm30,DWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x61, 0x7c, 0x08, 0x2f, 0x72, 0x7f }, { vcomiss xmm30,DWORD [rdx+0x1fc] }
-testcase { 0x62, 0x61, 0x7c, 0x08, 0x2f, 0xb2, 0x00, 0x02, 0x00, 0x00 }, { vcomiss xmm30,DWORD [rdx+0x200] }
-testcase { 0x62, 0x61, 0x7c, 0x08, 0x2f, 0x72, 0x80 }, { vcomiss xmm30,DWORD [rdx-0x200] }
-testcase { 0x62, 0x61, 0x7c, 0x08, 0x2f, 0xb2, 0xfc, 0xfd, 0xff, 0xff }, { vcomiss xmm30,DWORD [rdx-0x204] }
-testcase { 0x62, 0x62, 0xfd, 0x48, 0x8a, 0x31 }, { vcompresspd ZWORD [rcx],zmm30 }
-testcase { 0x62, 0x62, 0xfd, 0x4f, 0x8a, 0x31 }, { vcompresspd ZWORD [rcx]\{k7\},zmm30 }
-testcase { 0x62, 0x22, 0xfd, 0x48, 0x8a, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vcompresspd ZWORD [rax+r14*8+0x1234],zmm30 }
-testcase { 0x62, 0x62, 0xfd, 0x48, 0x8a, 0x72, 0x7f }, { vcompresspd ZWORD [rdx+0x3f8],zmm30 }
-testcase { 0x62, 0x62, 0xfd, 0x48, 0x8a, 0xb2, 0x00, 0x04, 0x00, 0x00 }, { vcompresspd ZWORD [rdx+0x400],zmm30 }
-testcase { 0x62, 0x62, 0xfd, 0x48, 0x8a, 0x72, 0x80 }, { vcompresspd ZWORD [rdx-0x400],zmm30 }
-testcase { 0x62, 0x62, 0xfd, 0x48, 0x8a, 0xb2, 0xf8, 0xfb, 0xff, 0xff }, { vcompresspd ZWORD [rdx-0x408],zmm30 }
-testcase { 0x62, 0x02, 0xfd, 0x48, 0x8a, 0xee }, { vcompresspd zmm30,zmm29 }
-testcase { 0x62, 0x02, 0xfd, 0x4f, 0x8a, 0xee }, { vcompresspd zmm30\{k7\},zmm29 }
-testcase { 0x62, 0x02, 0xfd, 0xcf, 0x8a, 0xee }, { vcompresspd zmm30\{k7\}\{z\},zmm29 }
-testcase { 0x62, 0x62, 0x7d, 0x48, 0x8a, 0x31 }, { vcompressps ZWORD [rcx],zmm30 }
-testcase { 0x62, 0x62, 0x7d, 0x4f, 0x8a, 0x31 }, { vcompressps ZWORD [rcx]\{k7\},zmm30 }
-testcase { 0x62, 0x22, 0x7d, 0x48, 0x8a, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vcompressps ZWORD [rax+r14*8+0x1234],zmm30 }
-testcase { 0x62, 0x62, 0x7d, 0x48, 0x8a, 0x72, 0x7f }, { vcompressps ZWORD [rdx+0x1fc],zmm30 }
-testcase { 0x62, 0x62, 0x7d, 0x48, 0x8a, 0xb2, 0x00, 0x02, 0x00, 0x00 }, { vcompressps ZWORD [rdx+0x200],zmm30 }
-testcase { 0x62, 0x62, 0x7d, 0x48, 0x8a, 0x72, 0x80 }, { vcompressps ZWORD [rdx-0x200],zmm30 }
-testcase { 0x62, 0x62, 0x7d, 0x48, 0x8a, 0xb2, 0xfc, 0xfd, 0xff, 0xff }, { vcompressps ZWORD [rdx-0x204],zmm30 }
-testcase { 0x62, 0x02, 0x7d, 0x48, 0x8a, 0xee }, { vcompressps zmm30,zmm29 }
-testcase { 0x62, 0x02, 0x7d, 0x4f, 0x8a, 0xee }, { vcompressps zmm30\{k7\},zmm29 }
-testcase { 0x62, 0x02, 0x7d, 0xcf, 0x8a, 0xee }, { vcompressps zmm30\{k7\}\{z\},zmm29 }
-testcase { 0x62, 0x01, 0x7e, 0x4f, 0xe6, 0xf5 }, { vcvtdq2pd zmm30\{k7\},ymm29 }
-testcase { 0x62, 0x01, 0x7e, 0xcf, 0xe6, 0xf5 }, { vcvtdq2pd zmm30\{k7\}\{z\},ymm29 }
-testcase { 0x62, 0x61, 0x7e, 0x4f, 0xe6, 0x31 }, { vcvtdq2pd zmm30\{k7\},YWORD [rcx] }
-testcase { 0x62, 0x21, 0x7e, 0x4f, 0xe6, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vcvtdq2pd zmm30\{k7\},YWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x61, 0x7e, 0x5f, 0xe6, 0x31 }, { vcvtdq2pd zmm30\{k7\},DWORD [rcx]\{1to8\} }
-testcase { 0x62, 0x61, 0x7e, 0x4f, 0xe6, 0x72, 0x7f }, { vcvtdq2pd zmm30\{k7\},YWORD [rdx+0xfe0] }
-testcase { 0x62, 0x61, 0x7e, 0x4f, 0xe6, 0xb2, 0x00, 0x10, 0x00, 0x00 }, { vcvtdq2pd zmm30\{k7\},YWORD [rdx+0x1000] }
-testcase { 0x62, 0x61, 0x7e, 0x4f, 0xe6, 0x72, 0x80 }, { vcvtdq2pd zmm30\{k7\},YWORD [rdx-0x1000] }
-testcase { 0x62, 0x61, 0x7e, 0x4f, 0xe6, 0xb2, 0xe0, 0xef, 0xff, 0xff }, { vcvtdq2pd zmm30\{k7\},YWORD [rdx-0x1020] }
-testcase { 0x62, 0x61, 0x7e, 0x5f, 0xe6, 0x72, 0x7f }, { vcvtdq2pd zmm30\{k7\},DWORD [rdx+0x1fc]\{1to8\} }
-testcase { 0x62, 0x61, 0x7e, 0x5f, 0xe6, 0xb2, 0x00, 0x02, 0x00, 0x00 }, { vcvtdq2pd zmm30\{k7\},DWORD [rdx+0x200]\{1to8\} }
-testcase { 0x62, 0x61, 0x7e, 0x5f, 0xe6, 0x72, 0x80 }, { vcvtdq2pd zmm30\{k7\},DWORD [rdx-0x200]\{1to8\} }
-testcase { 0x62, 0x61, 0x7e, 0x5f, 0xe6, 0xb2, 0xfc, 0xfd, 0xff, 0xff }, { vcvtdq2pd zmm30\{k7\},DWORD [rdx-0x204]\{1to8\} }
-testcase { 0x62, 0x01, 0x7c, 0x48, 0x5b, 0xf5 }, { vcvtdq2ps zmm30,zmm29 }
-testcase { 0x62, 0x01, 0x7c, 0x4f, 0x5b, 0xf5 }, { vcvtdq2ps zmm30\{k7\},zmm29 }
-testcase { 0x62, 0x01, 0x7c, 0xcf, 0x5b, 0xf5 }, { vcvtdq2ps zmm30\{k7\}\{z\},zmm29 }
-testcase { 0x62, 0x01, 0x7c, 0x18, 0x5b, 0xf5 }, { vcvtdq2ps zmm30,zmm29,\{rn-sae\} }
-testcase { 0x62, 0x01, 0x7c, 0x58, 0x5b, 0xf5 }, { vcvtdq2ps zmm30,zmm29,\{ru-sae\} }
-testcase { 0x62, 0x01, 0x7c, 0x38, 0x5b, 0xf5 }, { vcvtdq2ps zmm30,zmm29,\{rd-sae\} }
-testcase { 0x62, 0x01, 0x7c, 0x78, 0x5b, 0xf5 }, { vcvtdq2ps zmm30,zmm29,\{rz-sae\} }
-testcase { 0x62, 0x61, 0x7c, 0x48, 0x5b, 0x31 }, { vcvtdq2ps zmm30,ZWORD [rcx] }
-testcase { 0x62, 0x21, 0x7c, 0x48, 0x5b, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vcvtdq2ps zmm30,ZWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x61, 0x7c, 0x58, 0x5b, 0x31 }, { vcvtdq2ps zmm30,DWORD [rcx]\{1to16\} }
-testcase { 0x62, 0x61, 0x7c, 0x48, 0x5b, 0x72, 0x7f }, { vcvtdq2ps zmm30,ZWORD [rdx+0x1fc0] }
-testcase { 0x62, 0x61, 0x7c, 0x48, 0x5b, 0xb2, 0x00, 0x20, 0x00, 0x00 }, { vcvtdq2ps zmm30,ZWORD [rdx+0x2000] }
-testcase { 0x62, 0x61, 0x7c, 0x48, 0x5b, 0x72, 0x80 }, { vcvtdq2ps zmm30,ZWORD [rdx-0x2000] }
-testcase { 0x62, 0x61, 0x7c, 0x48, 0x5b, 0xb2, 0xc0, 0xdf, 0xff, 0xff }, { vcvtdq2ps zmm30,ZWORD [rdx-0x2040] }
-testcase { 0x62, 0x61, 0x7c, 0x58, 0x5b, 0x72, 0x7f }, { vcvtdq2ps zmm30,DWORD [rdx+0x1fc]\{1to16\} }
-testcase { 0x62, 0x61, 0x7c, 0x58, 0x5b, 0xb2, 0x00, 0x02, 0x00, 0x00 }, { vcvtdq2ps zmm30,DWORD [rdx+0x200]\{1to16\} }
-testcase { 0x62, 0x61, 0x7c, 0x58, 0x5b, 0x72, 0x80 }, { vcvtdq2ps zmm30,DWORD [rdx-0x200]\{1to16\} }
-testcase { 0x62, 0x61, 0x7c, 0x58, 0x5b, 0xb2, 0xfc, 0xfd, 0xff, 0xff }, { vcvtdq2ps zmm30,DWORD [rdx-0x204]\{1to16\} }
-testcase { 0x62, 0x01, 0xff, 0x4f, 0xe6, 0xf5 }, { vcvtpd2dq ymm30\{k7\},zmm29 }
-testcase { 0x62, 0x01, 0xff, 0xcf, 0xe6, 0xf5 }, { vcvtpd2dq ymm30\{k7\}\{z\},zmm29 }
-testcase { 0x62, 0x01, 0xff, 0x1f, 0xe6, 0xf5 }, { vcvtpd2dq ymm30\{k7\},zmm29,\{rn-sae\} }
-testcase { 0x62, 0x01, 0xff, 0x5f, 0xe6, 0xf5 }, { vcvtpd2dq ymm30\{k7\},zmm29,\{ru-sae\} }
-testcase { 0x62, 0x01, 0xff, 0x3f, 0xe6, 0xf5 }, { vcvtpd2dq ymm30\{k7\},zmm29,\{rd-sae\} }
-testcase { 0x62, 0x01, 0xff, 0x7f, 0xe6, 0xf5 }, { vcvtpd2dq ymm30\{k7\},zmm29,\{rz-sae\} }
-testcase { 0x62, 0x61, 0xff, 0x4f, 0xe6, 0x31 }, { vcvtpd2dq ymm30\{k7\},ZWORD [rcx] }
-testcase { 0x62, 0x21, 0xff, 0x4f, 0xe6, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vcvtpd2dq ymm30\{k7\},ZWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x61, 0xff, 0x5f, 0xe6, 0x31 }, { vcvtpd2dq ymm30\{k7\},QWORD [rcx]\{1to8\} }
-testcase { 0x62, 0x61, 0xff, 0x4f, 0xe6, 0x72, 0x7f }, { vcvtpd2dq ymm30\{k7\},ZWORD [rdx+0x1fc0] }
-testcase { 0x62, 0x61, 0xff, 0x4f, 0xe6, 0xb2, 0x00, 0x20, 0x00, 0x00 }, { vcvtpd2dq ymm30\{k7\},ZWORD [rdx+0x2000] }
-testcase { 0x62, 0x61, 0xff, 0x4f, 0xe6, 0x72, 0x80 }, { vcvtpd2dq ymm30\{k7\},ZWORD [rdx-0x2000] }
-testcase { 0x62, 0x61, 0xff, 0x4f, 0xe6, 0xb2, 0xc0, 0xdf, 0xff, 0xff }, { vcvtpd2dq ymm30\{k7\},ZWORD [rdx-0x2040] }
-testcase { 0x62, 0x61, 0xff, 0x5f, 0xe6, 0x72, 0x7f }, { vcvtpd2dq ymm30\{k7\},QWORD [rdx+0x3f8]\{1to8\} }
-testcase { 0x62, 0x61, 0xff, 0x5f, 0xe6, 0xb2, 0x00, 0x04, 0x00, 0x00 }, { vcvtpd2dq ymm30\{k7\},QWORD [rdx+0x400]\{1to8\} }
-testcase { 0x62, 0x61, 0xff, 0x5f, 0xe6, 0x72, 0x80 }, { vcvtpd2dq ymm30\{k7\},QWORD [rdx-0x400]\{1to8\} }
-testcase { 0x62, 0x61, 0xff, 0x5f, 0xe6, 0xb2, 0xf8, 0xfb, 0xff, 0xff }, { vcvtpd2dq ymm30\{k7\},QWORD [rdx-0x408]\{1to8\} }
-testcase { 0x62, 0x01, 0xfd, 0x4f, 0x5a, 0xf5 }, { vcvtpd2ps ymm30\{k7\},zmm29 }
-testcase { 0x62, 0x01, 0xfd, 0xcf, 0x5a, 0xf5 }, { vcvtpd2ps ymm30\{k7\}\{z\},zmm29 }
-testcase { 0x62, 0x01, 0xfd, 0x1f, 0x5a, 0xf5 }, { vcvtpd2ps ymm30\{k7\},zmm29,\{rn-sae\} }
-testcase { 0x62, 0x01, 0xfd, 0x5f, 0x5a, 0xf5 }, { vcvtpd2ps ymm30\{k7\},zmm29,\{ru-sae\} }
-testcase { 0x62, 0x01, 0xfd, 0x3f, 0x5a, 0xf5 }, { vcvtpd2ps ymm30\{k7\},zmm29,\{rd-sae\} }
-testcase { 0x62, 0x01, 0xfd, 0x7f, 0x5a, 0xf5 }, { vcvtpd2ps ymm30\{k7\},zmm29,\{rz-sae\} }
-testcase { 0x62, 0x61, 0xfd, 0x4f, 0x5a, 0x31 }, { vcvtpd2ps ymm30\{k7\},ZWORD [rcx] }
-testcase { 0x62, 0x21, 0xfd, 0x4f, 0x5a, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vcvtpd2ps ymm30\{k7\},ZWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x61, 0xfd, 0x5f, 0x5a, 0x31 }, { vcvtpd2ps ymm30\{k7\},QWORD [rcx]\{1to8\} }
-testcase { 0x62, 0x61, 0xfd, 0x4f, 0x5a, 0x72, 0x7f }, { vcvtpd2ps ymm30\{k7\},ZWORD [rdx+0x1fc0] }
-testcase { 0x62, 0x61, 0xfd, 0x4f, 0x5a, 0xb2, 0x00, 0x20, 0x00, 0x00 }, { vcvtpd2ps ymm30\{k7\},ZWORD [rdx+0x2000] }
-testcase { 0x62, 0x61, 0xfd, 0x4f, 0x5a, 0x72, 0x80 }, { vcvtpd2ps ymm30\{k7\},ZWORD [rdx-0x2000] }
-testcase { 0x62, 0x61, 0xfd, 0x4f, 0x5a, 0xb2, 0xc0, 0xdf, 0xff, 0xff }, { vcvtpd2ps ymm30\{k7\},ZWORD [rdx-0x2040] }
-testcase { 0x62, 0x61, 0xfd, 0x5f, 0x5a, 0x72, 0x7f }, { vcvtpd2ps ymm30\{k7\},QWORD [rdx+0x3f8]\{1to8\} }
-testcase { 0x62, 0x61, 0xfd, 0x5f, 0x5a, 0xb2, 0x00, 0x04, 0x00, 0x00 }, { vcvtpd2ps ymm30\{k7\},QWORD [rdx+0x400]\{1to8\} }
-testcase { 0x62, 0x61, 0xfd, 0x5f, 0x5a, 0x72, 0x80 }, { vcvtpd2ps ymm30\{k7\},QWORD [rdx-0x400]\{1to8\} }
-testcase { 0x62, 0x61, 0xfd, 0x5f, 0x5a, 0xb2, 0xf8, 0xfb, 0xff, 0xff }, { vcvtpd2ps ymm30\{k7\},QWORD [rdx-0x408]\{1to8\} }
-testcase { 0x62, 0x01, 0xfc, 0x4f, 0x79, 0xf5 }, { vcvtpd2udq ymm30\{k7\},zmm29 }
-testcase { 0x62, 0x01, 0xfc, 0xcf, 0x79, 0xf5 }, { vcvtpd2udq ymm30\{k7\}\{z\},zmm29 }
-testcase { 0x62, 0x01, 0xfc, 0x1f, 0x79, 0xf5 }, { vcvtpd2udq ymm30\{k7\},zmm29,\{rn-sae\} }
-testcase { 0x62, 0x01, 0xfc, 0x5f, 0x79, 0xf5 }, { vcvtpd2udq ymm30\{k7\},zmm29,\{ru-sae\} }
-testcase { 0x62, 0x01, 0xfc, 0x3f, 0x79, 0xf5 }, { vcvtpd2udq ymm30\{k7\},zmm29,\{rd-sae\} }
-testcase { 0x62, 0x01, 0xfc, 0x7f, 0x79, 0xf5 }, { vcvtpd2udq ymm30\{k7\},zmm29,\{rz-sae\} }
-testcase { 0x62, 0x61, 0xfc, 0x4f, 0x79, 0x31 }, { vcvtpd2udq ymm30\{k7\},ZWORD [rcx] }
-testcase { 0x62, 0x21, 0xfc, 0x4f, 0x79, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vcvtpd2udq ymm30\{k7\},ZWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x61, 0xfc, 0x5f, 0x79, 0x31 }, { vcvtpd2udq ymm30\{k7\},QWORD [rcx]\{1to8\} }
-testcase { 0x62, 0x61, 0xfc, 0x4f, 0x79, 0x72, 0x7f }, { vcvtpd2udq ymm30\{k7\},ZWORD [rdx+0x1fc0] }
-testcase { 0x62, 0x61, 0xfc, 0x4f, 0x79, 0xb2, 0x00, 0x20, 0x00, 0x00 }, { vcvtpd2udq ymm30\{k7\},ZWORD [rdx+0x2000] }
-testcase { 0x62, 0x61, 0xfc, 0x4f, 0x79, 0x72, 0x80 }, { vcvtpd2udq ymm30\{k7\},ZWORD [rdx-0x2000] }
-testcase { 0x62, 0x61, 0xfc, 0x4f, 0x79, 0xb2, 0xc0, 0xdf, 0xff, 0xff }, { vcvtpd2udq ymm30\{k7\},ZWORD [rdx-0x2040] }
-testcase { 0x62, 0x61, 0xfc, 0x5f, 0x79, 0x72, 0x7f }, { vcvtpd2udq ymm30\{k7\},QWORD [rdx+0x3f8]\{1to8\} }
-testcase { 0x62, 0x61, 0xfc, 0x5f, 0x79, 0xb2, 0x00, 0x04, 0x00, 0x00 }, { vcvtpd2udq ymm30\{k7\},QWORD [rdx+0x400]\{1to8\} }
-testcase { 0x62, 0x61, 0xfc, 0x5f, 0x79, 0x72, 0x80 }, { vcvtpd2udq ymm30\{k7\},QWORD [rdx-0x400]\{1to8\} }
-testcase { 0x62, 0x61, 0xfc, 0x5f, 0x79, 0xb2, 0xf8, 0xfb, 0xff, 0xff }, { vcvtpd2udq ymm30\{k7\},QWORD [rdx-0x408]\{1to8\} }
-testcase { 0x62, 0x02, 0x7d, 0x4f, 0x13, 0xf5 }, { vcvtph2ps zmm30\{k7\},ymm29 }
-testcase { 0x62, 0x02, 0x7d, 0xcf, 0x13, 0xf5 }, { vcvtph2ps zmm30\{k7\}\{z\},ymm29 }
-testcase { 0x62, 0x02, 0x7d, 0x1f, 0x13, 0xf5 }, { vcvtph2ps zmm30\{k7\},ymm29,\{sae\} }
-testcase { 0x62, 0x62, 0x7d, 0x4f, 0x13, 0x31 }, { vcvtph2ps zmm30\{k7\},YWORD [rcx] }
-testcase { 0x62, 0x22, 0x7d, 0x4f, 0x13, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vcvtph2ps zmm30\{k7\},YWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x62, 0x7d, 0x4f, 0x13, 0x72, 0x7f }, { vcvtph2ps zmm30\{k7\},YWORD [rdx+0xfe0] }
-testcase { 0x62, 0x62, 0x7d, 0x4f, 0x13, 0xb2, 0x00, 0x10, 0x00, 0x00 }, { vcvtph2ps zmm30\{k7\},YWORD [rdx+0x1000] }
-testcase { 0x62, 0x62, 0x7d, 0x4f, 0x13, 0x72, 0x80 }, { vcvtph2ps zmm30\{k7\},YWORD [rdx-0x1000] }
-testcase { 0x62, 0x62, 0x7d, 0x4f, 0x13, 0xb2, 0xe0, 0xef, 0xff, 0xff }, { vcvtph2ps zmm30\{k7\},YWORD [rdx-0x1020] }
-testcase { 0x62, 0x01, 0x7d, 0x48, 0x5b, 0xf5 }, { vcvtps2dq zmm30,zmm29 }
-testcase { 0x62, 0x01, 0x7d, 0x4f, 0x5b, 0xf5 }, { vcvtps2dq zmm30\{k7\},zmm29 }
-testcase { 0x62, 0x01, 0x7d, 0xcf, 0x5b, 0xf5 }, { vcvtps2dq zmm30\{k7\}\{z\},zmm29 }
-testcase { 0x62, 0x01, 0x7d, 0x18, 0x5b, 0xf5 }, { vcvtps2dq zmm30,zmm29,\{rn-sae\} }
-testcase { 0x62, 0x01, 0x7d, 0x58, 0x5b, 0xf5 }, { vcvtps2dq zmm30,zmm29,\{ru-sae\} }
-testcase { 0x62, 0x01, 0x7d, 0x38, 0x5b, 0xf5 }, { vcvtps2dq zmm30,zmm29,\{rd-sae\} }
-testcase { 0x62, 0x01, 0x7d, 0x78, 0x5b, 0xf5 }, { vcvtps2dq zmm30,zmm29,\{rz-sae\} }
-testcase { 0x62, 0x61, 0x7d, 0x48, 0x5b, 0x31 }, { vcvtps2dq zmm30,ZWORD [rcx] }
-testcase { 0x62, 0x21, 0x7d, 0x48, 0x5b, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vcvtps2dq zmm30,ZWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x61, 0x7d, 0x58, 0x5b, 0x31 }, { vcvtps2dq zmm30,DWORD [rcx]\{1to16\} }
-testcase { 0x62, 0x61, 0x7d, 0x48, 0x5b, 0x72, 0x7f }, { vcvtps2dq zmm30,ZWORD [rdx+0x1fc0] }
-testcase { 0x62, 0x61, 0x7d, 0x48, 0x5b, 0xb2, 0x00, 0x20, 0x00, 0x00 }, { vcvtps2dq zmm30,ZWORD [rdx+0x2000] }
-testcase { 0x62, 0x61, 0x7d, 0x48, 0x5b, 0x72, 0x80 }, { vcvtps2dq zmm30,ZWORD [rdx-0x2000] }
-testcase { 0x62, 0x61, 0x7d, 0x48, 0x5b, 0xb2, 0xc0, 0xdf, 0xff, 0xff }, { vcvtps2dq zmm30,ZWORD [rdx-0x2040] }
-testcase { 0x62, 0x61, 0x7d, 0x58, 0x5b, 0x72, 0x7f }, { vcvtps2dq zmm30,DWORD [rdx+0x1fc]\{1to16\} }
-testcase { 0x62, 0x61, 0x7d, 0x58, 0x5b, 0xb2, 0x00, 0x02, 0x00, 0x00 }, { vcvtps2dq zmm30,DWORD [rdx+0x200]\{1to16\} }
-testcase { 0x62, 0x61, 0x7d, 0x58, 0x5b, 0x72, 0x80 }, { vcvtps2dq zmm30,DWORD [rdx-0x200]\{1to16\} }
-testcase { 0x62, 0x61, 0x7d, 0x58, 0x5b, 0xb2, 0xfc, 0xfd, 0xff, 0xff }, { vcvtps2dq zmm30,DWORD [rdx-0x204]\{1to16\} }
-testcase { 0x62, 0x01, 0x7c, 0x4f, 0x5a, 0xf5 }, { vcvtps2pd zmm30\{k7\},ymm29 }
-testcase { 0x62, 0x01, 0x7c, 0xcf, 0x5a, 0xf5 }, { vcvtps2pd zmm30\{k7\}\{z\},ymm29 }
-testcase { 0x62, 0x01, 0x7c, 0x1f, 0x5a, 0xf5 }, { vcvtps2pd zmm30\{k7\},ymm29,\{sae\} }
-testcase { 0x62, 0x61, 0x7c, 0x4f, 0x5a, 0x31 }, { vcvtps2pd zmm30\{k7\},YWORD [rcx] }
-testcase { 0x62, 0x21, 0x7c, 0x4f, 0x5a, 0xb4, 0xf0, 0x34, 0x12, 0x00, 0x00 }, { vcvtps2pd zmm30\{k7\},YWORD [rax+r14*8+0x1234] }
-testcase { 0x62, 0x61, 0x7c, 0x5f, 0x5a, 0x31 }, { vcvtps2pd zmm30\{k7\},DWORD [rcx]\{1to8\} }
-testcase { 0x62, 0x61, 0x7c, 0x4f, 0x5a, 0x72, 0x7f }, { vcvtps2pd zmm30\{k7\},YWORD [rdx+0xfe0] }
-testcase { 0x62, 0x61, 0x7c, 0x4f, 0x5a, 0xb2, 0x00, 0x10, 0x00, 0x00 }, { vcvtps2pd zmm30\{k7\},YWORD [rdx+0x1000] }
-testcase { 0x62, 0x61, 0x7c, 0x4f, 0x5a, 0x72, 0x80 }, { vcvtps2pd zmm30\{k7\},YWORD [rdx-0x1000] }
-testcase { 0x62, 0x61, 0x7c, 0x4f, 0x5a, 0xb2, 0xe0, 0xef, 0xff, 0xff }, { vcvtps2pd zmm30\{k7\},YWORD [rdx-0x1020] }
-testcase { 0x62, 0x61, 0x7c, 0x5f, 0x5a, 0x72, 0x7f }, { vcvtps2pd zmm30\{k7\},DWORD [rdx+0x1fc]\{1to8\} }
-testcase { 0x62, 0x61, 0x7c, 0x5f, 0x5a, 0xb2, 0x00, 0x02, 0x00, 0x00 }, { vcvtps2pd zmm30\{k7\},DWORD [rdx+0x200]\{1to8\} }
-testcase { 0x62, 0x61, 0x7c, 0x5f, 0x5a, 0x72, 0x80 }, { vcvtps2pd zmm30\{k7\},DWORD [rdx-0x200]\{1to8\} }
-testcase { 0x6...
[truncated message content] |
|
From: Jin K. S. <jin...@in...> - 2013-08-29 02:16:34
|
Added opmask instructions (kandw and etc). Defined KREG and RM_K aliasing RM_OPMASK and OPMASKREG respectively to make insns.dat look neat. Signed-off-by: Jin Kyu Song <jin...@in...> --- insns.dat | 44 ++++++++++++++++++++++++++++++-------------- opflags.h | 4 +++- 2 files changed, 33 insertions(+), 15 deletions(-) diff --git a/insns.dat b/insns.dat index 772a3e9..cfb2d71 100644 --- a/insns.dat +++ b/insns.dat @@ -3478,10 +3478,10 @@ VBROADCASTSD zmmreg|mask|z,mem64 [rm:t1s: VBROADCASTSD zmmreg|mask|z,xmmreg [rm: evex.512.66.0f38.w1 19 /r ] AVX512,FUTURE VBROADCASTSS zmmreg|mask|z,mem32 [rm:t1s: evex.512.66.0f38.w0 18 /r ] AVX512,FUTURE VBROADCASTSS zmmreg|mask|z,xmmreg [rm: evex.512.66.0f38.w0 18 /r ] AVX512,FUTURE -VCMPPD opmaskreg|mask,zmmreg,zmmrm512|b64|sae,imm8 [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r ib ] AVX512,FUTURE -VCMPPS opmaskreg|mask,zmmreg,zmmrm512|b32|sae,imm8 [rvmi:fv: evex.nds.512.0f.w0 c2 /r ib ] AVX512,FUTURE -VCMPSD opmaskreg|mask,xmmreg,xmmrm64|sae,imm8 [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r ib ] AVX512,FUTURE -VCMPSS opmaskreg|mask,xmmreg,xmmrm32|sae,imm8 [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r ib ] AVX512,FUTURE +VCMPPD kreg|mask,zmmreg,zmmrm512|b64|sae,imm8 [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r ib ] AVX512,FUTURE +VCMPPS kreg|mask,zmmreg,zmmrm512|b32|sae,imm8 [rvmi:fv: evex.nds.512.0f.w0 c2 /r ib ] AVX512,FUTURE +VCMPSD kreg|mask,xmmreg,xmmrm64|sae,imm8 [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r ib ] AVX512,FUTURE +VCMPSS kreg|mask,xmmreg,xmmrm32|sae,imm8 [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r ib ] AVX512,FUTURE VCOMISD xmmreg,xmmrm64|sae [rm:t1s: evex.lig.66.0f.w1 2f /r ] AVX512,FUTURE VCOMISS xmmreg,xmmrm32|sae [rm:t1s: evex.lig.0f.w0 2f /r ] AVX512,FUTURE VCOMPRESSPD mem512|mask,zmmreg [mr:t1s: evex.512.66.0f38.w1 8a /r ] AVX512,FUTURE @@ -3713,14 +3713,14 @@ VPBROADCASTD zmmreg|mask|z,xmmreg [rm: VPBROADCASTQ zmmreg|mask|z,mem64 [rm:t1s: evex.512.66.0f38.w1 59 /r ] AVX512,FUTURE VPBROADCASTQ zmmreg|mask|z,reg64 [rm: evex.512.66.0f38.w1 7c /r ] AVX512,FUTURE VPBROADCASTQ zmmreg|mask|z,xmmreg [rm: evex.512.66.0f38.w1 59 /r ] AVX512,FUTURE -VPCMPD opmaskreg|mask,zmmreg,zmmrm512|b32,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 1f /r ib ] AVX512,FUTURE -VPCMPEQD opmaskreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 76 /r ] AVX512,FUTURE -VPCMPEQQ opmaskreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 29 /r ] AVX512,FUTURE -VPCMPGTD opmaskreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 66 /r ] AVX512,FUTURE -VPCMPGTQ opmaskreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 37 /r ] AVX512,FUTURE -VPCMPQ opmaskreg|mask,zmmreg,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 1f /r ib ] AVX512,FUTURE -VPCMPUD opmaskreg|mask,zmmreg,zmmrm512|b32,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 1e /r ib ] AVX512,FUTURE -VPCMPUQ opmaskreg|mask,zmmreg,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 1e /r ib ] AVX512,FUTURE +VPCMPD kreg|mask,zmmreg,zmmrm512|b32,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 1f /r ib ] AVX512,FUTURE +VPCMPEQD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 76 /r ] AVX512,FUTURE +VPCMPEQQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 29 /r ] AVX512,FUTURE +VPCMPGTD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 66 /r ] AVX512,FUTURE +VPCMPGTQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 37 /r ] AVX512,FUTURE +VPCMPQ kreg|mask,zmmreg,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 1f /r ib ] AVX512,FUTURE +VPCMPUD kreg|mask,zmmreg,zmmrm512|b32,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 1e /r ib ] AVX512,FUTURE +VPCMPUQ kreg|mask,zmmreg,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 1e /r ib ] AVX512,FUTURE VPCOMPRESSD mem512|mask,zmmreg [mr:t1s: evex.512.66.0f38.w0 8b /r ] AVX512,FUTURE VPCOMPRESSD zmmreg|mask|z,zmmreg [mr: evex.512.66.0f38.w0 8b /r ] AVX512,FUTURE VPCOMPRESSQ mem512|mask,zmmreg [mr:t1s: evex.512.66.0f38.w1 8b /r ] AVX512,FUTURE @@ -3839,8 +3839,8 @@ VPSUBD zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: VPSUBQ zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f.w1 fb /r ] AVX512,FUTURE VPTERNLOGD zmmreg|mask|z,zmmreg,zmmrm512|b32,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 25 /r ib ] AVX512,FUTURE VPTERNLOGQ zmmreg|mask|z,zmmreg,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 25 /r ib ] AVX512,FUTURE -VPTESTMD opmaskreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 27 /r ] AVX512,FUTURE -VPTESTMQ opmaskreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 27 /r ] AVX512,FUTURE +VPTESTMD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 27 /r ] AVX512,FUTURE +VPTESTMQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 27 /r ] AVX512,FUTURE VPUNPCKHDQ zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 6a /r ] AVX512,FUTURE VPUNPCKHQDQ zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f.w1 6d /r ] AVX512,FUTURE VPUNPCKLDQ zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 62 /r ] AVX512,FUTURE @@ -3888,6 +3888,22 @@ VUNPCKHPS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: VUNPCKLPD zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f.w1 14 /r ] AVX512,FUTURE VUNPCKLPS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.0f.w0 14 /r ] AVX512,FUTURE +; AVX-512 opmask instructions +KANDNW kreg,kreg,kreg [rvm: vex.nds.l1.0f.w0 42 /r ] AVX512,FUTURE +KANDW kreg,kreg,kreg [rvm: vex.nds.l1.0f.w0 41 /r ] AVX512,FUTURE +KMOVW kreg,krm16 [rm: vex.l0.0f.w0 90 /r ] AVX512,FUTURE +KMOVW kreg,reg32 [rm: vex.l0.0f.w0 92 /r ] AVX512,FUTURE +KMOVW mem16,kreg [mr: vex.l0.0f.w0 91 /r ] AVX512,FUTURE +KMOVW reg32,kreg [rm: vex.l0.0f.w0 93 /r ] AVX512,FUTURE +KNOTW kreg,kreg [rm: vex.l0.0f.w0 44 /r ] AVX512,FUTURE +KORTESTW kreg,kreg [rm: vex.l0.0f.w0 98 /r ] AVX512,FUTURE +KORW kreg,kreg,kreg [rvm: vex.nds.l1.0f.w0 45 /r ] AVX512,FUTURE +KSHIFTLW kreg,kreg,imm8 [rmi: vex.l0.66.0f3a.w1 32 /r ib ] AVX512,FUTURE +KSHIFTRW kreg,kreg,imm8 [rmi: vex.l0.66.0f3a.w1 30 /r ib ] AVX512,FUTURE +KUNPCKBW kreg,kreg,kreg [rvm: vex.nds.l1.66.0f.w0 4b /r ] AVX512,FUTURE +KXNORW kreg,kreg,kreg [rvm: vex.nds.l1.0f.w0 46 /r ] AVX512,FUTURE +KXORW kreg,kreg,kreg [rvm: vex.nds.l1.0f.w0 47 /r ] AVX512,FUTURE + ;# Systematic names for the hinting nop instructions ; These should be last in the file diff --git a/opflags.h b/opflags.h index ee387d7..014abe8 100644 --- a/opflags.h +++ b/opflags.h @@ -194,6 +194,8 @@ #define RM_OPMASK ( REG_CLASS_OPMASK | REGMEM) /* Opmask operand */ #define OPMASKREG ( REG_CLASS_OPMASK | REGMEM | REGISTER) /* Opmask register */ #define OPMASK0 (GEN_SUBCLASS(1) | REG_CLASS_OPMASK | REGMEM | REGISTER) /* Opmask register zero (k0) */ +#define RM_K RM_OPMASK +#define KREG OPMASKREG #define REG_CDT ( REG_CLASS_CDT | BITS32 | REGISTER) /* CRn, DRn and TRn */ #define REG_CREG (GEN_SUBCLASS(1) | REG_CLASS_CDT | BITS32 | REGISTER) /* CRn */ #define REG_DREG (GEN_SUBCLASS(2) | REG_CLASS_CDT | BITS32 | REGISTER) /* DRn */ @@ -241,7 +243,7 @@ #define ZMEM (GEN_SUBCLASS(5) | MEMORY) /* 512-bit vector SIB */ /* memory which matches any type of r/m operand */ -#define MEMORY_ANY (MEMORY | RM_GPR | RM_MMX | RM_XMM | RM_YMM | RM_ZMM) +#define MEMORY_ANY (MEMORY | RM_GPR | RM_MMX | RM_XMM | RM_YMM | RM_ZMM | RM_OPMASK) /* special immediate values */ #define UNITY (GEN_SUBCLASS(0) | IMMEDIATE) /* operand equals 1 */ -- 1.7.9.5 |
|
From: Jin K. S. <jin...@in...> - 2013-08-29 02:16:34
|
Cosmetic change
Signed-off-by: Jin Kyu Song <jin...@in...>
---
nasm.h | 2 +-
regs.dat | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/nasm.h b/nasm.h
index 5ae9d54..e9ef585 100644
--- a/nasm.h
+++ b/nasm.h
@@ -1117,7 +1117,7 @@ enum decorator_tokens {
#define MASK OPMASK_MASK /* Opmask (k1 ~ 7) can be used */
#define Z Z_MASK
-#define B32 (BRDCAST_MASK|BR_BITS32) /* {1to16} : broadcast 32b * 16 to zmm(512b) */
+#define B32 (BRDCAST_MASK|BR_BITS32) /* {1to16} : broadcast 32b * 16 to zmm(512b) */
#define B64 (BRDCAST_MASK|BR_BITS64) /* {1to8} : broadcast 64b * 8 to zmm(512b) */
#define ER STATICRND_MASK /* ER(Embedded Rounding) == Static rounding mode */
#define SAE SAE_MASK /* SAE(Suppress All Exception) */
diff --git a/regs.dat b/regs.dat
index fb112e6..7861119 100644
--- a/regs.dat
+++ b/regs.dat
@@ -128,5 +128,5 @@ zmm0 ZMM0 zmmreg 0
zmm1-31 ZMMREG zmmreg 1
# Opmask registers
-k0 OPMASK0 opmaskreg 0
+k0 OPMASK0 opmaskreg 0
k1-7 OPMASKREG opmaskreg 1 TFLAG_BRC_OPT
--
1.7.9.5
|
|
From: Jin K. S. <jin...@in...> - 2013-08-29 02:16:33
|
Defined IF_SPMASK for specific processor types and
fixed IF_PFMASK to mask the exact preferred bits only.
Signed-off-by: Jin Kyu Song <jin...@in...>
---
insns.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/insns.h b/insns.h
index ad795e2..19b27ae 100644
--- a/insns.h
+++ b/insns.h
@@ -132,7 +132,6 @@ extern const uint8_t nasm_bytecodes[];
#define IF_PMASK 0xFF000000UL /* the mask for processor types */
#define IF_PLEVEL 0x0F000000UL /* the mask for processor instr. level */
/* also the highest possible processor */
-#define IF_PFMASK 0xFFF0000000UL /* the mask for disassembly "prefer" */
#define IF_8086 0x00000000UL /* 8086 instruction */
#define IF_186 0x01000000UL /* 186+ instruction */
#define IF_286 0x02000000UL /* 286+ instruction */
@@ -152,5 +151,7 @@ extern const uint8_t nasm_bytecodes[];
#define IF_IA64 0x0F000000UL /* IA64 instructions (in x86 mode) */
#define IF_CYRIX 0x10000000UL /* Cyrix-specific instruction */
#define IF_AMD 0x20000000UL /* AMD-specific instruction */
+#define IF_SPMASK 0x30000000UL /* specific processor types mask */
+#define IF_PFMASK (IF_INSMASK|IF_SPMASK) /* disassembly "prefer" mask */
#endif /* NASM_INSNS_H */
--
1.7.9.5
|
|
From: Jin K. S. <jin...@in...> - 2013-08-29 02:16:33
|
Register value needs to be checked. Previous patch compared with reg_enum.
Signed-off-by: Jin Kyu Song <jin...@in...>
---
assemble.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/assemble.c b/assemble.c
index d847d37..6ea8be6 100644
--- a/assemble.c
+++ b/assemble.c
@@ -2144,7 +2144,7 @@ static enum match_result matches(const struct itemplate *itemp,
*/
opsizemissing = true;
}
- } else if (instruction->oprs[i].basereg >= 16 &&
+ } else if (nasm_regvals[instruction->oprs[i].basereg] >= 16 &&
(itemp->flags & IF_INSMASK) != IF_AVX512) {
return MERR_ENCMISMATCH;
}
--
1.7.9.5
|
|
From: Jin K. S. <jin...@in...> - 2013-08-29 02:16:32
|
Fixed or purged some old comments and added a comment for a previous patch.
Signed-off-by: Jin Kyu Song <jin...@in...>
---
nasm.h | 3 ++-
regs.dat | 2 +-
test/gas2nasm.py | 1 -
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/nasm.h b/nasm.h
index 8d61748..5ae9d54 100644
--- a/nasm.h
+++ b/nasm.h
@@ -689,12 +689,13 @@ typedef struct insn { /* an instruction itself */
uint8_t evex_p[3]; /* EVEX.P0: [RXB,R',00,mm], P1: [W,vvvv,1,pp] */
/* EVEX.P2: [z,L'L,b,V',aaa] */
enum ttypes evex_tuple; /* Tuple type for compressed Disp8*N */
- int evex_rm; /* static rounding mode for AVX3 (EVEX) */
+ int evex_rm; /* static rounding mode for AVX512 (EVEX) */
int8_t evex_brerop; /* BR/ER/SAE operand position */
} insn;
enum geninfo { GI_SWITCH };
+/* Instruction flags type: IF_* flags are defined in insns.h */
typedef uint64_t iflags_t;
/*
diff --git a/regs.dat b/regs.dat
index 1e083d0..fb112e6 100644
--- a/regs.dat
+++ b/regs.dat
@@ -123,7 +123,7 @@ xmm1-31 XMMREG xmmreg 1
ymm0 YMM0 ymmreg 0
ymm1-31 YMMREG ymmreg 1
-# AVX3 registers
+# AVX512 registers
zmm0 ZMM0 zmmreg 0
zmm1-31 ZMMREG zmmreg 1
diff --git a/test/gas2nasm.py b/test/gas2nasm.py
index a00af92..d0b8579 100755
--- a/test/gas2nasm.py
+++ b/test/gas2nasm.py
@@ -89,7 +89,6 @@ def write_rawbytes(data, options):
if __name__ == "__main__":
options = setup()
recs = read(options)
- print "AVX3.1 instructions"
write_rawbytes(recs, options)
--
1.7.9.5
|
|
From: Jin K. S. <jin...@in...> - 2013-08-29 02:16:32
|
It was not so straight forward to find the postion of operand that has
a broadcasting, embedded rounding mode or SAE (Suppress All Exceptions)
decorator out from operands types or bytecode.
Remebering the postion of the operand of interest in the parser reduces
the burden that assembler looks through the operands.
Signed-off-by: Jin Kyu Song <jin...@in...>
---
assemble.c | 24 ++++++++----------------
nasm.h | 1 +
parser.c | 6 ++++++
3 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/assemble.c b/assemble.c
index b0d4571..d847d37 100644
--- a/assemble.c
+++ b/assemble.c
@@ -1150,7 +1150,7 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
int rfield;
opflags_t rflags;
struct operand *opy = &ins->oprs[op2];
- struct operand *oplast;
+ struct operand *op_er_sae;
ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
@@ -1158,24 +1158,23 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
/* pick rfield from operand b (opx) */
rflags = regflag(opx);
rfield = nasm_regvals[opx->basereg];
- /* find the last SIMD operand where ER decorator resides */
- oplast = &ins->oprs[op1 > op2 ? op1 : op2];
- while (oplast && is_class(REG_CLASS_GPR, oplast->type))
- oplast--;
} else {
rflags = 0;
rfield = c & 7;
- oplast = opy;
}
- if (oplast->decoflags & ER) {
+ /* EVEX.b1 : evex_brerop contains the operand position */
+ op_er_sae = (ins->evex_brerop >= 0 ?
+ &ins->oprs[ins->evex_brerop] : NULL);
+
+ if (op_er_sae && (op_er_sae->decoflags & ER)) {
/* set EVEX.RC (rounding control) and b */
ins->evex_p[2] |= (((ins->evex_rm - BRC_RN) << 5) & EVEX_P2LL) |
EVEX_P2B;
} else {
/* set EVEX.L'L (vector length) */
ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
- if ((oplast->decoflags & SAE) ||
+ if ((op_er_sae && (op_er_sae->decoflags & SAE)) ||
(opy->decoflags & BRDCAST_MASK)) {
/* set EVEX.b */
ins->evex_p[2] |= EVEX_P2B;
@@ -1924,16 +1923,9 @@ static enum match_result find_match(const struct itemplate **tempp,
enum match_result m, merr;
opflags_t xsizeflags[MAX_OPERANDS];
bool opsizemissing = false;
- int8_t broadcast = -1;
+ int8_t broadcast = instruction->evex_brerop;
int i;
- /* find the position of broadcasting operand */
- for (i = 0; i < instruction->operands; i++)
- if (instruction->oprs[i].decoflags & BRDCAST_MASK) {
- broadcast = i;
- break;
- }
-
/* broadcasting uses a different data element size */
for (i = 0; i < instruction->operands; i++)
if (i == broadcast)
diff --git a/nasm.h b/nasm.h
index 72986ee..8d61748 100644
--- a/nasm.h
+++ b/nasm.h
@@ -690,6 +690,7 @@ typedef struct insn { /* an instruction itself */
/* EVEX.P2: [z,L'L,b,V',aaa] */
enum ttypes evex_tuple; /* Tuple type for compressed Disp8*N */
int evex_rm; /* static rounding mode for AVX3 (EVEX) */
+ int8_t evex_brerop; /* BR/ER/SAE operand position */
} insn;
enum geninfo { GI_SWITCH };
diff --git a/parser.c b/parser.c
index 585abe2..1b08657 100644
--- a/parser.c
+++ b/parser.c
@@ -262,6 +262,8 @@ restart_parse:
result->label = NULL; /* Assume no label */
result->eops = NULL; /* must do this, whatever happens */
result->operands = 0; /* must initialize this */
+ result->evex_rm = 0; /* Ensure EVEX rounding mode is reset */
+ result->evex_brerop = -1; /* Reset EVEX broadcasting/ER op position */
/* Ignore blank lines */
if (i == TOKEN_EOS) {
@@ -1034,6 +1036,10 @@ is_expression:
"register size specification ignored");
}
}
+
+ /* remember the position of operand having broadcasting/ER mode */
+ if (result->oprs[operand].decoflags & (BRDCAST_MASK | ER | SAE))
+ result->evex_brerop = operand;
}
result->operands = operand; /* set operand count */
--
1.7.9.5
|
|
From: Jin K. S. <jin...@in...> - 2013-08-29 02:16:31
|
To find out the position of the operand containing broadcast,
embedded roudning or SAE decorator information is a bit tricky
due to the syntax of putting {er} and {sae} decorators.
So the position is now stored from the parser if any of these is used.
Opmask instructions (K*) are added in this patch set. These are encoded
with VEX rather than EVEX even though they are added in AVX-512.
Jin Kyu Song (7):
AVX-512: Remember the position of operand with broadcast or embedded
rounding
AVX-512: Fix comments
AVX-512: Fix bug in checking high-16 registers
AVX-512: Add IF_SPMASK and fix IF_PFMASK
AVX-512: Add OPMASK instructions
AVX-512: Remove trailing space and align columns
AVX-512: Add test case for opmask instructions
assemble.c | 26 +-
insns.dat | 44 +-
insns.h | 3 +-
nasm.h | 6 +-
opflags.h | 4 +-
parser.c | 6 +
regs.dat | 4 +-
test/avx512f.asm | 4600 +-----------------------------------------------------
test/gas2nasm.py | 3 +-
9 files changed, 80 insertions(+), 4616 deletions(-)
--
1.7.9.5
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From: Cyrill G. <gor...@gm...> - 2013-08-28 10:52:47
|
On Wed, Aug 28, 2013 at 02:50:23PM +0400, Cyrill Gorcunov wrote: > > > > Please correct me if I am wrong since I do not think I fully understood > > the whole code history of NASM. > > Yup, sorry for warning, it were all zeros previously, but still I think what > we need here is > > - fix this 64 bitfield to generic bitmap (I've it in my todo list, actually > for too long alredy :-) I'll do this bullet probably on weekend > > - keep all IF_ flags you don't need at moment to zeros but change IF_ value > for those instructions which you need to distinguish in avx512 sake, nothing > else. Once generic bitmaps will be ready we simply update all IF_ flags > to have different bits set and this resolve all problems, no? |
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From: Cyrill G. <gor...@gm...> - 2013-08-28 10:50:33
|
On Wed, Aug 28, 2013 at 10:33:19AM +0000, Song, Jin Kyu wrote: > > > > Why you've changed flags here and a couple of other places? > > > > > > The reason is actually written in the commit message. "Since they are > > not bit masks, only one > > > instruction set is allowed for each instruction." So both SSE and MMX > > could not be set for > > > one instruction. As nasm64developer mentioned in his email, this may not > > be a proper way > > > to expand and define bits for instruction sets. And it needs a major > > restructuring of > > > instruction flags not a simple fix of increasing data type size. > > > > Yes, feature flag is broken, i know. Can't such change affect existing > > code? > > I thought this would not affect existing code because these feature flags were > set to zero until now. The only place using this flag I could find was > 'preferred disasm' part. So I slightly modified the mask bits to make it > compatible with that part of code. > > Please correct me if I am wrong since I do not think I fully understood > the whole code history of NASM. Yup, sorry for warning, it were all zeros previously, but still I think what we need here is - fix this 64 bitfield to generic bitmap (I've it in my todo list, actually for too long alredy :-) - keep all IF_ flags you don't need at moment to zeros but change IF_ value for those instructions which you need to distinguish in avx512 sake, nothing else. Once generic bitmaps will be ready we simply update all IF_ flags to have different bits set and this resolve all problems, no? |
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From: Song, J. K. <jin...@in...> - 2013-08-28 10:33:29
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> > > Why you've changed flags here and a couple of other places? > > > > The reason is actually written in the commit message. "Since they are > not bit masks, only one > > instruction set is allowed for each instruction." So both SSE and MMX > could not be set for > > one instruction. As nasm64developer mentioned in his email, this may not > be a proper way > > to expand and define bits for instruction sets. And it needs a major > restructuring of > > instruction flags not a simple fix of increasing data type size. > > Yes, feature flag is broken, i know. Can't such change affect existing > code? I thought this would not affect existing code because these feature flags were set to zero until now. The only place using this flag I could find was 'preferred disasm' part. So I slightly modified the mask bits to make it compatible with that part of code. Please correct me if I am wrong since I do not think I fully understood the whole code history of NASM. |
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From: Cyrill G. <gor...@gm...> - 2013-08-28 10:29:53
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On Wed, Aug 28, 2013 at 10:20:01AM +0000, Song, Jin Kyu wrote: > > > This one doesn't apply. Please refresh and send again. > > The reason why this patch[4/7] does not apply is that "[PATCH 1/7] AVX-512: Add a test case for EVEX encoded instructions" is not applied first. I had sent [PATCH 1/7] file twice but that is not delivered. I hope this attached patch files are delivered this time. > > Same commits can be found in git://repo.or.cz/nasm/avx512.git, too. All applied and pushed out, thanks! |
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From: Cyrill G. <gor...@gm...> - 2013-08-28 10:26:40
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On Wed, Aug 28, 2013 at 09:55:48AM +0000, Song, Jin Kyu wrote:
> > -----Original Message-----
> > From: Cyrill Gorcunov [mailto:gor...@gm...]
> > Sent: Tuesday, August 27, 2013 10:44 PM
> > To: Song, Jin Kyu
> > Cc: nas...@li...
> > Subject: Re: [Nasm-devel] [PATCH 6/7] AVX-512: Change the data type for
> > instruction flags
> >
> > On Mon, Aug 26, 2013 at 08:28:42PM -0700, Jin Kyu Song wrote:
> > > Increased the size of data type for instruction flags from 32bits to
> > 64bits.
> > > And a new type (iflags_t) is defined for better maintainability.
> > >
> > > Bigger data type is needed because more instruction set types are coming
> > > but there were not enough space for them. Since they are not bit masks,
> > > only one instruction set is allowed for each instruction.
> > >
> > > Signed-off-by: Jin Kyu Song <jin...@in...>
> > > -CVTPI2PS xmmreg,mmxrm64 [rm: np 0f 2a /r]
> > KATMAI,SSE,MMX
> > > -CVTPS2PI mmxreg,xmmrm64 [rm: np 0f 2d /r]
> > KATMAI,SSE,MMX
> > > +CVTPI2PS xmmreg,mmxrm64 [rm: np 0f 2a /r]
> > KATMAI,SSE
> > > +CVTPS2PI mmxreg,xmmrm64 [rm: np 0f 2d /r]
> > KATMAI,SSE
> >
> > Why you've changed flags here and a couple of other places?
>
> The reason is actually written in the commit message. "Since they are not bit masks, only one
> instruction set is allowed for each instruction." So both SSE and MMX could not be set for
> one instruction. As nasm64developer mentioned in his email, this may not be a proper way
> to expand and define bits for instruction sets. And it needs a major restructuring of
> instruction flags not a simple fix of increasing data type size.
Yes, feature flag is broken, i know. Can't such change affect existing code?
>
> The original purpose of this change was merely that I needed a way to distinguish
> EVEX instruction from VEX one which has exactly same operand types. For example,
> "vmovq xmm30,xmm29" should be encoded with EVEX because of high-16 registers but
> in the matches() function, I could not think of a way to see the current
> template being matched is VEX or EVEX except checking the first byte
> of bytecode (0240 or 0260). So I decided to enable instruction set flags in IF_*.
Sounds reasonable, agreed.
> static const struct itemplate instrux_VMOVQ[] = {
> {I_VMOVQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13891, IF_AVX|IF_SANDYBRIDGE|IF_SQ},
> {I_VMOVQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9496, IF_AVX512|IF_FUTURE},
>
> Please let me know any better way to implement this part.
Well, can't think of any better, maybe Peter has something in mind?
(since it's separate branch ouside of master, I'll push it out to
not stop you, but need to revisit this flags place).
|
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From: Cyrill G. <gor...@gm...> - 2013-08-28 10:08:20
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On Tue, Aug 27, 2013 at 10:17:17PM -0700, anonymous coward wrote: > > You already need more than 64 bits to properly map > all existing instructions to their CPUID features (and > in some case you will need to make up a flag, since > CPUID lacks a few of them, e.g. hinting NOPs, hints > for branches, PAUSE, etc.). > > So instead of just widening from 32 to 64 bits, you'll > need a real bit vector, with more than 64 bits. > > Also, this would be a change that you would want to > make on the main tree, not the AVX-512 branch. I knew this day would come once :( Will check on weekend (I hope time will permits) if there not that massive changes needed for generic bitmaps support, sigh... Cyrill |
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From: Jin K. S. <jin...@in...> - 2013-08-28 10:00:20
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>From gas testsuite file, a text file containing raw bytecodes
is useful when verifying the output of NASM.
Signed-off-by: Jin Kyu Song <jin...@in...>
---
test/gas2nasm.py | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/test/gas2nasm.py b/test/gas2nasm.py
index de16745..a00af92 100755
--- a/test/gas2nasm.py
+++ b/test/gas2nasm.py
@@ -21,6 +21,9 @@ def setup():
parser.add_option('-b', dest='bits', action='store',
default="",
help='Bits for output ASM file.')
+ parser.add_option('-r', dest='raw_output', action='store',
+ default="",
+ help='Name for raw output bytes in text')
(options, args) = parser.parse_args()
return options
@@ -77,11 +80,19 @@ def write(data, options):
outstr = outstrfmt % tuple(insn)
out.write(outstr)
+def write_rawbytes(data, options):
+ if options.raw_output:
+ with open(options.raw_output, 'wb') as out:
+ for insn in data:
+ out.write(insn[0] + '\n')
+
if __name__ == "__main__":
options = setup()
recs = read(options)
print "AVX3.1 instructions"
+ write_rawbytes(recs, options)
+
recs = commas(recs)
write(recs, options)
--
1.7.9.5
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