nasm-devel — NASM development work

Re: [Nasm-devel] Instruction flags engine is merged upstream

[Cyrill G. <gor...@gm...>]

On Sun, Nov 24, 2013 at 01:05:46PM -0800, H. Peter Anvin wrote:
> On 11/24/2013 11:31 AM, Cyrill Gorcunov wrote:
> > 
> > Hi Peter, sorry for delay, was out. Look, I can rollback my commits
> > restoring former master and move flags patches out of mainline to
> > a separate tree (just one revert for all commits, it'll be easy).
> > The reason I merged it into master was that -- without rebase I've
> > got a number of merge problems because of new IF_ flags introduced
> > into master, so the longer I stay out of mainline the harder it will
> > be to port back. But again, Peter, it's not a problem to revert, just
> > say a word ;)
> 
> There is no reason to revert.  If it turns out to be a problem we can
> just fork a new branch off 305f3cee04d1adf3f4e335c5645814f2b67e8a69 and
> then re-merge later.

OK, great. As far as I remember, Jin said the new engine is pretty fine
for him, still better to double check this moment.

Re: [Nasm-devel] Instruction flags engine is merged upstream

[H. P. A. <hp...@zy...>]

On 11/24/2013 11:31 AM, Cyrill Gorcunov wrote:
> 
> Hi Peter, sorry for delay, was out. Look, I can rollback my commits
> restoring former master and move flags patches out of mainline to
> a separate tree (just one revert for all commits, it'll be easy).
> The reason I merged it into master was that -- without rebase I've
> got a number of merge problems because of new IF_ flags introduced
> into master, so the longer I stay out of mainline the harder it will
> be to port back. But again, Peter, it's not a problem to revert, just
> say a word ;)
> 

There is no reason to revert.  If it turns out to be a problem we can
just fork a new branch off 305f3cee04d1adf3f4e335c5645814f2b67e8a69 and
then re-merge later.

> Also merge here make no much sence because the commits are almost unsplittable,
> I tried to make them as simple as I can, but the change of @flags is too much
> fundamental.
> 
> As to SSE,MMX, SSE,FPU flags -- the only purpose I've had initially is to
> restore flags 1:1 as they were before avx512 changes. In future I think
> we may provide a user options to select more flags from command line
> and allow to filter instructions.
> 

That makes sense.  And yes, and the idea was that we'd be able to
enhance the CPU directive to filter instructions at some point.

	-hpa

Re: [Nasm-devel] Instruction flags engine is merged upstream

[Cyrill G. <gor...@gm...>]

On Sun, Nov 24, 2013 at 10:59:18AM -0800, H. Peter Anvin wrote:
> On 11/24/2013 01:29 AM, Cyrill Gorcunov wrote:
> > Hi guys, I've just merged up the reworked instruction flags engine.
> > Please review. I mostly worried about dissassembler part, which I
> > supposed I've converted well but more eyes needed here.
> > 
> > 	Cyrill
> 
> Oh, nevermind... I see you did it as a rebase rather than as a merge.
> Generally a merge is better since it preserves more of the history.
> 
> Jin, do you think this will slow down the AVX512 support, or is it fine
> as-is?
> 
> I'm not sure to what extent the SSE,MMX and SSE,FPU flags combinations
> ever made any sense... I don't think they ever made all that much sense
> it was more of "what do we do with this?"

Hi Peter, sorry for delay, was out. Look, I can rollback my commits
restoring former master and move flags patches out of mainline to
a separate tree (just one revert for all commits, it'll be easy).
The reason I merged it into master was that -- without rebase I've
got a number of merge problems because of new IF_ flags introduced
into master, so the longer I stay out of mainline the harder it will
be to port back. But again, Peter, it's not a problem to revert, just
say a word ;)

Also merge here make no much sence because the commits are almost unsplittable,
I tried to make them as simple as I can, but the change of @flags is too much
fundamental.

As to SSE,MMX, SSE,FPU flags -- the only purpose I've had initially is to
restore flags 1:1 as they were before avx512 changes. In future I think
we may provide a user options to select more flags from command line
and allow to filter instructions.

Re: [Nasm-devel] Instruction flags engine is merged upstream

[H. P. A. <hp...@zy...>]

On 11/24/2013 01:29 AM, Cyrill Gorcunov wrote:
> Hi guys, I've just merged up the reworked instruction flags engine.
> Please review. I mostly worried about dissassembler part, which I
> supposed I've converted well but more eyes needed here.
> 
> 	Cyrill

Oh, nevermind... I see you did it as a rebase rather than as a merge.
Generally a merge is better since it preserves more of the history.

Jin, do you think this will slow down the AVX512 support, or is it fine
as-is?

I'm not sure to what extent the SSE,MMX and SSE,FPU flags combinations
ever made any sense... I don't think they ever made all that much sense
it was more of "what do we do with this?"

	-hpa

Re: [Nasm-devel] Instruction flags engine is merged upstream

[H. P. A. <hp...@zy...>]

On 11/24/2013 01:29 AM, Cyrill Gorcunov wrote:
> Hi guys, I've just merged up the reworked instruction flags engine.
> Please review. I mostly worried about dissassembler part, which I
> supposed I've converted well but more eyes needed here.
> 
> 	Cyrill

Hi Cyrill... I don't see this merge in master, but perhaps could we hold
off on this until we can get a release out with AVX512 &c support?  This
is getting really urgent.

	-hpa

[Nasm-devel] Instruction flags engine is merged upstream

[Cyrill G. <gor...@gm...>]

Hi guys, I've just merged up the reworked instruction flags engine.
Please review. I mostly worried about dissassembler part, which I
supposed I've converted well but more eyes needed here.

	Cyrill

Re: [Nasm-devel] [PATCH 2/9] MPX: Adapt GAS's mib syntax with an index reg only

[Cyrill G. <gor...@gm...>]

On Mon, Nov 11, 2013 at 07:20:49AM -0800, anonymous coward wrote:
> You might find the attached file useful for
> creating additional NASM test cases.

May we have your Signed-off-by: nas...@us... ?

Re: [Nasm-devel] [PATCH 4/9] AVX512: Update instruction group

[anonymous c. <nas...@us...>]

>> CPUID bit for vptestnm[dq] changed.
>> vptestnm[dq]: AVX512CD -> AVX512F
>
> The public #319433-015 spec says AVX512CD, not AVX512F.

Ah, it looks like there is a -016 now.

Intel should fix all of the "stale" links to -015 on their site.  :)

Re: [Nasm-devel] [PATCH 5/9] PREFETCHWT1: Add a new instruction flag

[anonymous c. <nas...@us...>]

On 11/11/13, anonymous coward <nas...@us...> wrote:
>> PREFETCHWT1 instruction's CPUID was TBD before.
>> Now it has its new CPUID bit : PREFETCHWT1
>
> The public #319433-015 spec says TBD.

Ah, it looks like there is a -016 now.

Intel should fix all of the "stale" links to -015 on their site.  :)

Re: [Nasm-devel] [PATCH 5/9] PREFETCHWT1: Add a new instruction flag

[anonymous c. <nas...@us...>]

> PREFETCHWT1 instruction's CPUID was TBD before.
> Now it has its new CPUID bit : PREFETCHWT1

The public #319433-015 spec says TBD.

Re: [Nasm-devel] [PATCH 4/9] AVX512: Update instruction group

[anonymous c. <nas...@us...>]

> CPUID bit for vptestnm[dq] changed.
> vptestnm[dq]: AVX512CD -> AVX512F

The public #319433-015 spec says AVX512CD, not AVX512F.

Re: [Nasm-devel] [PATCH 2/9] MPX: Adapt GAS's mib syntax with an index reg only

[anonymous c. <nas...@us...>]

You might find the attached file useful for
creating additional NASM test cases.

Re: [Nasm-devel] [PATCH 0/9] Bug fixes and improvements

[H. P. A. <hp...@zy...>]

On 11/08/2013 08:14 PM, Jin Kyu Song wrote:
> A bug which encoded zmm16~23 as zmm24~31 is fixed. Some improvement has
> been done for MPX : compatible with gas's mib encoding with no base reg.
> There were some changes in CPUID bits for AVX-512 instructions. And in a case
> that a user wants to force nasm to encode an instruction in evex,
> {evex} prefix is now added.
> The logic to match broadcasting operand is improved and now it makes sure
> the broadcasting decorator {1to<n>} is correctly written.
> 
> All these commits can be pulled from git://repo.or.cz/nasm/avx512.git , too.
> 

That branch shares no common history with the NASM master branch, so I
tried to apply the patchset manually (minus patch #1, which is already
in master.)

It doesn't apply, presumably because the baseline is subtly different.

I would ask that you regenerate the patchset onto the master branch and
commit it.  At this point we have already merged in avx512 into the
master branch, so we might as well just finish the job there.

	-hpa

Re: [Nasm-devel] [PATCH 0/9] Bug fixes and improvements

[Cyrill G. <gor...@gm...>]

On Fri, Nov 08, 2013 at 08:14:53PM -0800, Jin Kyu Song wrote:
> A bug which encoded zmm16~23 as zmm24~31 is fixed. Some improvement has
> been done for MPX : compatible with gas's mib encoding with no base reg.
> There were some changes in CPUID bits for AVX-512 instructions. And in a case
> that a user wants to force nasm to encode an instruction in evex,
> {evex} prefix is now added.
> The logic to match broadcasting operand is improved and now it makes sure
> the broadcasting decorator {1to<n>} is correctly written.
> 
> All these commits can be pulled from git://repo.or.cz/nasm/avx512.git , too.

Great job, Jin! Btw, why not merging this stuff into avx512 branch in nasm
repo which was created exactly for avx512 development things?

[Nasm-devel] [PATCH 8/9] match: Improve broadcast opsize matching

[Jin K. S. <jin...@in...>]

Broadcasting operand size is different from the original
operand size because 32b or 64b element is repeated to form a vector.
So when matching a broadcasting operand, opsize should be treated
differently.
The broadcasting element size is specified in the decorator information.

Signed-off-by: Jin Kyu Song <jin...@in...>
---
 assemble.c |   55 +++++++++++++++++++++++++++++++++++--------------------
 1 file changed, 35 insertions(+), 20 deletions(-)

diff --git a/assemble.c b/assemble.c
index 11a7db6..afc5457 100644
--- a/assemble.c
+++ b/assemble.c
@@ -2020,10 +2020,13 @@ static enum match_result find_match(const struct itemplate **tempp,
         if ((xsizeflags[i] & (xsizeflags[i]-1)))
             goto done;                /* No luck */
 
-        if (i == broadcast)
+        if (i == broadcast) {
             instruction->oprs[i].decoflags |= xsizeflags[i];
-        else
+            instruction->oprs[i].type |= (xsizeflags[i] == BR_BITS32 ?
+                                          BITS32 : BITS64);
+        } else {
             instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
+        }
     }
 
     /* Try matching again... */
@@ -2159,32 +2162,44 @@ static enum match_result matches(const struct itemplate *itemp,
     for (i = 0; i < itemp->operands; i++) {
         opflags_t type = instruction->oprs[i].type;
         decoflags_t deco = instruction->oprs[i].decoflags;
+        bool is_broadcast = deco & BRDCAST_MASK;
+        opflags_t template_opsize, insn_opsize;
+
         if (!(type & SIZE_MASK))
             type |= size[i];
 
+        insn_opsize     = type & SIZE_MASK;
+        if (!is_broadcast) {
+            template_opsize = itemp->opd[i] & SIZE_MASK;
+        } else {
+            decoflags_t deco_brsize = itemp->deco[i] & BRSIZE_MASK;
+            /*
+             * when broadcasting, the element size depends on
+             * the instruction type. decorator flag should match.
+             */
+
+            if (deco_brsize) {
+                template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
+            } else {
+                template_opsize = 0;
+            }
+        }
+
         if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
             (itemp->deco[i] & deco) != deco) {
             return MERR_INVALOP;
-        } else if ((itemp->opd[i] & SIZE_MASK) &&
-                   (itemp->opd[i] & SIZE_MASK) != (type & SIZE_MASK)) {
-            if (type & SIZE_MASK) {
-                /*
-                 * when broadcasting, the element size depends on
-                 * the instruction type. decorator flag should match.
-                 */
-#define MATCH_BRSZ(bits) (((type & SIZE_MASK) == BITS##bits) &&             \
-                          ((itemp->deco[i] & BRSIZE_MASK) == BR_BITS##bits))
-                if (!((deco & BRDCAST_MASK) &&
-                      (MATCH_BRSZ(32) || MATCH_BRSZ(64)))) {
+        } else if (template_opsize) {
+            if (template_opsize != insn_opsize) {
+                if (insn_opsize) {
                     return MERR_INVALOP;
+                } else if (!is_class(REGISTER, type)) {
+                    /*
+                     * Note: we don't honor extrinsic operand sizes for registers,
+                     * so "missing operand size" for a register should be
+                     * considered a wildcard match rather than an error.
+                     */
+                    opsizemissing = true;
                 }
-            } else if (!is_class(REGISTER, type)) {
-                /*
-                 * Note: we don't honor extrinsic operand sizes for registers,
-                 * so "missing operand size" for a register should be
-                 * considered a wildcard match rather than an error.
-                 */
-                opsizemissing = true;
             }
         } else if (is_register(instruction->oprs[i].basereg) &&
                    nasm_regvals[instruction->oprs[i].basereg] >= 16 &&
-- 
1.7.9.5

[Nasm-devel] [PATCH 9/9] match: Check the number of elements in broadcasting operands

[Jin K. S. <jin...@in...>]

The broadcasting decorator {1to##} must describe exactly how many times
the memory element is repeated in order to clearly match the correct
instruction format.

For example,
    vaddpd zmm30,zmm29,QWORD [rdx+0x3f8]{1to8}   ; good
    vaddpd zmm30,zmm29,QWORD [rdx+0x3f8]{1to16}  ; fail qword * 16 = 1024b

    vaddps zmm30,zmm29,DWORD [rcx]{1to16}	 ; good
    vaddps zmm30,zmm29,DWORD [rcx]{1to8}	 ; fail dword * 8 = 256b

Signed-off-by: Jin Kyu Song <jin...@in...>
---
 assemble.c |   21 ++++++++++++++++++++-
 nasm.h     |   14 ++++++++++++++
 parser.c   |    3 ++-
 3 files changed, 36 insertions(+), 2 deletions(-)

diff --git a/assemble.c b/assemble.c
index afc5457..6aeb9a2 100644
--- a/assemble.c
+++ b/assemble.c
@@ -189,6 +189,7 @@ enum match_result {
     MERR_INVALOP,
     MERR_OPSIZEMISSING,
     MERR_OPSIZEMISMATCH,
+    MERR_BRNUMMISMATCH,
     MERR_BADCPU,
     MERR_BADMODE,
     MERR_BADHLE,
@@ -671,6 +672,10 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, iflags_t cp,
         case MERR_OPSIZEMISMATCH:
             error(ERR_NONFATAL, "mismatch in operand sizes");
             break;
+        case MERR_BRNUMMISMATCH:
+            error(ERR_NONFATAL,
+                  "mismatch in the number of broadcasting elements");
+            break;
         case MERR_BADCPU:
             error(ERR_NONFATAL, "no instruction for this cpu level");
             break;
@@ -2163,6 +2168,7 @@ static enum match_result matches(const struct itemplate *itemp,
         opflags_t type = instruction->oprs[i].type;
         decoflags_t deco = instruction->oprs[i].decoflags;
         bool is_broadcast = deco & BRDCAST_MASK;
+        uint8_t brcast_num = 0;
         opflags_t template_opsize, insn_opsize;
 
         if (!(type & SIZE_MASK))
@@ -2180,13 +2186,16 @@ static enum match_result matches(const struct itemplate *itemp,
 
             if (deco_brsize) {
                 template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
+                /* calculate the proper number : {1to<brcast_num>} */
+                brcast_num = (itemp->opd[i] & SIZE_MASK) / BITS128 *
+                                BITS64 / template_opsize * 2;
             } else {
                 template_opsize = 0;
             }
         }
 
         if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
-            (itemp->deco[i] & deco) != deco) {
+            (deco & ~itemp->deco[i] & ~BRNUM_MASK)) {
             return MERR_INVALOP;
         } else if (template_opsize) {
             if (template_opsize != insn_opsize) {
@@ -2200,6 +2209,16 @@ static enum match_result matches(const struct itemplate *itemp,
                      */
                     opsizemissing = true;
                 }
+            } else if (is_broadcast &&
+                       (brcast_num !=
+                        (8U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
+                /*
+                 * broadcasting opsize matches but the number of repeated memory
+                 * element does not match.
+                 * if 64b double precision float is broadcasted to zmm (512b),
+                 * broadcasting decorator must be {1to8}.
+                 */
+                return MERR_BRNUMMISMATCH;
             }
         } else if (is_register(instruction->oprs[i].basereg) &&
                    nasm_regvals[instruction->oprs[i].basereg] >= 16 &&
diff --git a/nasm.h b/nasm.h
index 34adc69..b68a8ba 100644
--- a/nasm.h
+++ b/nasm.h
@@ -1048,6 +1048,7 @@ enum decorator_tokens {
  * .........................1...... static rounding
  * ........................1....... SAE
  * ......................11........ broadcast element size
+ * ....................11.......... number of broadcast elements
  */
 #define OP_GENVAL(val, bits, shift)     (((val) & ((UINT64_C(1) << (bits)) - 1)) << (shift))
 
@@ -1119,6 +1120,19 @@ enum decorator_tokens {
 #define BR_BITS32               GEN_BRSIZE(0)
 #define BR_BITS64               GEN_BRSIZE(1)
 
+/*
+ * Number of broadcasting elements
+ *
+ * Bits: 10 - 11
+ */
+#define BRNUM_SHIFT             (10)
+#define BRNUM_BITS              (2)
+#define BRNUM_MASK              OP_GENMASK(BRNUM_BITS, BRNUM_SHIFT)
+#define VAL_BRNUM(val)          OP_GENVAL(val, BRNUM_BITS, BRNUM_SHIFT)
+
+#define BR_1TO8                 VAL_BRNUM(0)
+#define BR_1TO16                VAL_BRNUM(1)
+
 #define MASK                    OPMASK_MASK             /* Opmask (k1 ~ 7) can be used */
 #define Z                       Z_MASK
 #define B32                     (BRDCAST_MASK|BR_BITS32) /* {1to16} : broadcast 32b * 16 to zmm(512b) */
diff --git a/parser.c b/parser.c
index 7112781..9a54ce6 100644
--- a/parser.c
+++ b/parser.c
@@ -946,7 +946,8 @@ is_expression:
                      * is expected for memory reference operands
                      */
                     if (tokval.t_flag & TFLAG_BRDCAST) {
-                        brace_flags |= GEN_BRDCAST(0);
+                        brace_flags |= GEN_BRDCAST(0) |
+                                       VAL_BRNUM(tokval.t_integer - BRC_1TO8);
                         i = stdscan(NULL, &tokval);
                     } else if (i == TOKEN_OPMASK) {
                         brace_flags |= VAL_OPMASK(nasm_regvals[tokval.t_integer]);
-- 
1.7.9.5

[Nasm-devel] [PATCH 7/9] Build: Suppress warning messages

[Jin K. S. <jin...@in...>]

Giving a correct printf format specifier supresses the warning message.
And a local pointer variable is initialized with NULL.

Signed-off-by: Jin Kyu Song <jin...@in...>
---
 parser.c  |    2 +-
 preproc.c |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/parser.c b/parser.c
index 4207702..7112781 100644
--- a/parser.c
+++ b/parser.c
@@ -212,7 +212,7 @@ static bool parse_braces(decoflags_t *decoflags)
     do {
         if (i == TOKEN_OPMASK) {
             if (*decoflags & OPMASK_MASK) {
-                nasm_error(ERR_NONFATAL, "opmask k%lu is already set",
+                nasm_error(ERR_NONFATAL, "opmask k%"PRIu64" is already set",
                            *decoflags & OPMASK_MASK);
                 *decoflags &= ~OPMASK_MASK;
             }
diff --git a/preproc.c b/preproc.c
index b878e4b..8a0c2c8 100644
--- a/preproc.c
+++ b/preproc.c
@@ -2156,7 +2156,7 @@ static int do_directive(Token * tline)
     Context *ctx;
     Cond *cond;
     MMacro *mmac, **mmhead;
-    Token *t, *tt, *param_start, *macro_start, *last, **tptr, *origline;
+    Token *t = NULL, *tt, *param_start, *macro_start, *last, **tptr, *origline;
     Line *l;
     struct tokenval tokval;
     expr *evalresult;
-- 
1.7.9.5

[Nasm-devel] [PATCH 6/9] AVX-512: Add {evex} instruction prefix

[Jin K. S. <jin...@in...>]

For instructions that can be encoded either in VEX or EVEX,
{evex} forces nasm to encode in EVEX.

Signed-off-by: Jin Kyu Song <jin...@in...>
---
 assemble.c |    7 +++++++
 nasm.h     |    2 ++
 parser.c   |    2 ++
 tokens.dat |    3 +++
 4 files changed, 14 insertions(+)

diff --git a/assemble.c b/assemble.c
index 89a7e00..11a7db6 100644
--- a/assemble.c
+++ b/assemble.c
@@ -632,6 +632,9 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, iflags_t cp,
                     case P_OSP:
                         c = 0x66;
                         break;
+                    case P_EVEX:
+                        /* EVEX */
+                        break;
                     case P_none:
                         break;
                     default:
@@ -786,6 +789,7 @@ int64_t insn_size(int32_t segment, int64_t offset, int bits, iflags_t cp,
                 break;
             case P_A64:
             case P_O64:
+            case P_EVEX:
             case P_none:
                 break;
             default:
@@ -2186,6 +2190,9 @@ static enum match_result matches(const struct itemplate *itemp,
                    nasm_regvals[instruction->oprs[i].basereg] >= 16 &&
                    !(itemp->flags & IF_AVX512)) {
             return MERR_ENCMISMATCH;
+        } else if (instruction->prefixes[PPS_EVEX] &&
+                   !(itemp->flags & IF_AVX512)) {
+            return MERR_ENCMISMATCH;
         }
     }
 
diff --git a/nasm.h b/nasm.h
index 5ca2aa5..34adc69 100644
--- a/nasm.h
+++ b/nasm.h
@@ -553,6 +553,7 @@ enum prefixes { /* instruction prefixes */
     P_XACQUIRE,
     P_XRELEASE,
     P_BND,
+    P_EVEX,
     PREFIX_ENUM_LIMIT
 };
 
@@ -635,6 +636,7 @@ enum prefix_pos {
     PPS_SEG,    /* Segment override prefix */
     PPS_OSIZE,  /* Operand size prefix */
     PPS_ASIZE,  /* Address size prefix */
+    PPS_EVEX,   /* EVEX prefix */
     MAXPREFIX   /* Total number of prefix slots */
 };
 
diff --git a/parser.c b/parser.c
index 092135d..4207702 100644
--- a/parser.c
+++ b/parser.c
@@ -101,6 +101,8 @@ static int prefix_slot(int prefix)
     case P_A64:
     case P_ASP:
         return PPS_ASIZE;
+    case P_EVEX:
+        return PPS_EVEX;
     default:
         nasm_error(ERR_PANIC, "Invalid value %d passed to prefix_slot()", prefix);
         return -1;
diff --git a/tokens.dat b/tokens.dat
index 211eb09..284cf30 100644
--- a/tokens.dat
+++ b/tokens.dat
@@ -122,3 +122,6 @@ rz-sae
 % TOKEN_DECORATOR, 0, TFLAG_BRC, BRC_*
 sae
 z
+
+% TOKEN_PREFIX, 0, TFLAG_BRC, P_*
+evex
-- 
1.7.9.5

[Nasm-devel] [PATCH 5/9] PREFETCHWT1: Add a new instruction flag

[Jin K. S. <jin...@in...>]

PREFETCHWT1 instruction's CPUID was TBD before.
Now it has its new CPUID bit : PREFETCHWT1

Signed-off-by: Jin Kyu Song <jin...@in...>
---
 insns.dat |    2 +-
 insns.h   |    1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/insns.dat b/insns.dat
index c169772..de89cfa 100644
--- a/insns.dat
+++ b/insns.dat
@@ -4144,7 +4144,7 @@ VSCATTERPF1DPD  ymem64|mask  [m:t1s:    vsiby evex.512.66.0f38.w1 c6 /6 ]  AVX51
 VSCATTERPF1DPS  zmem32|mask  [m:t1s:    vsibz evex.512.66.0f38.w0 c6 /6 ]  AVX512PF,FUTURE
 VSCATTERPF1QPD  zmem64|mask  [m:t1s:    vsibz evex.512.66.0f38.w1 c7 /6 ]  AVX512PF,FUTURE
 VSCATTERPF1QPS  zmem32|mask  [m:t1s:    vsibz evex.512.66.0f38.w0 c7 /6 ]  AVX512PF,FUTURE
-PREFETCHWT1     mem8         [m:                               0f 0d /2 ]  FUTURE
+PREFETCHWT1     mem8         [m:                               0f 0d /2 ]  PREFETCHWT1,FUTURE
 
 ; MPX instructions
 BNDMK       bndreg,mem32           [rm:     o32 f3 0f 1b /r ]  MPX,SD,FUTURE
diff --git a/insns.h b/insns.h
index 0320e8d..dd447c5 100644
--- a/insns.h
+++ b/insns.h
@@ -135,6 +135,7 @@ extern const uint8_t nasm_bytecodes[];
 #define IF_AVX512PF     (UINT64_C(0x1800000000)|IF_AVX512) /* AVX-512 Prefetch instructions */
 #define IF_MPX          UINT64_C(0x1900000000)    /* MPX instructions */
 #define IF_SHA          UINT64_C(0x1A00000000)    /* SHA instructions */
+#define IF_PREFETCHWT1  UINT64_C(0x1F00000000)    /* PREFETCHWT1 instructions */
 #define IF_INSMASK      UINT64_C(0xFF00000000)    /* the mask for instruction set types */
 #define IF_PMASK        UINT64_C(0xFF000000)    /* the mask for processor types */
 #define IF_PLEVEL       UINT64_C(0x0F000000)    /* the mask for processor instr. level */
-- 
1.7.9.5

[Nasm-devel] [PATCH 3/9] MPX: Move BND prefix indication from bytecode to iflags

[Jin K. S. <jin...@in...>]

As BND prefix validity check conflicts with jcc8 prefix,
IF_BND is added for the instruction templates which can have
bnd prefix for preserving the content of bound register.

Signed-off-by: Jin Kyu Song <jin...@in...>
---
 assemble.c |    6 ++--
 disasm.c   |    7 +----
 insns.dat  |   91 ++++++++++++++++++++++++++++++------------------------------
 insns.h    |    1 +
 insns.pl   |    1 -
 5 files changed, 50 insertions(+), 56 deletions(-)

diff --git a/assemble.c b/assemble.c
index 2f35cd9..89a7e00 100644
--- a/assemble.c
+++ b/assemble.c
@@ -162,7 +162,6 @@
  * \367          - address-size prefix (0x67) used as opcode extension
  * \370,\371     - match only if operand 0 meets byte jump criteria.
  *                 370 is used for Jcc, 371 is used for JMP.
- * \372          - BND prefix (0xF2 byte) used for preserving bnd0..3
  * \373          - assemble 0x03 if bits==16, 0x05 if bits==32;
  *                 used for conditional jump over longer jump
  * \374          - this instruction takes an XMM VSIB memory EA
@@ -1124,7 +1123,8 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
             length++;
             break;
 
-        case3(0370):
+        case 0370:
+        case 0371:
             break;
 
         case 0373:
@@ -2244,7 +2244,7 @@ static enum match_result matches(const struct itemplate *itemp,
     /*
      * Check if BND prefix is allowed
      */
-    if ((itemp->code[0] != 0372) &&
+    if ((IF_BND & ~itemp->flags) &&
         has_prefix(instruction, PPS_REP, P_BND))
         return MERR_BADBND;
 
diff --git a/disasm.c b/disasm.c
index eace1e9..6498610 100644
--- a/disasm.c
+++ b/disasm.c
@@ -408,7 +408,7 @@ static int matches(const struct itemplate *t, uint8_t *data,
         return false;
 
     if (prefix->rep == 0xF2)
-        drep = P_REPNE;
+        drep = (t->flags & IF_BND ? P_BND : P_REPNE);
     else if (prefix->rep == 0xF3)
         drep = P_REP;
 
@@ -862,11 +862,6 @@ static int matches(const struct itemplate *t, uint8_t *data,
         case 0371:
             break;
 
-        case 0372:
-            if (prefix->rep == 0xF2)
-                drep = P_BND;
-            break;
-
         case 0374:
             eat = EA_XMMVSIB;
             break;
diff --git a/insns.dat b/insns.dat
index 3906dba..e67a242 100644
--- a/insns.dat
+++ b/insns.dat
@@ -274,22 +274,22 @@ CALL		rm16				[m:	o16 ff /2]				8086,NOLONG
 CALL		rm32				[m:	o32 ff /2]				386,NOLONG
 CALL		rm64				[m:	o64nw ff /2]				X64
 ; BND + CALL
-CALL		imm				[i:	bnd odf e8 rel]				8086,MPX
-CALL		imm|near			[i:	bnd odf e8 rel]				8086,ND,MPX
-CALL		imm16				[i:	bnd o16 e8 rel]				8086,NOLONG,MPX
-CALL		imm16|near			[i:	bnd o16 e8 rel]				8086,ND,NOLONG,MPX
-CALL		imm32				[i:	bnd o32 e8 rel]				386,NOLONG,MPX
-CALL		imm32|near			[i:	bnd o32 e8 rel]				386,ND,NOLONG,MPX
-CALL		imm64				[i:	bnd o64nw e8 rel]			X64,MPX
-CALL		imm64|near			[i:	bnd o64nw e8 rel]			X64,ND,MPX
-CALL		mem|near			[m:	bnd odf ff /2]				8086,ND,MPX
-CALL		rm16|near			[m:	bnd o16 ff /2]				8086,NOLONG,ND,MPX
-CALL		rm32|near			[m:	bnd o32 ff /2]				386,NOLONG,ND,MPX
-CALL		rm64|near			[m:	bnd o64nw ff /2]			X64,ND,MPX
-CALL		mem				[m:	bnd odf ff /2]				8086,MPX
-CALL		rm16				[m:	bnd o16 ff /2]				8086,NOLONG,MPX
-CALL		rm32				[m:	bnd o32 ff /2]				386,NOLONG,MPX
-CALL		rm64				[m:	bnd o64nw ff /2]			X64,MPX
+CALL		imm				[i:	odf e8 rel]				8086,MPX,BND
+CALL		imm|near			[i:	odf e8 rel]				8086,ND,MPX,BND
+CALL		imm16				[i:	o16 e8 rel]				8086,NOLONG,MPX,BND
+CALL		imm16|near			[i:	o16 e8 rel]				8086,ND,NOLONG,MPX,BND
+CALL		imm32				[i:	o32 e8 rel]				386,NOLONG,MPX,BND
+CALL		imm32|near			[i:	o32 e8 rel]				386,ND,NOLONG,MPX,BND
+CALL		imm64				[i:	o64nw e8 rel]				X64,MPX,BND
+CALL		imm64|near			[i:	o64nw e8 rel]				X64,ND,MPX,BND
+CALL		mem|near			[m:	odf ff /2]				8086,ND,MPX,BND
+CALL		rm16|near			[m:	o16 ff /2]				8086,NOLONG,ND,MPX,BND
+CALL		rm32|near			[m:	o32 ff /2]				386,NOLONG,ND,MPX,BND
+CALL		rm64|near			[m:	o64nw ff /2]				X64,ND,MPX,BND
+CALL		mem				[m:	odf ff /2]				8086,MPX,BND
+CALL		rm16				[m:	o16 ff /2]				8086,NOLONG,MPX,BND
+CALL		rm32				[m:	o32 ff /2]				386,NOLONG,MPX,BND
+CALL		rm64				[m:	o64nw ff /2]				X64,MPX,BND
 
 CBW		void				[	o16 98]					8086
 CDQ		void				[	o32 99]					386
@@ -725,22 +725,22 @@ JMP		rm16				[m:	o16 ff /4]				8086,NOLONG
 JMP		rm32				[m:	o32 ff /4]				386,NOLONG
 JMP		rm64				[m:	o64nw ff /4]				X64
 ; BND + JMP
-JMP		imm				[i:	bnd odf e9 rel]				8086,MPX
-JMP		imm|near			[i:	bnd odf e9 rel]				8086,ND,MPX
-JMP		imm16				[i:	bnd o16 e9 rel]				8086,NOLONG,MPX
-JMP		imm16|near			[i:	bnd o16 e9 rel]				8086,ND,NOLONG,MPX
-JMP		imm32				[i:	bnd o32 e9 rel]				386,NOLONG,MPX
-JMP		imm32|near			[i:	bnd o32 e9 rel]				386,ND,NOLONG,MPX
-JMP		imm64				[i:	bnd o64nw e9 rel]			X64,MPX
-JMP		imm64|near			[i:	bnd o64nw e9 rel]			X64,ND,MPX
-JMP		mem|near			[m:	bnd odf ff /4]				8086,ND,MPX
-JMP		rm16|near			[m:	bnd o16 ff /4]				8086,NOLONG,ND,MPX
-JMP		rm32|near			[m:	bnd o32 ff /4]				386,NOLONG,ND,MPX
-JMP		rm64|near			[m:	bnd o64nw ff /4]			X64,ND,MPX
-JMP		mem				[m:	bnd odf ff /4]				8086,MPX
-JMP		rm16				[m:	bnd o16 ff /4]				8086,NOLONG,MPX
-JMP		rm32				[m:	bnd o32 ff /4]				386,NOLONG,MPX
-JMP		rm64				[m:	bnd o64nw ff /4]			X64,MPX
+JMP		imm				[i:	odf e9 rel]				8086,MPX,BND
+JMP		imm|near			[i:	odf e9 rel]				8086,ND,MPX,BND
+JMP		imm16				[i:	o16 e9 rel]				8086,NOLONG,MPX,BND
+JMP		imm16|near			[i:	o16 e9 rel]				8086,ND,NOLONG,MPX,BND
+JMP		imm32				[i:	o32 e9 rel]				386,NOLONG,MPX,BND
+JMP		imm32|near			[i:	o32 e9 rel]				386,ND,NOLONG,MPX,BND
+JMP		imm64				[i:	o64nw e9 rel]				X64,MPX,BND
+JMP		imm64|near			[i:	o64nw e9 rel]				X64,ND,MPX,BND
+JMP		mem|near			[m:	odf ff /4]				8086,ND,MPX,BND
+JMP		rm16|near			[m:	o16 ff /4]				8086,NOLONG,ND,MPX,BND
+JMP		rm32|near			[m:	o32 ff /4]				386,NOLONG,ND,MPX,BND
+JMP		rm64|near			[m:	o64nw ff /4]				X64,ND,MPX,BND
+JMP		mem				[m:	odf ff /4]				8086,MPX,BND
+JMP		rm16				[m:	o16 ff /4]				8086,NOLONG,MPX,BND
+JMP		rm32				[m:	o32 ff /4]				386,NOLONG,MPX,BND
+JMP		rm64				[m:	o64nw ff /4]				X64,MPX,BND
 
 JMPE		imm				[i:	odf 0f b8 rel]				IA64
 JMPE		imm16				[i:	o16 0f b8 rel]				IA64
@@ -1154,10 +1154,10 @@ RETF		imm				[i:	ca iw]					8086,SW
 RETN		void				[	c3]					8086
 RETN		imm				[i:	c2 iw]					8086,SW
 ; BND + RET
-RET		void				[	bnd c3]					8086,MPX
-RET		imm				[i:	bnd c2 iw]				8086,SW,MPX
-RETN		void				[	bnd c3]					8086,MPX
-RETN		imm				[i:	bnd c2 iw]				8086,SW,MPX
+RET		void				[	c3]					8086,MPX,BND
+RET		imm				[i:	c2 iw]					8086,SW,MPX,BND
+RETN		void				[	c3]					8086,MPX,BND
+RETN		imm				[i:	c2 iw]					8086,SW,MPX,BND
 
 ROL		rm8,unity			[m-:	d0 /0]					8086
 ROL		rm8,reg_cl			[m-:	d2 /0]					8086
@@ -1526,16 +1526,15 @@ Jcc		imm				[i:	0f 80+c rel]				386,ND
 Jcc		imm				[i:	71+c jlen e9 rel]			8086,ND
 Jcc		imm				[i:	70+c rel8]				8086
 ; BND + Jcc
-Jcc		imm|near			[i:	bnd odf 0f 80+c rel]		386,MPX
-Jcc		imm16|near			[i:	bnd o16 0f 80+c rel]		386,NOLONG,MPX
-Jcc		imm32|near			[i:	bnd o32 0f 80+c rel]		386,NOLONG,MPX
-Jcc		imm64|near			[i:	bnd o64nw 0f 80+c rel]		X64,MPX
-Jcc		imm|short			[i:	bnd 70+c rel8]			8086,ND,MPX
-; TODO: check if bnd and jcc8 can be used together
-;Jcc		imm				[i:	bnd jcc8 70+c rel8]		8086,ND,MPX
-Jcc		imm				[i:	bnd 0f 80+c rel]		386,ND,MPX
-Jcc		imm				[i:	bnd 71+c jlen e9 rel]		8086,ND,MPX
-Jcc		imm				[i:	bnd 70+c rel8]			8086,MPX
+Jcc		imm|near			[i:	odf 0f 80+c rel]		386,MPX,BND
+Jcc		imm16|near			[i:	o16 0f 80+c rel]		386,NOLONG,MPX,BND
+Jcc		imm32|near			[i:	o32 0f 80+c rel]		386,NOLONG,MPX,BND
+Jcc		imm64|near			[i:	o64nw 0f 80+c rel]		X64,MPX,BND
+Jcc		imm|short			[i:	70+c rel8]			8086,ND,MPX,BND
+Jcc		imm				[i:	jcc8 70+c rel8]			8086,ND,MPX,BND
+Jcc		imm				[i:	0f 80+c rel]			386,ND,MPX,BND
+Jcc		imm				[i:	71+c jlen e9 rel]		8086,ND,MPX,BND
+Jcc		imm				[i:	70+c rel8]			8086,MPX,BND
 
 SETcc		mem				[m:	0f 90+c /0]				386,SB
 SETcc		reg8				[m:	0f 90+c /0]				386
diff --git a/insns.h b/insns.h
index a170533..0320e8d 100644
--- a/insns.h
+++ b/insns.h
@@ -105,6 +105,7 @@ extern const uint8_t nasm_bytecodes[];
 #define IF_LONG         UINT64_C(0x00001000)    /* long mode instruction */
 #define IF_NOHLE        UINT64_C(0x00002000)    /* HLE prefixes forbidden */
 #define IF_MIB          UINT64_C(0x00004000)    /* Disassemble with split EA */
+#define IF_BND          UINT64_C(0x00008000)    /* BND (0xF2) prefix available */
 /* These flags are currently not used for anything - intended for insn set */
 #define IF_UNDOC        UINT64_C(0x8000000000)    /* it's an undocumented instruction */
 #define IF_HLE          UINT64_C(0x4000000000)    /* HACK NEED TO REORGANIZE THESE BITS */
diff --git a/insns.pl b/insns.pl
index 40478df..f897794 100755
--- a/insns.pl
+++ b/insns.pl
@@ -765,7 +765,6 @@ sub byte_code_compile($$) {
         'resb'      => 0340,
         'jcc8'      => 0370,    # Match only if Jcc possible with single byte
         'jmp8'      => 0371,    # Match only if JMP possible with single byte
-        'bnd'       => 0372,    # BND (0xF2) prefix available
         'jlen'      => 0373,    # Length of jump
         'hlexr'     => 0271,
         'hlenl'     => 0272,
-- 
1.7.9.5

[Nasm-devel] [PATCH 4/9] AVX512: Update instruction group

[Jin K. S. <jin...@in...>]

CPUID bit for vptestnm[dq] changed.
vptestnm[dq]: AVX512CD -> AVX512F

Signed-off-by: Jin Kyu Song <jin...@in...>
---
 insns.dat |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/insns.dat b/insns.dat
index e67a242..c169772 100644
--- a/insns.dat
+++ b/insns.dat
@@ -4044,6 +4044,8 @@ VPTERNLOGD       zmmreg|mask|z,zmmreg,zmmrm512|b32,imm8        [rvmi:fv:   evex.
 VPTERNLOGQ       zmmreg|mask|z,zmmreg,zmmrm512|b64,imm8        [rvmi:fv:   evex.nds.512.66.0f3a.w1 25 /r ib ]  AVX512,FUTURE
 VPTESTMD         kreg|mask,zmmreg,zmmrm512|b32                 [rvm:fv:       evex.nds.512.66.0f38.w0 27 /r ]  AVX512,FUTURE
 VPTESTMQ         kreg|mask,zmmreg,zmmrm512|b64                 [rvm:fv:       evex.nds.512.66.0f38.w1 27 /r ]  AVX512,FUTURE
+VPTESTNMD        kreg|mask,zmmreg,zmmrm512|b32                 [rvm:fv:       evex.nds.512.f3.0f38.w0 27 /r ]  AVX512,FUTURE
+VPTESTNMQ        kreg|mask,zmmreg,zmmrm512|b64                 [rvm:fv:       evex.nds.512.f3.0f38.w1 27 /r ]  AVX512,FUTURE
 VPUNPCKHDQ       zmmreg|mask|z,zmmreg,zmmrm512|b32             [rvm:fv:         evex.nds.512.66.0f.w0 6a /r ]  AVX512,FUTURE
 VPUNPCKHQDQ      zmmreg|mask|z,zmmreg,zmmrm512|b64             [rvm:fv:         evex.nds.512.66.0f.w1 6d /r ]  AVX512,FUTURE
 VPUNPCKLDQ       zmmreg|mask|z,zmmreg,zmmrm512|b32             [rvm:fv:         evex.nds.512.66.0f.w0 62 /r ]  AVX512,FUTURE
@@ -4114,8 +4116,6 @@ VPCONFLICTD      zmmreg|mask|z,zmmrm512|b32      [rm:fv:          evex.512.66.0f
 VPCONFLICTQ      zmmreg|mask|z,zmmrm512|b64      [rm:fv:          evex.512.66.0f38.w1 c4 /r ]  AVX512CD,FUTURE
 VPLZCNTD         zmmreg|mask|z,zmmrm512|b32      [rm:fv:          evex.512.66.0f38.w0 44 /r ]  AVX512CD,FUTURE
 VPLZCNTQ         zmmreg|mask|z,zmmrm512|b64      [rm:fv:          evex.512.66.0f38.w1 44 /r ]  AVX512CD,FUTURE
-VPTESTNMD        kreg|mask,zmmreg,zmmrm512|b32   [rvm:fv:     evex.nds.512.f3.0f38.w0 27 /r ]  AVX512CD,FUTURE
-VPTESTNMQ        kreg|mask,zmmreg,zmmrm512|b64   [rvm:fv:     evex.nds.512.f3.0f38.w1 27 /r ]  AVX512CD,FUTURE
 ; AVX-512ER (Exponential and Reciprocal) instructions
 VEXP2PD      zmmreg|mask|z,zmmrm512|b64|sae    [rm:fv:          evex.512.66.0f38.w1 c8 /r ]  AVX512ER,FUTURE
 VEXP2PS      zmmreg|mask|z,zmmrm512|b32|sae    [rm:fv:          evex.512.66.0f38.w0 c8 /r ]  AVX512ER,FUTURE
-- 
1.7.9.5

[Nasm-devel] [PATCH 2/9] MPX: Adapt GAS's mib syntax with an index reg only

[Jin K. S. <jin...@in...>]

GAS uses *1 multiplier for explicitly marking an index register in mib operand.
e.g.) [rdx * 1 + 3] is equivalent to [3, rdx] in NASM's split EA format
So only for mib operands, this is encoded same as gas does.

Signed-off-by: Jin Kyu Song <jin...@in...>
---
 assemble.c      |   12 ++++++++++++
 test/mpx-64.asm |    8 ++++----
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/assemble.c b/assemble.c
index ddf0af7..2f35cd9 100644
--- a/assemble.c
+++ b/assemble.c
@@ -1205,6 +1205,18 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
                     opy->hinttype = EAH_NOTBASE;
                 }
 
+                /*
+                 * only for mib operands, make a single reg index [reg*1].
+                 * gas uses this form to explicitly denote index register.
+                 */
+                if ((temp->flags & IF_MIB) &&
+                    (opy->indexreg == -1 && opy->hintbase == opy->basereg &&
+                     opy->hinttype == EAH_NOTBASE)) {
+                    opy->indexreg = opy->basereg;
+                    opy->basereg  = -1;
+                    opy->scale    = 1;
+                }
+
                 if (process_ea(opy, &ea_data, bits,
                                rfield, rflags, ins) != eat) {
                     errfunc(ERR_NONFATAL, "invalid effective address");
diff --git a/test/mpx-64.asm b/test/mpx-64.asm
index 50cc4da..bc5e7d4 100644
--- a/test/mpx-64.asm
+++ b/test/mpx-64.asm
@@ -81,16 +81,16 @@ BITS 64
 	bndstx [rax+0x3], bnd0, rbx	; ICC-1
 	bndstx [rax+0x3], rbx, bnd0	; ICC-2
 
-	; GAS's confusing EA - rcx is base reg in NASM
-	bndstx [rcx*1], bnd2
-	; next 4 lines should be parsed same
+	; next 5 lines should be parsed same
 	bndstx [,rcx*1], bnd2		; NASM
 	bndstx [0,rcx*1], bnd2		; NASM
 	bndstx [0], bnd2, rcx		; ICC-1
 	bndstx [0], rcx, bnd2		; ICC-2
+	bndstx [rcx*1], bnd2		; GAS - rcx is encoded as index only when it is mib
 
-	bndstx [1*r12+3], bnd2		; GAS's confusing EA again
+	; next 3 lines should be parsed same
 	bndstx [3,1*r12], bnd2		; NASM
+	bndstx [1*r12+3], bnd2		; GAS
 	bndstx [3], r12, bnd2		; ICC
 
 	bndstx [r12+0x399], bnd3
-- 
1.7.9.5

[Nasm-devel] [PATCH 1/9] REX: Set REX bits in accordance with 32-register environment

[Jin K. S. <jin...@in...>]

REX.RXB bits were set for high-8 registers previously.
Since high-16 zmm registers are newly added, those bits should
be set as one bit of binary number of register value.
Similarly EVEX.R'/V'/X should be set in the same manner.

Authored-by: H. Peter Anvin <hp...@li...>
Signed-off-by: Jin Kyu Song <jin...@in...>
---
 assemble.c |   14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/assemble.c b/assemble.c
index 07e4723..ddf0af7 100644
--- a/assemble.c
+++ b/assemble.c
@@ -1549,9 +1549,9 @@ static void gencode(int32_t segment, int64_t offset, int bits,
             ins->evex_p[2] ^= EVEX_P2VP;        /* 1's complement */
             bytes[0] = 0x62;
             /* EVEX.X can be set by either REX or EVEX for different reasons */
-            bytes[1] = (~(((ins->rex & 7) << 5) |
-                          (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) & 0xf0) |
-                        (ins->vex_cm & 3);
+            bytes[1] = ((((ins->rex & 7) << 5) |
+                         (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
+                       (ins->vex_cm & 3);
             bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
                        ((~ins->vexreg & 15) << 3) |
                        (1 << 2) | (ins->vex_wlp & 3);
@@ -1895,7 +1895,7 @@ static int rexflags(int val, opflags_t flags, int mask)
 {
     int rex = 0;
 
-    if (val >= 8)
+    if (val >= 0 && val & 8)
         rex |= REX_B|REX_X|REX_R;
     if (flags & BITS64)
         rex |= REX_W;
@@ -1912,13 +1912,13 @@ static int evexflags(int val, decoflags_t deco,
 {
     int evex = 0;
 
-    switch(byte) {
+    switch (byte) {
     case 0:
-        if (val >= 16)
+        if (val >= 0 && val & 16)
             evex |= (EVEX_P0RP | EVEX_P0X);
         break;
     case 2:
-        if (val >= 16)
+        if (val >= 0 && val & 16)
             evex |= EVEX_P2VP;
         if (deco & Z)
             evex |= EVEX_P2Z;
-- 
1.7.9.5

[Nasm-devel] [PATCH 0/9] Bug fixes and improvements

[Jin K. S. <jin...@in...>]

A bug which encoded zmm16~23 as zmm24~31 is fixed. Some improvement has
been done for MPX : compatible with gas's mib encoding with no base reg.
There were some changes in CPUID bits for AVX-512 instructions. And in a case
that a user wants to force nasm to encode an instruction in evex,
{evex} prefix is now added.
The logic to match broadcasting operand is improved and now it makes sure
the broadcasting decorator {1to<n>} is correctly written.

All these commits can be pulled from git://repo.or.cz/nasm/avx512.git , too.

Jin Kyu Song (9):
  REX: Set REX bits in accordance with 32-register environment
  MPX: Adapt GAS's mib syntax with an index reg only
  MPX: Move BND prefix indication from bytecode to iflags
  AVX512: Update instruction group
  PREFETCHWT1: Add a new instruction flag
  AVX-512: Add {evex} instruction prefix
  Build: Suppress warning messages
  match: Improve broadcast opsize matching
  match: Check the number of elements in broadcasting operands

 assemble.c      |  111 ++++++++++++++++++++++++++++++++++++++++---------------
 disasm.c        |    7 +---
 insns.dat       |   97 ++++++++++++++++++++++++------------------------
 insns.h         |    2 +
 insns.pl        |    1 -
 nasm.h          |   16 ++++++++
 parser.c        |    7 +++-
 preproc.c       |    2 +-
 test/mpx-64.asm |    8 ++--
 tokens.dat      |    3 ++
 10 files changed, 162 insertions(+), 92 deletions(-)

-- 
1.7.9.5

Re: [Nasm-devel] [nasm:master] make: Remove generated files on clean target

[Cyrill G. <gor...@gm...>]

On Mon, Oct 28, 2013 at 11:34:18AM +0400, Cyrill Gorcunov wrote:
> > 
> > Hmm, maybe add cleanout target which would call clean first and
> > remove generated files as well?
> 
> Ah, I misread your email. I'll move it to spotless then.

I managed to miss that we already have this step in "cleaner"
target. Commit is reverted, thanks for pointing.