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[nasm:master] PREFETCHWT1: Add a new instruction flag
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From: nasm-bot f. J. K. S. <jin...@in...> - 2013-11-21 22:21:29
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Commit-ID: 267d0af79c7de8887ff1618e803cafa5a528a554 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=267d0af79c7de8887ff1618e803cafa5a528a554 Author: Jin Kyu Song <jin...@in...> AuthorDate: Wed, 23 Oct 2013 18:39:03 -0700 Committer: Jin Kyu Song <jin...@in...> CommitDate: Wed, 20 Nov 2013 11:29:42 -0800 PREFETCHWT1: Add a new instruction flag PREFETCHWT1 instruction's CPUID was TBD before. Now it has its new CPUID bit : PREFETCHWT1 Signed-off-by: Jin Kyu Song <jin...@in...> --- insns.dat | 2 +- insns.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/insns.dat b/insns.dat index 202069f..9435e03 100644 --- a/insns.dat +++ b/insns.dat @@ -4146,7 +4146,7 @@ VSCATTERPF1DPD ymem64|mask [m:t1s: vsiby evex.512.66.0f38.w1 c6 /6 ] AVX51 VSCATTERPF1DPS zmem32|mask [m:t1s: vsibz evex.512.66.0f38.w0 c6 /6 ] AVX512PF,FUTURE VSCATTERPF1QPD zmem64|mask [m:t1s: vsibz evex.512.66.0f38.w1 c7 /6 ] AVX512PF,FUTURE VSCATTERPF1QPS zmem32|mask [m:t1s: vsibz evex.512.66.0f38.w0 c7 /6 ] AVX512PF,FUTURE -PREFETCHWT1 mem8 [m: 0f 0d /2 ] FUTURE +PREFETCHWT1 mem8 [m: 0f 0d /2 ] PREFETCHWT1,FUTURE ; MPX instructions BNDMK bndreg,mem32 [rm: o32 f3 0f 1b /r ] MPX,SD,FUTURE diff --git a/insns.h b/insns.h index 0320e8d..dd447c5 100644 --- a/insns.h +++ b/insns.h @@ -135,6 +135,7 @@ extern const uint8_t nasm_bytecodes[]; #define IF_AVX512PF (UINT64_C(0x1800000000)|IF_AVX512) /* AVX-512 Prefetch instructions */ #define IF_MPX UINT64_C(0x1900000000) /* MPX instructions */ #define IF_SHA UINT64_C(0x1A00000000) /* SHA instructions */ +#define IF_PREFETCHWT1 UINT64_C(0x1F00000000) /* PREFETCHWT1 instructions */ #define IF_INSMASK UINT64_C(0xFF00000000) /* the mask for instruction set types */ #define IF_PMASK UINT64_C(0xFF000000) /* the mask for processor types */ #define IF_PLEVEL UINT64_C(0x0F000000) /* the mask for processor instr. level */ |
