[Nasm-devel] [PATCH 00/11] new MPX, SHA instructions

[Jin K. S. <jin...@in...>]

This patch set includes Peter's patches for parsing a new split EA syntax.
- [base + disp, index * scale]

On top of these patches, I implemented MPX assembler. To encode ICC style
mib operand - separate EA : [base + disp], index, a new 'x' operand type is
added in insns.dat. This is for the separate index register.

BND prefix support is also added. I did not know of a case using bnd and jcc8
at the same time. So I left that unresolved. Please let me know if this should
be resolved.

Test cases for MPX and SHA are also included.

H. Peter Anvin (4):
  parser: simplify code by keeping a pointer to the current operand
  parse: factor out mref parsing
  parser: support split base,index effective address
  disasm: add support for emitting split EA format

Jin Kyu Song (7):
  AVX-512: Add perfomtest-compliant headers to test cases
  MPX: Add MPX instructions
  MPX: Add BND prefix for brach instructions
  MPX: Add test cases for MPX
  SHA: Add SHA instructions
  SHA: SHA test cases
  iflags: Use UINT64_C() for 64bit values

 assemble.c        |   36 +++-
 disasm.c          |   22 ++-
 insns.dat         |   84 ++++++++
 insns.h           |  155 +++++++--------
 insns.pl          |    4 +
 nasm.h            |    1 +
 nasmlib.c         |    2 +-
 opflags.h         |    5 +-
 parser.c          |  552 +++++++++++++++++++++++++++++------------------------
 regs.dat          |    3 +
 test/avx512cd.asm |    1 +
 test/avx512er.asm |    1 +
 test/avx512f.asm  |    3 +-
 test/avx512pf.asm |    1 +
 test/mpx-64.asm   |  117 ++++++++++++
 test/mpx.asm      |   85 +++++++++
 test/sha-64.asm   |   31 +++
 test/sha.asm      |   31 +++
 test/splitea.asm  |   11 ++
 tokens.dat        |    1 +
 20 files changed, 814 insertions(+), 332 deletions(-)
 create mode 100644 test/mpx-64.asm
 create mode 100644 test/mpx.asm
 create mode 100644 test/sha-64.asm
 create mode 100644 test/sha.asm
 create mode 100644 test/splitea.asm

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1.7.9.5