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[nasm:avx512] AVX-512: Add Pseudo-ops for CMP instructions
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From: nasm-bot f. J. K. S. <jin...@in...> - 2013-09-21 12:31:07
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Commit-ID: c257bb6ae0d8f88e69a7ef30069aa0f1839de468 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=c257bb6ae0d8f88e69a7ef30069aa0f1839de468 Author: Jin Kyu Song <jin...@in...> AuthorDate: Fri, 6 Sep 2013 21:22:18 -0700 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Sat, 7 Sep 2013 11:50:39 +0400 AVX-512: Add Pseudo-ops for CMP instructions Added three-operand pseudo-ops for VCMPPD, VPCMPD and so on. Test case is also updated to validate them. Signed-off-by: Jin Kyu Song <jin...@in...> Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- insns.dat | 150 ++++ test/avx512f.asm | 2378 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ test/gas2nasm.py | 8 +- 3 files changed, 2531 insertions(+), 5 deletions(-) diff --git a/insns.dat b/insns.dat index 3c9b1ca..ad72d61 100644 --- a/insns.dat +++ b/insns.dat @@ -3478,9 +3478,137 @@ VBROADCASTSD zmmreg|mask|z,mem64 [rm:t1s: VBROADCASTSD zmmreg|mask|z,xmmreg [rm: evex.512.66.0f38.w1 19 /r ] AVX512,FUTURE VBROADCASTSS zmmreg|mask|z,xmmreg [rm: evex.512.66.0f38.w0 18 /r ] AVX512,FUTURE VBROADCASTSS zmmreg|mask|z,mem32 [rm:t1s: evex.512.66.0f38.w0 18 /r ] AVX512,FUTURE +VCMPEQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 00 ] AVX512,FUTURE +VCMPLTPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 01 ] AVX512,FUTURE +VCMPLEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 02 ] AVX512,FUTURE +VCMPUNORDPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 03 ] AVX512,FUTURE +VCMPNEQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 04 ] AVX512,FUTURE +VCMPNLTPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 05 ] AVX512,FUTURE +VCMPNLEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 06 ] AVX512,FUTURE +VCMPORDPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 07 ] AVX512,FUTURE +VCMPEQ_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 08 ] AVX512,FUTURE +VCMPNGEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 09 ] AVX512,FUTURE +VCMPNGTPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 0a ] AVX512,FUTURE +VCMPFALSEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 0b ] AVX512,FUTURE +VCMPNEQ_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 0c ] AVX512,FUTURE +VCMPGEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 0d ] AVX512,FUTURE +VCMPGTPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 0e ] AVX512,FUTURE +VCMPTRUEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 0f ] AVX512,FUTURE +VCMPEQ_OSPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 10 ] AVX512,FUTURE +VCMPLT_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 11 ] AVX512,FUTURE +VCMPLE_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 12 ] AVX512,FUTURE +VCMPUNORD_SPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 13 ] AVX512,FUTURE +VCMPNEQ_USPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 14 ] AVX512,FUTURE +VCMPNLT_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 15 ] AVX512,FUTURE +VCMPNLE_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 16 ] AVX512,FUTURE +VCMPORD_SPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 17 ] AVX512,FUTURE +VCMPEQ_USPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 18 ] AVX512,FUTURE +VCMPNGE_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 19 ] AVX512,FUTURE +VCMPNGT_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 1a ] AVX512,FUTURE +VCMPFALSE_OSPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 1b ] AVX512,FUTURE +VCMPNEQ_OSPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 1c ] AVX512,FUTURE +VCMPGE_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 1d ] AVX512,FUTURE +VCMPGT_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 1e ] AVX512,FUTURE +VCMPTRUE_USPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 c2 /r 1f ] AVX512,FUTURE VCMPPD kreg|mask,zmmreg,zmmrm512|b64|sae,imm8 [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r ib ] AVX512,FUTURE +VCMPEQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 00 ] AVX512,FUTURE +VCMPLTPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 01 ] AVX512,FUTURE +VCMPLEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 02 ] AVX512,FUTURE +VCMPUNORDPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 03 ] AVX512,FUTURE +VCMPNEQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 04 ] AVX512,FUTURE +VCMPNLTPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 05 ] AVX512,FUTURE +VCMPNLEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 06 ] AVX512,FUTURE +VCMPORDPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 07 ] AVX512,FUTURE +VCMPEQ_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 08 ] AVX512,FUTURE +VCMPNGEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 09 ] AVX512,FUTURE +VCMPNGTPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 0a ] AVX512,FUTURE +VCMPFALSEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 0b ] AVX512,FUTURE +VCMPNEQ_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 0c ] AVX512,FUTURE +VCMPGEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 0d ] AVX512,FUTURE +VCMPGTPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 0e ] AVX512,FUTURE +VCMPTRUEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 0f ] AVX512,FUTURE +VCMPEQ_OSPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 10 ] AVX512,FUTURE +VCMPLT_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 11 ] AVX512,FUTURE +VCMPLE_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 12 ] AVX512,FUTURE +VCMPUNORD_SPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 13 ] AVX512,FUTURE +VCMPNEQ_USPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 14 ] AVX512,FUTURE +VCMPNLT_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 15 ] AVX512,FUTURE +VCMPNLE_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 16 ] AVX512,FUTURE +VCMPORD_SPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 17 ] AVX512,FUTURE +VCMPEQ_USPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 18 ] AVX512,FUTURE +VCMPNGE_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 19 ] AVX512,FUTURE +VCMPNGT_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 1a ] AVX512,FUTURE +VCMPFALSE_OSPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 1b ] AVX512,FUTURE +VCMPNEQ_OSPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 1c ] AVX512,FUTURE +VCMPGE_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 1d ] AVX512,FUTURE +VCMPGT_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 1e ] AVX512,FUTURE +VCMPTRUE_USPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 c2 /r 1f ] AVX512,FUTURE VCMPPS kreg|mask,zmmreg,zmmrm512|b32|sae,imm8 [rvmi:fv: evex.nds.512.0f.w0 c2 /r ib ] AVX512,FUTURE +VCMPEQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 00 ] AVX512,FUTURE +VCMPLTSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 01 ] AVX512,FUTURE +VCMPLESD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 02 ] AVX512,FUTURE +VCMPUNORDSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 03 ] AVX512,FUTURE +VCMPNEQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 04 ] AVX512,FUTURE +VCMPNLTSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 05 ] AVX512,FUTURE +VCMPNLESD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 06 ] AVX512,FUTURE +VCMPORDSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 07 ] AVX512,FUTURE +VCMPEQ_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 08 ] AVX512,FUTURE +VCMPNGESD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 09 ] AVX512,FUTURE +VCMPNGTSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0a ] AVX512,FUTURE +VCMPFALSESD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0b ] AVX512,FUTURE +VCMPNEQ_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0c ] AVX512,FUTURE +VCMPGESD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0d ] AVX512,FUTURE +VCMPGTSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0e ] AVX512,FUTURE +VCMPTRUESD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0f ] AVX512,FUTURE +VCMPEQ_OSSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 10 ] AVX512,FUTURE +VCMPLT_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 11 ] AVX512,FUTURE +VCMPLE_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 12 ] AVX512,FUTURE +VCMPUNORD_SSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 13 ] AVX512,FUTURE +VCMPNEQ_USSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 14 ] AVX512,FUTURE +VCMPNLT_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 15 ] AVX512,FUTURE +VCMPNLE_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 16 ] AVX512,FUTURE +VCMPORD_SSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 17 ] AVX512,FUTURE +VCMPEQ_USSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 18 ] AVX512,FUTURE +VCMPNGE_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 19 ] AVX512,FUTURE +VCMPNGT_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 1a ] AVX512,FUTURE +VCMPFALSE_OSSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 1b ] AVX512,FUTURE +VCMPNEQ_OSSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 1c ] AVX512,FUTURE +VCMPGE_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 1d ] AVX512,FUTURE +VCMPGT_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 1e ] AVX512,FUTURE +VCMPTRUE_USSD kreg|mask,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.lig.f2.0f.w1 c2 /r 1f ] AVX512,FUTURE VCMPSD kreg|mask,xmmreg,xmmrm64|sae,imm8 [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r ib ] AVX512,FUTURE +VCMPEQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 00 ] AVX512,FUTURE +VCMPLTSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 01 ] AVX512,FUTURE +VCMPLESS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 02 ] AVX512,FUTURE +VCMPUNORDSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 03 ] AVX512,FUTURE +VCMPNEQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 04 ] AVX512,FUTURE +VCMPNLTSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 05 ] AVX512,FUTURE +VCMPNLESS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 06 ] AVX512,FUTURE +VCMPORDSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 07 ] AVX512,FUTURE +VCMPEQ_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 08 ] AVX512,FUTURE +VCMPNGESS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 09 ] AVX512,FUTURE +VCMPNGTSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0a ] AVX512,FUTURE +VCMPFALSESS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0b ] AVX512,FUTURE +VCMPNEQ_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0c ] AVX512,FUTURE +VCMPGESS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0d ] AVX512,FUTURE +VCMPGTSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0e ] AVX512,FUTURE +VCMPTRUESS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0f ] AVX512,FUTURE +VCMPEQ_OSSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 10 ] AVX512,FUTURE +VCMPLT_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 11 ] AVX512,FUTURE +VCMPLE_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 12 ] AVX512,FUTURE +VCMPUNORD_SSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 13 ] AVX512,FUTURE +VCMPNEQ_USSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 14 ] AVX512,FUTURE +VCMPNLT_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 15 ] AVX512,FUTURE +VCMPNLE_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 16 ] AVX512,FUTURE +VCMPORD_SSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 17 ] AVX512,FUTURE +VCMPEQ_USSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 18 ] AVX512,FUTURE +VCMPNGE_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 19 ] AVX512,FUTURE +VCMPNGT_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 1a ] AVX512,FUTURE +VCMPFALSE_OSSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 1b ] AVX512,FUTURE +VCMPNEQ_OSSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 1c ] AVX512,FUTURE +VCMPGE_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 1d ] AVX512,FUTURE +VCMPGT_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 1e ] AVX512,FUTURE +VCMPTRUE_USSS kreg|mask,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 c2 /r 1f ] AVX512,FUTURE VCMPSS kreg|mask,xmmreg,xmmrm32|sae,imm8 [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r ib ] AVX512,FUTURE VCOMISD xmmreg,xmmrm64|sae [rm:t1s: evex.lig.66.0f.w1 2f /r ] AVX512,FUTURE VCOMISS xmmreg,xmmrm32|sae [rm:t1s: evex.lig.0f.w0 2f /r ] AVX512,FUTURE @@ -3713,13 +3841,35 @@ VPBROADCASTD zmmreg|mask|z,reg32 [rm: VPBROADCASTQ zmmreg|mask|z,xmmreg [rm: evex.512.66.0f38.w1 59 /r ] AVX512,FUTURE VPBROADCASTQ zmmreg|mask|z,mem64 [rm:t1s: evex.512.66.0f38.w1 59 /r ] AVX512,FUTURE VPBROADCASTQ zmmreg|mask|z,reg64 [rm: evex.512.66.0f38.w1 7c /r ] AVX512,FUTURE +VPCMPLTD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1f /r 01 ] AVX512,FUTURE +VPCMPLED kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1f /r 02 ] AVX512,FUTURE +VPCMPNEQD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1f /r 04 ] AVX512,FUTURE +VPCMPNLTD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1f /r 05 ] AVX512,FUTURE +VPCMPNLED kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1f /r 06 ] AVX512,FUTURE VPCMPD kreg|mask,zmmreg,zmmrm512|b32,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 1f /r ib ] AVX512,FUTURE VPCMPEQD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 76 /r ] AVX512,FUTURE VPCMPEQQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 29 /r ] AVX512,FUTURE VPCMPGTD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 66 /r ] AVX512,FUTURE VPCMPGTQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 37 /r ] AVX512,FUTURE +VPCMPLTQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1f /r 01 ] AVX512,FUTURE +VPCMPLEQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1f /r 02 ] AVX512,FUTURE +VPCMPNEQQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1f /r 04 ] AVX512,FUTURE +VPCMPNLTQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1f /r 05 ] AVX512,FUTURE +VPCMPNLEQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1f /r 06 ] AVX512,FUTURE VPCMPQ kreg|mask,zmmreg,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 1f /r ib ] AVX512,FUTURE +VPCMPEQUD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1e /r 00 ] AVX512,FUTURE +VPCMPLTUD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1e /r 01 ] AVX512,FUTURE +VPCMPLEUD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1e /r 02 ] AVX512,FUTURE +VPCMPNEQUD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1e /r 04 ] AVX512,FUTURE +VPCMPNLTUD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1e /r 05 ] AVX512,FUTURE +VPCMPNLEUD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f3a.w0 1e /r 06 ] AVX512,FUTURE VPCMPUD kreg|mask,zmmreg,zmmrm512|b32,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 1e /r ib ] AVX512,FUTURE +VPCMPEQUQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1e /r 00 ] AVX512,FUTURE +VPCMPLTUQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1e /r 01 ] AVX512,FUTURE +VPCMPLEUQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1e /r 02 ] AVX512,FUTURE +VPCMPNEQUQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1e /r 04 ] AVX512,FUTURE +VPCMPNLTUQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1e /r 05 ] AVX512,FUTURE +VPCMPNLEUQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f3a.w1 1e /r 06 ] AVX512,FUTURE VPCMPUQ kreg|mask,zmmreg,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 1e /r ib ] AVX512,FUTURE VPCOMPRESSD zmmreg|mask|z,zmmreg [mr: evex.512.66.0f38.w0 8b /r ] AVX512,FUTURE VPCOMPRESSD mem512|mask,zmmreg [mr:t1s: evex.512.66.0f38.w0 8b /r ] AVX512,FUTURE diff --git a/test/avx512f.asm b/test/avx512f.asm index 3dcae37..282dbea 100644 --- a/test/avx512f.asm +++ b/test/avx512f.asm @@ -190,6 +190,650 @@ testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x7b testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x7b }, { vcmppd k5,zmm30,QWORD [rdx+0x400]\{1to8\},0x7b } testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x7b }, { vcmppd k5,zmm30,QWORD [rdx-0x400]\{1to8\},0x7b } testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x7b }, { vcmppd k5,zmm30,QWORD [rdx-0x408]\{1to8\},0x7b } +testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x00 }, { vcmpeqpd k5,zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x00 }, { vcmpeqpd k5\{k7\},zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x00 }, { vcmpeqpd k5,zmm30,zmm29,\{sae\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rcx] } +testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rax+r14*8+0x123] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x00 }, { vcmpeqpd k5,zmm30,QWORD [rcx]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rdx+0x1fc0] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rdx+0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rdx-0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rdx-0x2040] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x00 }, { vcmpeqpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x00 }, { vcmpeqpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x00 }, { vcmpeqpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x00 }, { vcmpeqpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} } +testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x00 }, { vcmpeqpd k5,zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x00 }, { vcmpeqpd k5\{k7\},zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x00 }, { vcmpeqpd k5,zmm30,zmm29,\{sae\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rcx] } +testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rax+r14*8+0x123] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x00 }, { vcmpeqpd k5,zmm30,QWORD [rcx]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rdx+0x1fc0] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rdx+0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rdx-0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x00 }, { vcmpeqpd k5,zmm30,ZWORD [rdx-0x2040] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x00 }, { vcmpeqpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x00 }, { vcmpeqpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x00 }, { vcmpeqpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x00 }, { vcmpeqpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} } +testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x01 }, { vcmpltpd k5,zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x01 }, { vcmpltpd k5\{k7\},zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x01 }, { vcmpltpd k5,zmm30,zmm29,\{sae\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rcx] } +testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rax+r14*8+0x123] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x01 }, { vcmpltpd k5,zmm30,QWORD [rcx]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rdx+0x1fc0] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rdx+0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rdx-0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rdx-0x2040] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x01 }, { vcmpltpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x01 }, { vcmpltpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x01 }, { vcmpltpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x01 }, { vcmpltpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} } +testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x01 }, { vcmpltpd k5,zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x01 }, { vcmpltpd k5\{k7\},zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x01 }, { vcmpltpd k5,zmm30,zmm29,\{sae\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rcx] } +testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rax+r14*8+0x123] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x01 }, { vcmpltpd k5,zmm30,QWORD [rcx]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rdx+0x1fc0] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rdx+0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rdx-0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x01 }, { vcmpltpd k5,zmm30,ZWORD [rdx-0x2040] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x01 }, { vcmpltpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x01 }, { vcmpltpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x01 }, { vcmpltpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x01 }, { vcmpltpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} } +testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x02 }, { vcmplepd k5,zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x02 }, { vcmplepd k5\{k7\},zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x02 }, { vcmplepd k5,zmm30,zmm29,\{sae\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rcx] } +testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rax+r14*8+0x123] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x02 }, { vcmplepd k5,zmm30,QWORD [rcx]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rdx+0x1fc0] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rdx+0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rdx-0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rdx-0x2040] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x02 }, { vcmplepd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x02 }, { vcmplepd k5,zmm30,QWORD [rdx+0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x02 }, { vcmplepd k5,zmm30,QWORD [rdx-0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x02 }, { vcmplepd k5,zmm30,QWORD [rdx-0x408]\{1to8\} } +testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x02 }, { vcmplepd k5,zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x02 }, { vcmplepd k5\{k7\},zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x02 }, { vcmplepd k5,zmm30,zmm29,\{sae\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rcx] } +testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rax+r14*8+0x123] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x02 }, { vcmplepd k5,zmm30,QWORD [rcx]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rdx+0x1fc0] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rdx+0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rdx-0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x02 }, { vcmplepd k5,zmm30,ZWORD [rdx-0x2040] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x02 }, { vcmplepd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x02 }, { vcmplepd k5,zmm30,QWORD [rdx+0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x02 }, { vcmplepd k5,zmm30,QWORD [rdx-0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x02 }, { vcmplepd k5,zmm30,QWORD [rdx-0x408]\{1to8\} } +testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x03 }, { vcmpunordpd k5,zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x03 }, { vcmpunordpd k5\{k7\},zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x03 }, { vcmpunordpd k5,zmm30,zmm29,\{sae\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rcx] } +testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rax+r14*8+0x123] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x03 }, { vcmpunordpd k5,zmm30,QWORD [rcx]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rdx+0x1fc0] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rdx+0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rdx-0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rdx-0x2040] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x03 }, { vcmpunordpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x03 }, { vcmpunordpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x03 }, { vcmpunordpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x03 }, { vcmpunordpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} } +testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x03 }, { vcmpunordpd k5,zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x03 }, { vcmpunordpd k5\{k7\},zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x03 }, { vcmpunordpd k5,zmm30,zmm29,\{sae\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rcx] } +testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rax+r14*8+0x123] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x03 }, { vcmpunordpd k5,zmm30,QWORD [rcx]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rdx+0x1fc0] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rdx+0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rdx-0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x03 }, { vcmpunordpd k5,zmm30,ZWORD [rdx-0x2040] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x03 }, { vcmpunordpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x03 }, { vcmpunordpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x03 }, { vcmpunordpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x03 }, { vcmpunordpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} } +testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x04 }, { vcmpneqpd k5,zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x04 }, { vcmpneqpd k5\{k7\},zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x04 }, { vcmpneqpd k5,zmm30,zmm29,\{sae\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rcx] } +testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rax+r14*8+0x123] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x04 }, { vcmpneqpd k5,zmm30,QWORD [rcx]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rdx+0x1fc0] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rdx+0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rdx-0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rdx-0x2040] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x04 }, { vcmpneqpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x04 }, { vcmpneqpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x04 }, { vcmpneqpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x04 }, { vcmpneqpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} } +testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x04 }, { vcmpneqpd k5,zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x04 }, { vcmpneqpd k5\{k7\},zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x04 }, { vcmpneqpd k5,zmm30,zmm29,\{sae\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rcx] } +testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rax+r14*8+0x123] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x04 }, { vcmpneqpd k5,zmm30,QWORD [rcx]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rdx+0x1fc0] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rdx+0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rdx-0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x04 }, { vcmpneqpd k5,zmm30,ZWORD [rdx-0x2040] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x04 }, { vcmpneqpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x04 }, { vcmpneqpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x04 }, { vcmpneqpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x04 }, { vcmpneqpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} } +testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x05 }, { vcmpnltpd k5,zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x05 }, { vcmpnltpd k5\{k7\},zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x05 }, { vcmpnltpd k5,zmm30,zmm29,\{sae\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rcx] } +testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rax+r14*8+0x123] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x05 }, { vcmpnltpd k5,zmm30,QWORD [rcx]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rdx+0x1fc0] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rdx+0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rdx-0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rdx-0x2040] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x05 }, { vcmpnltpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x05 }, { vcmpnltpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x05 }, { vcmpnltpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x05 }, { vcmpnltpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} } +testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x05 }, { vcmpnltpd k5,zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x05 }, { vcmpnltpd k5\{k7\},zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x05 }, { vcmpnltpd k5,zmm30,zmm29,\{sae\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rcx] } +testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rax+r14*8+0x123] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x05 }, { vcmpnltpd k5,zmm30,QWORD [rcx]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rdx+0x1fc0] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rdx+0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rdx-0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x05 }, { vcmpnltpd k5,zmm30,ZWORD [rdx-0x2040] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x05 }, { vcmpnltpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x05 }, { vcmpnltpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x05 }, { vcmpnltpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x05 }, { vcmpnltpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} } +testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x06 }, { vcmpnlepd k5,zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x06 }, { vcmpnlepd k5\{k7\},zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x06 }, { vcmpnlepd k5,zmm30,zmm29,\{sae\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rcx] } +testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rax+r14*8+0x123] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x06 }, { vcmpnlepd k5,zmm30,QWORD [rcx]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rdx+0x1fc0] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rdx+0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rdx-0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rdx-0x2040] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x06 }, { vcmpnlepd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x06 }, { vcmpnlepd k5,zmm30,QWORD [rdx+0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x06 }, { vcmpnlepd k5,zmm30,QWORD [rdx-0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x06 }, { vcmpnlepd k5,zmm30,QWORD [rdx-0x408]\{1to8\} } +testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x06 }, { vcmpnlepd k5,zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x06 }, { vcmpnlepd k5\{k7\},zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x06 }, { vcmpnlepd k5,zmm30,zmm29,\{sae\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rcx] } +testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rax+r14*8+0x123] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x06 }, { vcmpnlepd k5,zmm30,QWORD [rcx]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rdx+0x1fc0] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rdx+0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rdx-0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x06 }, { vcmpnlepd k5,zmm30,ZWORD [rdx-0x2040] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x06 }, { vcmpnlepd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x06 }, { vcmpnlepd k5,zmm30,QWORD [rdx+0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x06 }, { vcmpnlepd k5,zmm30,QWORD [rdx-0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x06 }, { vcmpnlepd k5,zmm30,QWORD [rdx-0x408]\{1to8\} } +testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x07 }, { vcmpordpd k5,zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x07 }, { vcmpordpd k5\{k7\},zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x07 }, { vcmpordpd k5,zmm30,zmm29,\{sae\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rcx] } +testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rax+r14*8+0x123] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x07 }, { vcmpordpd k5,zmm30,QWORD [rcx]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rdx+0x1fc0] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rdx+0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rdx-0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rdx-0x2040] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x07 }, { vcmpordpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x07 }, { vcmpordpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x07 }, { vcmpordpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x07 }, { vcmpordpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} } +testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x07 }, { vcmpordpd k5,zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x07 }, { vcmpordpd k5\{k7\},zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x07 }, { vcmpordpd k5,zmm30,zmm29,\{sae\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rcx] } +testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rax+r14*8+0x123] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x07 }, { vcmpordpd k5,zmm30,QWORD [rcx]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rdx+0x1fc0] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rdx+0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rdx-0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x07 }, { vcmpordpd k5,zmm30,ZWORD [rdx-0x2040] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x07 }, { vcmpordpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x07 }, { vcmpordpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x07 }, { vcmpordpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x07 }, { vcmpordpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} } +testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x08 }, { vcmpeq_uqpd k5,zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x08 }, { vcmpeq_uqpd k5\{k7\},zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x08 }, { vcmpeq_uqpd k5,zmm30,zmm29,\{sae\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x08 }, { vcmpeq_uqpd k5,zmm30,ZWORD [rcx] } +testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x08 }, { vcmpeq_uqpd k5,zmm30,ZWORD [rax+r14*8+0x123] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x08 }, { vcmpeq_uqpd k5,zmm30,QWORD [rcx]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x08 }, { vcmpeq_uqpd k5,zmm30,ZWORD [rdx+0x1fc0] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x08 }, { vcmpeq_uqpd k5,zmm30,ZWORD [rdx+0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x08 }, { vcmpeq_uqpd k5,zmm30,ZWORD [rdx-0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0xc0, 0xdf, 0xff, 0xff, 0x08 }, { vcmpeq_uqpd k5,zmm30,ZWORD [rdx-0x2040] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x7f, 0x08 }, { vcmpeq_uqpd k5,zmm30,QWORD [rdx+0x3f8]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0x00, 0x04, 0x00, 0x00, 0x08 }, { vcmpeq_uqpd k5,zmm30,QWORD [rdx+0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x6a, 0x80, 0x08 }, { vcmpeq_uqpd k5,zmm30,QWORD [rdx-0x400]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0xaa, 0xf8, 0xfb, 0xff, 0xff, 0x08 }, { vcmpeq_uqpd k5,zmm30,QWORD [rdx-0x408]\{1to8\} } +testcase { 0x62, 0x91, 0x8d, 0x40, 0xc2, 0xed, 0x09 }, { vcmpngepd k5,zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x47, 0xc2, 0xed, 0x09 }, { vcmpngepd k5\{k7\},zmm30,zmm29 } +testcase { 0x62, 0x91, 0x8d, 0x10, 0xc2, 0xed, 0x09 }, { vcmpngepd k5,zmm30,zmm29,\{sae\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x29, 0x09 }, { vcmpngepd k5,zmm30,ZWORD [rcx] } +testcase { 0x62, 0xb1, 0x8d, 0x40, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x09 }, { vcmpngepd k5,zmm30,ZWORD [rax+r14*8+0x123] } +testcase { 0x62, 0xf1, 0x8d, 0x50, 0xc2, 0x29, 0x09 }, { vcmpngepd k5,zmm30,QWORD [rcx]\{1to8\} } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x7f, 0x09 }, { vcmpngepd k5,zmm30,ZWORD [rdx+0x1fc0] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0xaa, 0x00, 0x20, 0x00, 0x00, 0x09 }, { vcmpngepd k5,zmm30,ZWORD [rdx+0x2000] } +testcase { 0x62, 0xf1, 0x8d, 0x40, 0xc2, 0x6a, 0x80, 0x09 }, { vcmpngepd k5,zmm30,ZWORD [rdx-0x2000] } +testcase { 0x62,... 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