[nasm:avx512] AVX-512: Add IF_SPMASK and fix IF_PFMASK

[nasm-bot f. J. K. S. <jin...@in...>]

Commit-ID:  b21f97db0e5dc785092ec168b0bacd4d1f6ddfce
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=b21f97db0e5dc785092ec168b0bacd4d1f6ddfce
Author:     Jin Kyu Song <jin...@in...>
AuthorDate: Wed, 28 Aug 2013 19:15:26 -0700
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Thu, 29 Aug 2013 10:03:19 +0400

AVX-512: Add IF_SPMASK and fix IF_PFMASK

Defined IF_SPMASK for specific processor types and
fixed IF_PFMASK to mask the exact preferred bits only.

Signed-off-by: Jin Kyu Song <jin...@in...>
Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 insns.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/insns.h b/insns.h
index ad795e2..19b27ae 100644
--- a/insns.h
+++ b/insns.h
@@ -132,7 +132,6 @@ extern const uint8_t nasm_bytecodes[];
 #define IF_PMASK        0xFF000000UL    /* the mask for processor types */
 #define IF_PLEVEL       0x0F000000UL    /* the mask for processor instr. level */
                                         /* also the highest possible processor */
-#define IF_PFMASK       0xFFF0000000UL    /* the mask for disassembly "prefer" */
 #define IF_8086         0x00000000UL    /* 8086 instruction */
 #define IF_186          0x01000000UL    /* 186+ instruction */
 #define IF_286          0x02000000UL    /* 286+ instruction */
@@ -152,5 +151,7 @@ extern const uint8_t nasm_bytecodes[];
 #define IF_IA64         0x0F000000UL    /* IA64 instructions (in x86 mode) */
 #define IF_CYRIX        0x10000000UL    /* Cyrix-specific instruction */
 #define IF_AMD          0x20000000UL    /* AMD-specific instruction */
+#define IF_SPMASK       0x30000000UL    /* specific processor types mask */
+#define IF_PFMASK       (IF_INSMASK|IF_SPMASK) /* disassembly "prefer" mask */
 
 #endif /* NASM_INSNS_H */