Re: [Nasm-devel] [PATCH 6/7] AVX-512: Change the data type for instruction flags

[anonymous c. <nas...@us...>]

>> PTEST and ROUND[PS|PD|SS|SD] were part of SSE4.1 and SSE5A.
> Thanks for letting me know. NASM does not have a definition of SSE5A though.
> Is NASM missing SSE5A intentionally?

AMD decided not to ship SSE5A in the end.

(I merely cited it as an example for instructions that
were part of more than one extension or feature.)

> So do you suggest make them all bit masks to lift this kind of limitation
> (prohibiting two different types)? Since it became 64bit, there are enough
> space for now. But I worried the case that it runs out quickly.

You already need more than 64 bits to properly map
all existing instructions to their CPUID features (and
in some case you will need to make up a flag, since
CPUID lacks a few of them, e.g. hinting NOPs, hints
for branches, PAUSE, etc.).

So instead of just widening from 32 to 64 bits, you'll
need a real bit vector, with more than 64 bits.

Also, this would be a change that you would want to
make on the main tree, not the AVX-512 branch.