[nasm:nasm-2.09.xx] insns: VLDQQU is back

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  79abe7a73126d51047d0715469264bb55ccca845
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=79abe7a73126d51047d0715469264bb55ccca845
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Wed, 23 Feb 2011 00:41:43 +0300
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Wed, 23 Feb 2011 00:41:43 +0300

insns: VLDQQU is back

As HPA explained
|
| w.r.t. the -QQ- instruction forms... when we did
| the initial AVX implementation we decided that
| using -DQ- (double quadword) for 256-bit instructions
| was a bit messy, so we decided to accept both -DQ-
| (being official) and -QQ-
|

So move VLDQQU back and place it before VLDDQU so disassembler
match it first.

Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 insns.dat |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/insns.dat b/insns.dat
index f8a8269..76a5a1d 100644
--- a/insns.dat
+++ b/insns.dat
@@ -2334,6 +2334,7 @@ VHSUBPS		ymmreg,ymmreg*,ymmrm256		[rvm:	vex.nds.256.f2.0f 7d /r]		AVX,SANDYBRIDG
 VINSERTF128	ymmreg,ymmreg,xmmrm128,imm8	[rvmi:	vex.nds.256.66.0f3a.w0 18 /r ib]	AVX,SANDYBRIDGE
 VINSERTPS	xmmreg,xmmreg*,xmmrm32,imm8	[rvmi:	vex.nds.128.66.0f3a 21 /r ib]		AVX,SANDYBRIDGE
 VLDDQU		xmmreg,mem128			[rm:	vex.128.f2.0f f0 /r]			AVX,SANDYBRIDGE
+VLDQQU		ymmreg,mem256			[rm:	vex.256.f2.0f f0 /r]			AVX,SANDYBRIDGE
 VLDDQU		ymmreg,mem256			[rm:	vex.256.f2.0f f0 /r]			AVX,SANDYBRIDGE
 VLDMXCSR	mem32				[m:	vex.lz.0f ae /2]			AVX,SANDYBRIDGE
 VMASKMOVDQU	xmmreg,xmmreg			[rm:	vex.128.66.0f f7 /r]			AVX,SANDYBRIDGE